Tom Rini
10 years ago
commit
d51aae6423
@ -0,0 +1,14 @@ |
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/*
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* Renesas SuperH MMCIF driver. |
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* |
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* Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
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* Copyright (C) 2014 Renesas Electronics Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef _RMOBILE_MMC_H_ |
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#define _RMOBILE_MMC_H_ |
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int mmcif_mmc_init(void); |
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#endif /* _RMOBILE_MMC_H_ */ |
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@ -0,0 +1,109 @@ |
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/*
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* arch/arm/include/asm/arch-rmobile/rcar-mstp.h |
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* |
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* Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
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* Copyright (C) 2013, 2014 Renesas Electronics Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef __ASM_ARCH_RCAR_MSTP_H |
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#define __ASM_ARCH_RCAR_MSTP_H |
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#define mstp_setbits(type, addr, saddr, set) \ |
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out_##type((saddr), in_##type(addr) | (set)) |
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#define mstp_clrbits(type, addr, saddr, clear) \ |
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out_##type((saddr), in_##type(addr) & ~(clear)) |
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#define mstp_setclrbits(type, addr, set, clear) \ |
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out_##type((addr), (in_##type(addr) | (set)) & ~(clear)) |
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#define mstp_setbits_le32(addr, saddr, set) \ |
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mstp_setbits(le32, addr, saddr, set) |
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#define mstp_clrbits_le32(addr, saddr, clear) \ |
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mstp_clrbits(le32, addr, saddr, clear) |
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#define mstp_setclrbits_le32(addr, set, clear) \ |
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mstp_setclrbits(le32, addr, set, clear) |
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#ifndef CONFIG_SMSTP0_ENA |
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#define CONFIG_SMSTP0_ENA 0x00 |
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#endif |
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#ifndef CONFIG_SMSTP1_ENA |
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#define CONFIG_SMSTP1_ENA 0x00 |
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#endif |
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#ifndef CONFIG_SMSTP2_ENA |
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#define CONFIG_SMSTP2_ENA 0x00 |
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#endif |
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#ifndef CONFIG_SMSTP3_ENA |
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#define CONFIG_SMSTP3_ENA 0x00 |
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#endif |
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#ifndef CONFIG_SMSTP4_ENA |
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#define CONFIG_SMSTP4_ENA 0x00 |
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#endif |
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#ifndef CONFIG_SMSTP5_ENA |
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#define CONFIG_SMSTP5_ENA 0x00 |
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#endif |
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#ifndef CONFIG_SMSTP6_ENA |
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#define CONFIG_SMSTP6_ENA 0x00 |
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#endif |
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#ifndef CONFIG_SMSTP7_ENA |
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#define CONFIG_SMSTP7_ENA 0x00 |
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#endif |
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#ifndef CONFIG_SMSTP8_ENA |
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#define CONFIG_SMSTP8_ENA 0x00 |
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#endif |
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#ifndef CONFIG_SMSTP9_ENA |
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#define CONFIG_SMSTP9_ENA 0x00 |
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#endif |
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#ifndef CONFIG_SMSTP10_ENA |
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#define CONFIG_SMSTP10_ENA 0x00 |
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#endif |
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#ifndef CONFIG_SMSTP11_ENA |
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#define CONFIG_SMSTP11_ENA 0x00 |
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#endif |
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#ifndef CONFIG_RMSTP0_ENA |
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#define CONFIG_RMSTP0_ENA 0x00 |
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#endif |
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#ifndef CONFIG_RMSTP1_ENA |
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#define CONFIG_RMSTP1_ENA 0x00 |
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#endif |
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#ifndef CONFIG_RMSTP2_ENA |
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#define CONFIG_RMSTP2_ENA 0x00 |
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#endif |
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#ifndef CONFIG_RMSTP3_ENA |
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#define CONFIG_RMSTP3_ENA 0x00 |
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#endif |
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#ifndef CONFIG_RMSTP4_ENA |
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#define CONFIG_RMSTP4_ENA 0x00 |
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#endif |
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#ifndef CONFIG_RMSTP5_ENA |
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#define CONFIG_RMSTP5_ENA 0x00 |
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#endif |
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#ifndef CONFIG_RMSTP6_ENA |
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#define CONFIG_RMSTP6_ENA 0x00 |
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#endif |
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#ifndef CONFIG_RMSTP7_ENA |
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#define CONFIG_RMSTP7_ENA 0x00 |
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#endif |
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#ifndef CONFIG_RMSTP8_ENA |
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#define CONFIG_RMSTP8_ENA 0x00 |
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#endif |
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#ifndef CONFIG_RMSTP9_ENA |
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#define CONFIG_RMSTP9_ENA 0x00 |
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#endif |
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#ifndef CONFIG_RMSTP10_ENA |
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#define CONFIG_RMSTP10_ENA 0x00 |
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#endif |
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#ifndef CONFIG_RMSTP11_ENA |
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#define CONFIG_RMSTP11_ENA 0x00 |
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#endif |
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struct mstp_ctl { |
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u32 s_addr; |
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u32 s_dis; |
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u32 s_ena; |
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u32 r_addr; |
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u32 r_dis; |
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u32 r_ena; |
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}; |
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#endif /* __ASM_ARCH_RCAR_MSTP_H */ |
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@ -0,0 +1,59 @@ |
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/*
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* board/renesas/rcar-gen2-common/common.c |
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* |
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* Copyright (C) 2013 Renesas Electronics Corporation |
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* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/rmobile.h> |
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#include <asm/arch/rcar-mstp.h> |
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#define TSTR0 0x04 |
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#define TSTR0_STR0 0x01 |
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static struct mstp_ctl mstptbl[] = { |
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{ SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA, |
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RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA }, |
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{ SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA, |
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RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA }, |
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{ SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA, |
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RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA }, |
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{ SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA, |
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RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA }, |
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{ SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA, |
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RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA }, |
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{ SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA, |
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RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA }, |
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/* No MSTP6 */ |
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{ SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA, |
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RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA }, |
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{ SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA, |
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RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA }, |
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{ SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA, |
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RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA }, |
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{ SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA, |
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RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA }, |
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{ SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA, |
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RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA }, |
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}; |
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void arch_preboot_os(void) |
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{ |
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int i; |
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/* stop TMU0 */ |
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mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0); |
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/* Stop module clock */ |
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for (i = 0; i < ARRAY_SIZE(mstptbl); i++) { |
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mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis, |
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mstptbl[i].s_ena); |
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mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis, |
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mstptbl[i].r_ena); |
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} |
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} |
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