Convert pico-imx7d to SPL support. There are two variants of pico-imx7d SOMs: - One with 512MB of RAM - One with 1GB of RAM The 512MB module contains two Hynix H5TC2G63GFR-PBA. The 1GB module contains two Hynix H5TC4G63GFR-PBA. The RAM size is determined in runtime by reading GPIO1_12. While at it, also add USB Serial Download mode support as it is very helpful for loading SPL and u-boot.img via imx_usb_loader. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>lime2-spi
Fabio Estevam
6 years ago
committed by
Stefano Babic
parent
3fbbfed7a8
commit
d5b7177f91
@ -1,4 +1,4 @@ |
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# SPDX-License-Identifier: GPL-2.0+
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# (C) Copyright 2017 NXP Semiconductors
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obj-y := pico-imx7d.o
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obj-y := pico-imx7d.o spl.o
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@ -1,97 +0,0 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/* |
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* Copyright (C) 2017 Freescale Semiconductor, Inc. |
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* |
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* Refer docs/README.imxmage for more details about how-to configure |
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* and create imximage boot image |
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* |
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* The syntax is taken as close as possible with the kwbimage |
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*/ |
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#define __ASSEMBLY__ |
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#include <config.h> |
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/* image version */ |
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IMAGE_VERSION 2 |
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BOOT_FROM sd |
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/* Secure boot support */ |
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#ifdef CONFIG_SECURE_BOOT |
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CSF CONFIG_CSF_SIZE |
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#endif |
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/* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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DATA 4 0x30340004 0x4F400005 |
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/* Clear then set bit30 to ensure exit from DDR retention */ |
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DATA 4 0x30360388 0x40000000 |
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DATA 4 0x30360384 0x40000000 |
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DATA 4 0x30391000 0x00000002 |
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DATA 4 0x307a0000 0x01040001 |
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DATA 4 0x307a01a0 0x80400003 |
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DATA 4 0x307a01a4 0x00100020 |
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DATA 4 0x307a01a8 0x80100004 |
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DATA 4 0x307a0064 0x00400046 |
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DATA 4 0x307a0490 0x00000001 |
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DATA 4 0x307a00d0 0x00020083 |
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DATA 4 0x307a00d4 0x00690000 |
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DATA 4 0x307a00dc 0x09300004 |
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DATA 4 0x307a00e0 0x04080000 |
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DATA 4 0x307a00e4 0x00100004 |
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DATA 4 0x307a00f4 0x0000033f |
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DATA 4 0x307a0100 0x09081109 |
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DATA 4 0x307a0104 0x0007020d |
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DATA 4 0x307a0108 0x03040407 |
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DATA 4 0x307a010c 0x00002006 |
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DATA 4 0x307a0110 0x04020205 |
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DATA 4 0x307a0114 0x03030202 |
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DATA 4 0x307a0120 0x00000803 |
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DATA 4 0x307a0180 0x00800020 |
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DATA 4 0x307a0184 0x02000100 |
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DATA 4 0x307a0190 0x02098204 |
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DATA 4 0x307a0194 0x00030303 |
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DATA 4 0x307a0200 0x00000016 |
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DATA 4 0x307a0204 0x00080808 |
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DATA 4 0x307a0210 0x00000f0f |
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DATA 4 0x307a0214 0x07070707 |
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DATA 4 0x307a0218 0x0f070707 |
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DATA 4 0x307a0240 0x06000604 |
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DATA 4 0x307a0244 0x00000001 |
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DATA 4 0x30391000 0x00000000 |
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DATA 4 0x30790000 0x17420f40 |
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DATA 4 0x30790004 0x10210100 |
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DATA 4 0x30790010 0x00060807 |
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DATA 4 0x307900b0 0x1010007e |
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DATA 4 0x3079009c 0x00000b24 |
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DATA 4 0x30790020 0x08080808 |
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DATA 4 0x30790030 0x08080808 |
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DATA 4 0x30790050 0x01000010 |
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DATA 4 0x30790050 0x00000010 |
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DATA 4 0x307900c0 0x0e407304 |
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DATA 4 0x307900c0 0x0e447304 |
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DATA 4 0x307900c0 0x0e447306 |
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CHECK_BITS_SET 4 0x307900c4 0x1 |
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DATA 4 0x307900c0 0x0e407304 |
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DATA 4 0x30384130 0x00000000 |
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DATA 4 0x30340020 0x00000178 |
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DATA 4 0x30384130 0x00000002 |
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DATA 4 0x30790018 0x0000000f |
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CHECK_BITS_SET 4 0x307a0004 0x1 |
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@ -0,0 +1,116 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Technexion Ltd. |
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* |
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* Author: Richard Hu <richard.hu@technexion.com> |
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*/ |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch-mx7/mx7-ddr.h> |
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#include <asm/gpio.h> |
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#include <spl.h> |
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#if defined(CONFIG_SPL_BUILD) |
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static struct ddrc ddrc_regs_val = { |
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.mstr = 0x01040001, |
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.rfshtmg = 0x00400046, |
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.init1 = 0x00690000, |
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.init0 = 0x00020083, |
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.init3 = 0x09300004, |
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.init4 = 0x04080000, |
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.init5 = 0x00100004, |
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.rankctl = 0x0000033F, |
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.dramtmg0 = 0x09081109, |
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.dramtmg1 = 0x0007020d, |
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.dramtmg2 = 0x03040407, |
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.dramtmg3 = 0x00002006, |
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.dramtmg4 = 0x04020205, |
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.dramtmg5 = 0x03030202, |
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.dramtmg8 = 0x00000803, |
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.zqctl0 = 0x00800020, |
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.dfitmg0 = 0x02098204, |
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.dfitmg1 = 0x00030303, |
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.dfiupd0 = 0x80400003, |
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.dfiupd1 = 0x00100020, |
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.dfiupd2 = 0x80100004, |
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.addrmap4 = 0x00000F0F, |
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.odtcfg = 0x06000604, |
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.odtmap = 0x00000001, |
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.rfshtmg = 0x00400046, |
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.dramtmg0 = 0x09081109, |
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.addrmap0 = 0x0000001f, |
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.addrmap1 = 0x00080808, |
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.addrmap4 = 0x00000f0f, |
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.addrmap5 = 0x07070707, |
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.addrmap6 = 0x0f0f0707, |
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}; |
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static struct ddrc_mp ddrc_mp_val = { |
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.pctrl_0 = 0x00000001, |
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}; |
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static struct ddr_phy ddr_phy_regs_val = { |
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.phy_con0 = 0x17420f40, |
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.phy_con1 = 0x10210100, |
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.phy_con4 = 0x00060807, |
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.mdll_con0 = 0x1010007e, |
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.drvds_con0 = 0x00000d6e, |
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.cmd_sdll_con0 = 0x00000010, |
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.offset_lp_con0 = 0x0000000f, |
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.offset_rd_con0 = 0x08080808, |
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.offset_wr_con0 = 0x08080808, |
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}; |
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static struct mx7_calibration calib_param = { |
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.num_val = 5, |
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.values = { |
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0x0E407304, |
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0x0E447304, |
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0x0E447306, |
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0x0E447304, |
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0x0E447304, |
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}, |
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}; |
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static void gpr_init(void) |
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{ |
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struct iomuxc_gpr_base_regs *gpr_regs = |
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; |
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writel(0x4F400005, &gpr_regs->gpr[1]); |
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} |
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static bool is_1g(void) |
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{ |
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gpio_direction_input(IMX_GPIO_NR(1, 12)); |
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return !gpio_get_value(IMX_GPIO_NR(1, 12)); |
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} |
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static void ddr_init(void) |
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{ |
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if (is_1g()) { |
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ddrc_regs_val.addrmap5 = 0x07070707; |
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ddrc_regs_val.addrmap6 = 0x0f070707; |
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} |
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mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val, |
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&calib_param); |
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} |
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void board_init_f(ulong dummy) |
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{ |
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arch_cpu_init(); |
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gpr_init(); |
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board_early_init_f(); |
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timer_init(); |
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preloader_console_init(); |
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ddr_init(); |
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memset(__bss_start, 0, __bss_end - __bss_start); |
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board_init_r(NULL, 0); |
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} |
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void reset_cpu(ulong addr) |
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{ |
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} |
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#endif |
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