Albert ARIBAUD
11 years ago
commit
d6694aff56
@ -0,0 +1,490 @@ |
||||
/*
|
||||
* Copyright (C) 2014 Gateworks Corporation |
||||
* Author: Tim Harvey <tharvey@gateworks.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/types.h> |
||||
#include <asm/arch/mx6-ddr.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/io.h> |
||||
#include <asm/types.h> |
||||
|
||||
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) |
||||
/* Configure MX6DQ mmdc iomux */ |
||||
void mx6dq_dram_iocfg(unsigned width, |
||||
const struct mx6dq_iomux_ddr_regs *ddr, |
||||
const struct mx6dq_iomux_grp_regs *grp) |
||||
{ |
||||
volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux; |
||||
volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux; |
||||
|
||||
mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE; |
||||
mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE; |
||||
|
||||
/* DDR IO Type */ |
||||
mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; |
||||
mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; |
||||
|
||||
/* Clock */ |
||||
mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; |
||||
mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1; |
||||
|
||||
/* Address */ |
||||
mx6_ddr_iomux->dram_cas = ddr->dram_cas; |
||||
mx6_ddr_iomux->dram_ras = ddr->dram_ras; |
||||
mx6_grp_iomux->grp_addds = grp->grp_addds; |
||||
|
||||
/* Control */ |
||||
mx6_ddr_iomux->dram_reset = ddr->dram_reset; |
||||
mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0; |
||||
mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1; |
||||
mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; |
||||
mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0; |
||||
mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1; |
||||
mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; |
||||
|
||||
/* Data Strobes */ |
||||
mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; |
||||
mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; |
||||
mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; |
||||
if (width >= 32) { |
||||
mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; |
||||
mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; |
||||
} |
||||
if (width >= 64) { |
||||
mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4; |
||||
mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5; |
||||
mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6; |
||||
mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7; |
||||
} |
||||
|
||||
/* Data */ |
||||
mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; |
||||
mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; |
||||
mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; |
||||
if (width >= 32) { |
||||
mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; |
||||
mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; |
||||
} |
||||
if (width >= 64) { |
||||
mx6_grp_iomux->grp_b4ds = grp->grp_b4ds; |
||||
mx6_grp_iomux->grp_b5ds = grp->grp_b5ds; |
||||
mx6_grp_iomux->grp_b6ds = grp->grp_b6ds; |
||||
mx6_grp_iomux->grp_b7ds = grp->grp_b7ds; |
||||
} |
||||
mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; |
||||
mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; |
||||
if (width >= 32) { |
||||
mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; |
||||
mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; |
||||
} |
||||
if (width >= 64) { |
||||
mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4; |
||||
mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5; |
||||
mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6; |
||||
mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7; |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) |
||||
/* Configure MX6SDL mmdc iomux */ |
||||
void mx6sdl_dram_iocfg(unsigned width, |
||||
const struct mx6sdl_iomux_ddr_regs *ddr, |
||||
const struct mx6sdl_iomux_grp_regs *grp) |
||||
{ |
||||
volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux; |
||||
volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux; |
||||
|
||||
mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE; |
||||
mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE; |
||||
|
||||
/* DDR IO Type */ |
||||
mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; |
||||
mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; |
||||
|
||||
/* Clock */ |
||||
mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; |
||||
mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1; |
||||
|
||||
/* Address */ |
||||
mx6_ddr_iomux->dram_cas = ddr->dram_cas; |
||||
mx6_ddr_iomux->dram_ras = ddr->dram_ras; |
||||
mx6_grp_iomux->grp_addds = grp->grp_addds; |
||||
|
||||
/* Control */ |
||||
mx6_ddr_iomux->dram_reset = ddr->dram_reset; |
||||
mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0; |
||||
mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1; |
||||
mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; |
||||
mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0; |
||||
mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1; |
||||
mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; |
||||
|
||||
/* Data Strobes */ |
||||
mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; |
||||
mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; |
||||
mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; |
||||
if (width >= 32) { |
||||
mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; |
||||
mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; |
||||
} |
||||
if (width >= 64) { |
||||
mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4; |
||||
mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5; |
||||
mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6; |
||||
mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7; |
||||
} |
||||
|
||||
/* Data */ |
||||
mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; |
||||
mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; |
||||
mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; |
||||
if (width >= 32) { |
||||
mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; |
||||
mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; |
||||
} |
||||
if (width >= 64) { |
||||
mx6_grp_iomux->grp_b4ds = grp->grp_b4ds; |
||||
mx6_grp_iomux->grp_b5ds = grp->grp_b5ds; |
||||
mx6_grp_iomux->grp_b6ds = grp->grp_b6ds; |
||||
mx6_grp_iomux->grp_b7ds = grp->grp_b7ds; |
||||
} |
||||
mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; |
||||
mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; |
||||
if (width >= 32) { |
||||
mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; |
||||
mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; |
||||
} |
||||
if (width >= 64) { |
||||
mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4; |
||||
mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5; |
||||
mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6; |
||||
mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7; |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* Configure mx6 mmdc registers based on: |
||||
* - board-specific memory configuration |
||||
* - board-specific calibration data |
||||
* - ddr3 chip details |
||||
* |
||||
* The various calculations here are derived from the Freescale |
||||
* i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC |
||||
* configuration registers based on memory system and memory chip parameters. |
||||
* |
||||
* The defaults here are those which were specified in the spreadsheet. |
||||
* For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM |
||||
* section titled MMDC initialization |
||||
*/ |
||||
#define MR(val, ba, cmd, cs1) \ |
||||
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) |
||||
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, |
||||
const struct mx6_mmdc_calibration *c, |
||||
const struct mx6_ddr3_cfg *m) |
||||
{ |
||||
volatile struct mmdc_p_regs *mmdc0; |
||||
volatile struct mmdc_p_regs *mmdc1; |
||||
u32 reg; |
||||
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; |
||||
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; |
||||
u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */ |
||||
u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; |
||||
u16 CS0_END; |
||||
u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */ |
||||
int clkper; /* clock period in picoseconds */ |
||||
int clock; /* clock freq in mHz */ |
||||
int cs; |
||||
|
||||
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; |
||||
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; |
||||
|
||||
/* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */ |
||||
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { |
||||
clock = 528; |
||||
tcwl = 4; |
||||
} |
||||
/* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */ |
||||
else { |
||||
clock = 400; |
||||
tcwl = 3; |
||||
} |
||||
clkper = (1000*1000)/clock; /* ps */ |
||||
todtlon = tcwl; |
||||
taxpd = tcwl; |
||||
tanpd = tcwl; |
||||
tcwl = tcwl; |
||||
|
||||
switch (m->density) { |
||||
case 1: /* 1Gb per chip */ |
||||
trfc = DIV_ROUND_UP(110000, clkper) - 1; |
||||
txs = DIV_ROUND_UP(120000, clkper) - 1; |
||||
break; |
||||
case 2: /* 2Gb per chip */ |
||||
trfc = DIV_ROUND_UP(160000, clkper) - 1; |
||||
txs = DIV_ROUND_UP(170000, clkper) - 1; |
||||
break; |
||||
case 4: /* 4Gb per chip */ |
||||
trfc = DIV_ROUND_UP(260000, clkper) - 1; |
||||
txs = DIV_ROUND_UP(270000, clkper) - 1; |
||||
break; |
||||
case 8: /* 8Gb per chip */ |
||||
trfc = DIV_ROUND_UP(350000, clkper) - 1; |
||||
txs = DIV_ROUND_UP(360000, clkper) - 1; |
||||
break; |
||||
default: |
||||
/* invalid density */ |
||||
printf("invalid chip density\n"); |
||||
hang(); |
||||
break; |
||||
} |
||||
txpr = txs; |
||||
|
||||
switch (m->mem_speed) { |
||||
case 800: |
||||
txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; |
||||
tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; |
||||
if (m->pagesz == 1) { |
||||
tfaw = DIV_ROUND_UP(40000, clkper) - 1; |
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; |
||||
} else { |
||||
tfaw = DIV_ROUND_UP(50000, clkper) - 1; |
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; |
||||
} |
||||
break; |
||||
case 1066: |
||||
txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; |
||||
tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1; |
||||
if (m->pagesz == 1) { |
||||
tfaw = DIV_ROUND_UP(37500, clkper) - 1; |
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; |
||||
} else { |
||||
tfaw = DIV_ROUND_UP(50000, clkper) - 1; |
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; |
||||
} |
||||
break; |
||||
case 1333: |
||||
txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1; |
||||
tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1; |
||||
if (m->pagesz == 1) { |
||||
tfaw = DIV_ROUND_UP(30000, clkper) - 1; |
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1; |
||||
} else { |
||||
tfaw = DIV_ROUND_UP(45000, clkper) - 1; |
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; |
||||
} |
||||
break; |
||||
case 1600: |
||||
txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1; |
||||
tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1; |
||||
if (m->pagesz == 1) { |
||||
tfaw = DIV_ROUND_UP(30000, clkper) - 1; |
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1; |
||||
} else { |
||||
tfaw = DIV_ROUND_UP(40000, clkper) - 1; |
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; |
||||
} |
||||
break; |
||||
default: |
||||
printf("invalid memory speed\n"); |
||||
hang(); |
||||
break; |
||||
} |
||||
txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1; |
||||
tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3; |
||||
tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper); |
||||
tcksrx = tcksre; |
||||
taonpd = DIV_ROUND_UP(2000, clkper) - 1; |
||||
taofpd = taonpd; |
||||
trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1; |
||||
trcd = trp; |
||||
trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1; |
||||
tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1; |
||||
twr = DIV_ROUND_UP(15000, clkper) - 1; |
||||
tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1; |
||||
twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1; |
||||
trtp = twtr; |
||||
CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127; |
||||
debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density); |
||||
debug("clock: %dMHz (%d ps)\n", clock, clkper); |
||||
debug("memspd:%d\n", m->mem_speed); |
||||
debug("tcke=%d\n", tcke); |
||||
debug("tcksrx=%d\n", tcksrx); |
||||
debug("tcksre=%d\n", tcksre); |
||||
debug("taofpd=%d\n", taofpd); |
||||
debug("taonpd=%d\n", taonpd); |
||||
debug("todtlon=%d\n", todtlon); |
||||
debug("tanpd=%d\n", tanpd); |
||||
debug("taxpd=%d\n", taxpd); |
||||
debug("trfc=%d\n", trfc); |
||||
debug("txs=%d\n", txs); |
||||
debug("txp=%d\n", txp); |
||||
debug("txpdll=%d\n", txpdll); |
||||
debug("tfaw=%d\n", tfaw); |
||||
debug("tcl=%d\n", tcl); |
||||
debug("trcd=%d\n", trcd); |
||||
debug("trp=%d\n", trp); |
||||
debug("trc=%d\n", trc); |
||||
debug("tras=%d\n", tras); |
||||
debug("twr=%d\n", twr); |
||||
debug("tmrd=%d\n", tmrd); |
||||
debug("tcwl=%d\n", tcwl); |
||||
debug("tdllk=%d\n", tdllk); |
||||
debug("trtp=%d\n", trtp); |
||||
debug("twtr=%d\n", twtr); |
||||
debug("trrd=%d\n", trrd); |
||||
debug("txpr=%d\n", txpr); |
||||
debug("CS0_END=%d\n", CS0_END); |
||||
debug("ncs=%d\n", i->ncs); |
||||
debug("Rtt_wr=%d\n", i->rtt_wr); |
||||
debug("Rtt_nom=%d\n", i->rtt_nom); |
||||
debug("SRT=%d\n", m->SRT); |
||||
debug("tcl=%d\n", tcl); |
||||
debug("twr=%d\n", twr); |
||||
|
||||
/*
|
||||
* board-specific configuration: |
||||
* These values are determined empirically and vary per board layout |
||||
* see: |
||||
* appnote, ddr3 spreadsheet |
||||
*/ |
||||
mmdc0->mpwldectrl0 = c->p0_mpwldectrl0; |
||||
mmdc0->mpwldectrl1 = c->p0_mpwldectrl1; |
||||
mmdc0->mpdgctrl0 = c->p0_mpdgctrl0; |
||||
mmdc0->mpdgctrl1 = c->p0_mpdgctrl1; |
||||
mmdc0->mprddlctl = c->p0_mprddlctl; |
||||
mmdc0->mpwrdlctl = c->p0_mpwrdlctl; |
||||
if (i->dsize > 1) { |
||||
mmdc1->mpwldectrl0 = c->p1_mpwldectrl0; |
||||
mmdc1->mpwldectrl1 = c->p1_mpwldectrl1; |
||||
mmdc1->mpdgctrl0 = c->p1_mpdgctrl0; |
||||
mmdc1->mpdgctrl1 = c->p1_mpdgctrl1; |
||||
mmdc1->mprddlctl = c->p1_mprddlctl; |
||||
mmdc1->mpwrdlctl = c->p1_mpwrdlctl; |
||||
} |
||||
|
||||
/* Read data DQ Byte0-3 delay */ |
||||
mmdc0->mprddqby0dl = (u32)0x33333333; |
||||
mmdc0->mprddqby1dl = (u32)0x33333333; |
||||
if (i->dsize > 0) { |
||||
mmdc0->mprddqby2dl = (u32)0x33333333; |
||||
mmdc0->mprddqby3dl = (u32)0x33333333; |
||||
} |
||||
if (i->dsize > 1) { |
||||
mmdc1->mprddqby0dl = (u32)0x33333333; |
||||
mmdc1->mprddqby1dl = (u32)0x33333333; |
||||
mmdc1->mprddqby2dl = (u32)0x33333333; |
||||
mmdc1->mprddqby3dl = (u32)0x33333333; |
||||
} |
||||
|
||||
/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */ |
||||
reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227; |
||||
mmdc0->mpodtctrl = reg; |
||||
if (i->dsize > 1) |
||||
mmdc1->mpodtctrl = reg; |
||||
|
||||
/* complete calibration */ |
||||
reg = (1 << 11); /* Force measurement on delay-lines */ |
||||
mmdc0->mpmur0 = reg; |
||||
if (i->dsize > 1) |
||||
mmdc1->mpmur0 = reg; |
||||
|
||||
/* Step 1: configuration request */ |
||||
mmdc0->mdscr = (u32)(1 << 15); /* config request */ |
||||
|
||||
/* Step 2: Timing configuration */ |
||||
reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) | |
||||
(tfaw << 4) | tcl; |
||||
mmdc0->mdcfg0 = reg; |
||||
reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) | |
||||
(1 << 15) | /* trpa */ |
||||
(twr << 9) | (tmrd << 5) | tcwl; |
||||
mmdc0->mdcfg1 = reg; |
||||
reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd; |
||||
mmdc0->mdcfg2 = reg; |
||||
reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) | |
||||
(todtlon << 12) | (todt_idle_off << 4); |
||||
mmdc0->mdotc = reg; |
||||
mmdc0->mdasp = CS0_END; /* CS addressing */ |
||||
|
||||
/* Step 3: Configure DDR type */ |
||||
reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) | |
||||
(i->mif3_mode << 9) | (i->ralat << 6); |
||||
mmdc0->mdmisc = reg; |
||||
|
||||
/* Step 4: Configure delay while leaving reset */ |
||||
reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0); |
||||
mmdc0->mdor = reg; |
||||
|
||||
/* Step 5: Configure DDR physical parameters (density and burst len) */ |
||||
reg = (m->rowaddr - 11) << 24 | /* ROW */ |
||||
(m->coladdr - 9) << 20 | /* COL */ |
||||
(1 << 19) | /* Burst Length = 8 for DDR3 */ |
||||
(i->dsize << 16); /* DDR data bus size */ |
||||
mmdc0->mdctl = reg; |
||||
|
||||
/* Step 6: Perform ZQ calibration */ |
||||
reg = (u32)0xa1390001; /* one-time HW ZQ calib */ |
||||
mmdc0->mpzqhwctrl = reg; |
||||
if (i->dsize > 1) |
||||
mmdc1->mpzqhwctrl = reg; |
||||
|
||||
/* Step 7: Enable MMDC with desired chip select */ |
||||
reg = mmdc0->mdctl | |
||||
(1 << 31) | /* SDE_0 for CS0 */ |
||||
((i->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ |
||||
mmdc0->mdctl = reg; |
||||
|
||||
/* Step 8: Write Mode Registers to Init DDR3 devices */ |
||||
for (cs = 0; cs < i->ncs; cs++) { |
||||
/* MR2 */ |
||||
reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 | |
||||
((tcwl - 3) & 3) << 3; |
||||
mmdc0->mdscr = (u32)MR(reg, 2, 3, cs); |
||||
/* MR3 */ |
||||
mmdc0->mdscr = (u32)MR(0, 3, 3, cs); |
||||
/* MR1 */ |
||||
reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 | |
||||
((i->rtt_nom & 2) ? 1 : 0) << 6; |
||||
mmdc0->mdscr = (u32)MR(reg, 1, 3, cs); |
||||
reg = ((tcl - 1) << 4) | /* CAS */ |
||||
(1 << 8) | /* DLL Reset */ |
||||
((twr - 3) << 9); /* Write Recovery */ |
||||
/* MR0 */ |
||||
mmdc0->mdscr = (u32)MR(reg, 0, 3, cs); |
||||
/* ZQ calibration */ |
||||
reg = (1 << 10); |
||||
mmdc0->mdscr = (u32)MR(reg, 0, 4, cs); |
||||
} |
||||
|
||||
/* Step 10: Power down control and self-refresh */ |
||||
reg = (tcke & 0x7) << 16 | |
||||
5 << 12 | /* PWDT_1: 256 cycles */ |
||||
5 << 8 | /* PWDT_0: 256 cycles */ |
||||
1 << 6 | /* BOTH_CS_PD */ |
||||
(tcksrx & 0x7) << 3 | |
||||
(tcksre & 0x7); |
||||
mmdc0->mdpdc = reg; |
||||
mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */ |
||||
|
||||
/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ |
||||
mmdc0->mpzqhwctrl = (u32)0xa1390003; |
||||
if (i->dsize > 1) |
||||
mmdc1->mpzqhwctrl = (u32)0xa1390003; |
||||
|
||||
/* Step 12: Configure and activate periodic refresh */ |
||||
reg = (1 << 14) | /* REF_SEL: Periodic refresh cycles of 32kHz */ |
||||
(7 << 11); /* REFR: Refresh Rate - 8 refreshes */ |
||||
mmdc0->mdref = reg; |
||||
|
||||
/* Step 13: Deassert config request - init complete */ |
||||
mmdc0->mdscr = (u32)0x00000000; |
||||
|
||||
/* wait for auto-ZQ calibration to complete */ |
||||
mdelay(1); |
||||
} |
||||
@ -0,0 +1,81 @@ |
||||
/*
|
||||
* Copyright (C) 2014 Gateworks Corporation |
||||
* Copyright (C) 2011-2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* Author: Tim Harvey <tharvey@gateworks.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/spl.h> |
||||
#include <spl.h> |
||||
|
||||
#if defined(CONFIG_MX6) |
||||
/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */ |
||||
u32 spl_boot_device(void) |
||||
{ |
||||
struct src *psrc = (struct src *)SRC_BASE_ADDR; |
||||
unsigned reg = readl(&psrc->sbmr1); |
||||
|
||||
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */ |
||||
switch ((reg & 0x000000FF) >> 4) { |
||||
/* EIM: See 8.5.1, Table 8-9 */ |
||||
case 0x0: |
||||
/* BOOT_CFG1[3]: NOR/OneNAND Selection */ |
||||
if ((reg & 0x00000008) >> 3) |
||||
return BOOT_DEVICE_ONENAND; |
||||
else |
||||
return BOOT_DEVICE_NOR; |
||||
break; |
||||
/* SATA: See 8.5.4, Table 8-20 */ |
||||
case 0x2: |
||||
return BOOT_DEVICE_SATA; |
||||
/* Serial ROM: See 8.5.5.1, Table 8-22 */ |
||||
case 0x3: |
||||
/* BOOT_CFG4[2:0] */ |
||||
switch ((reg & 0x07000000) >> 24) { |
||||
case 0x0 ... 0x4: |
||||
return BOOT_DEVICE_SPI; |
||||
case 0x5 ... 0x7: |
||||
return BOOT_DEVICE_I2C; |
||||
} |
||||
break; |
||||
/* SD/eSD: 8.5.3, Table 8-15 */ |
||||
case 0x4: |
||||
case 0x5: |
||||
return BOOT_DEVICE_MMC1; |
||||
/* MMC/eMMC: 8.5.3 */ |
||||
case 0x6: |
||||
case 0x7: |
||||
return BOOT_DEVICE_MMC1; |
||||
/* NAND Flash: 8.5.2 */ |
||||
case 0x8 ... 0xf: |
||||
return BOOT_DEVICE_NAND; |
||||
} |
||||
return BOOT_DEVICE_NONE; |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_SPL_MMC_SUPPORT) |
||||
/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ |
||||
u32 spl_boot_mode(void) |
||||
{ |
||||
switch (spl_boot_device()) { |
||||
/* for MMC return either RAW or FAT mode */ |
||||
case BOOT_DEVICE_MMC1: |
||||
case BOOT_DEVICE_MMC2: |
||||
#ifdef CONFIG_SPL_FAT_SUPPORT |
||||
return MMCSD_MODE_FAT; |
||||
#else |
||||
return MMCSD_MODE_RAW; |
||||
#endif |
||||
break; |
||||
default: |
||||
puts("spl: ERROR: unsupported device\n"); |
||||
hang(); |
||||
} |
||||
} |
||||
#endif |
||||
@ -1,24 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Atmel Corporation |
||||
* Bo Shen <voice.shen@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _ASM_ARCH_SPL_H_ |
||||
#define _ASM_ARCH_SPL_H_ |
||||
|
||||
enum { |
||||
BOOT_DEVICE_NONE, |
||||
#ifdef CONFIG_SYS_USE_MMC |
||||
BOOT_DEVICE_MMC1, |
||||
BOOT_DEVICE_MMC2, |
||||
BOOT_DEVICE_MMC2_2, |
||||
#elif CONFIG_SYS_USE_NANDFLASH |
||||
BOOT_DEVICE_NAND, |
||||
#elif CONFIG_SYS_USE_SERIALFLASH |
||||
BOOT_DEVICE_SPI, |
||||
#endif |
||||
}; |
||||
|
||||
#endif |
||||
@ -1,16 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2012 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef _ASM_ARCH_SPL_H_ |
||||
#define _ASM_ARCH_SPL_H_ |
||||
|
||||
#define BOOT_DEVICE_NAND 1 |
||||
#define BOOT_DEVICE_SPI 2 |
||||
#define BOOT_DEVICE_MMC1 3 |
||||
#define BOOT_DEVICE_MMC2 4 /* dummy */ |
||||
#define BOOT_DEVICE_MMC2_2 5 /* dummy */ |
||||
|
||||
#endif |
||||
@ -1,22 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2012 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef _ASM_ARCH_SPL_H_ |
||||
#define _ASM_ARCH_SPL_H_ |
||||
|
||||
#define BOOT_DEVICE_NONE 0 |
||||
#define BOOT_DEVICE_XIP 1 |
||||
#define BOOT_DEVICE_XIPWAIT 2 |
||||
#define BOOT_DEVICE_NAND 3 |
||||
#define BOOT_DEVICE_ONENAND 4 |
||||
#define BOOT_DEVICE_MMC1 5 |
||||
#define BOOT_DEVICE_MMC2 6 |
||||
#define BOOT_DEVICE_MMC2_2 7 |
||||
#define BOOT_DEVICE_NOR 8 |
||||
#define BOOT_DEVICE_I2C 9 |
||||
#define BOOT_DEVICE_SPI 10 |
||||
|
||||
#endif |
||||
@ -1,13 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Marek Vasut <marex@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_SPL_H__ |
||||
#define __ASM_ARCH_SPL_H__ |
||||
|
||||
#define BOOT_DEVICE_NONE 0 |
||||
#define BOOT_DEVICE_NAND 1 |
||||
|
||||
#endif /* __ASM_ARCH_SPL_H__ */ |
||||
@ -1,22 +0,0 @@ |
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms and conditions of the GNU General Public License, |
||||
* version 2, as published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope it will be useful, but WITHOUT |
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
||||
* more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/ |
||||
|
||||
#ifndef _ASM_ARCH_SPL_H_ |
||||
#define _ASM_ARCH_SPL_H_ |
||||
|
||||
#define BOOT_DEVICE_RAM 1 |
||||
|
||||
#endif |
||||
@ -1,13 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2010-2013 |
||||
* NVIDIA Corporation <www.nvidia.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _ASM_ARCH_SPL_H_ |
||||
#define _ASM_ARCH_SPL_H_ |
||||
|
||||
#define BOOT_DEVICE_RAM 1 |
||||
|
||||
#endif /* _ASM_ARCH_SPL_H_ */ |
||||
@ -1,12 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2012 |
||||
* NVIDIA Corporation <www.nvidia.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef _ASM_ARCH_SPL_H_ |
||||
#define _ASM_ARCH_SPL_H_ |
||||
|
||||
#define BOOT_DEVICE_RAM 1 |
||||
|
||||
#endif |
||||
@ -1,12 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2012 |
||||
* NVIDIA Corporation <www.nvidia.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef _ASM_ARCH_SPL_H_ |
||||
#define _ASM_ARCH_SPL_H_ |
||||
|
||||
#define BOOT_DEVICE_RAM 1 |
||||
|
||||
#endif |
||||
@ -0,0 +1,130 @@ |
||||
/* |
||||
* Copyright (C) 2013 Freescale Semiconductor, Inc. |
||||
* Jason Liu <r64343@freescale.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Refer doc/README.imximage for more details about how-to configure |
||||
* and create imximage boot image |
||||
* |
||||
* The syntax is taken as close as possible with the kwbimage |
||||
*/ |
||||
/* image version */ |
||||
|
||||
IMAGE_VERSION 2 |
||||
|
||||
/* |
||||
* Boot Device : one of |
||||
* spi, sd (the board has no nand neither onenand) |
||||
*/ |
||||
BOOT_FROM sd |
||||
|
||||
/* |
||||
* Device Configuration Data (DCD) |
||||
* |
||||
* Each entry must have the format: |
||||
* Addr-type Address Value |
||||
* |
||||
* where: |
||||
* Addr-type register length (1,2 or 4 bytes) |
||||
* Address absolute address of the register |
||||
* value value to be stored in the register |
||||
*/ |
||||
DATA 4 0x020e0774 0x000C0000 |
||||
DATA 4 0x020e0754 0x00000000 |
||||
DATA 4 0x020e04ac 0x00000030 |
||||
DATA 4 0x020e04b0 0x00000030 |
||||
DATA 4 0x020e0464 0x00000030 |
||||
DATA 4 0x020e0490 0x00000030 |
||||
DATA 4 0x020e074c 0x00000030 |
||||
DATA 4 0x020e0494 0x00000030 |
||||
DATA 4 0x020e04a0 0x00000000 |
||||
DATA 4 0x020e04b4 0x00000030 |
||||
DATA 4 0x020e04b8 0x00000030 |
||||
DATA 4 0x020e076c 0x00000030 |
||||
DATA 4 0x020e0750 0x00020000 |
||||
DATA 4 0x020e04bc 0x00000028 |
||||
DATA 4 0x020e04c0 0x00000028 |
||||
DATA 4 0x020e04c4 0x00000028 |
||||
DATA 4 0x020e04c8 0x00000028 |
||||
DATA 4 0x020e04cc 0x00000028 |
||||
DATA 4 0x020e04d0 0x00000028 |
||||
DATA 4 0x020e04d4 0x00000028 |
||||
DATA 4 0x020e04d8 0x00000028 |
||||
DATA 4 0x020e0760 0x00020000 |
||||
DATA 4 0x020e0764 0x00000028 |
||||
DATA 4 0x020e0770 0x00000028 |
||||
DATA 4 0x020e0778 0x00000028 |
||||
DATA 4 0x020e077c 0x00000028 |
||||
DATA 4 0x020e0780 0x00000028 |
||||
DATA 4 0x020e0784 0x00000028 |
||||
DATA 4 0x020e078c 0x00000028 |
||||
DATA 4 0x020e0748 0x00000028 |
||||
DATA 4 0x020e0470 0x00000028 |
||||
DATA 4 0x020e0474 0x00000028 |
||||
DATA 4 0x020e0478 0x00000028 |
||||
DATA 4 0x020e047c 0x00000028 |
||||
DATA 4 0x020e0480 0x00000028 |
||||
DATA 4 0x020e0484 0x00000028 |
||||
DATA 4 0x020e0488 0x00000028 |
||||
DATA 4 0x020e048c 0x00000028 |
||||
DATA 4 0x021b0800 0xa1390003 |
||||
DATA 4 0x021b080c 0x001F001F |
||||
DATA 4 0x021b0810 0x001F001F |
||||
DATA 4 0x021b480c 0x001F001F |
||||
DATA 4 0x021b4810 0x001F001F |
||||
DATA 4 0x021b083c 0x42190217 |
||||
DATA 4 0x021b0840 0x017B017B |
||||
DATA 4 0x021b483c 0x4176017B |
||||
DATA 4 0x021b4840 0x015F016C |
||||
DATA 4 0x021b0848 0x4C4C4D4C |
||||
DATA 4 0x021b4848 0x4A4D4C48 |
||||
DATA 4 0x021b0850 0x3F3F3F40 |
||||
DATA 4 0x021b4850 0x3538382E |
||||
DATA 4 0x021b081c 0x33333333 |
||||
DATA 4 0x021b0820 0x33333333 |
||||
DATA 4 0x021b0824 0x33333333 |
||||
DATA 4 0x021b0828 0x33333333 |
||||
DATA 4 0x021b481c 0x33333333 |
||||
DATA 4 0x021b4820 0x33333333 |
||||
DATA 4 0x021b4824 0x33333333 |
||||
DATA 4 0x021b4828 0x33333333 |
||||
DATA 4 0x021b08b8 0x00000800 |
||||
DATA 4 0x021b48b8 0x00000800 |
||||
DATA 4 0x021b0004 0x00020025 |
||||
DATA 4 0x021b0008 0x00333030 |
||||
DATA 4 0x021b000c 0x676B5313 |
||||
DATA 4 0x021b0010 0xB66E8B63 |
||||
DATA 4 0x021b0014 0x01FF00DB |
||||
DATA 4 0x021b0018 0x00001740 |
||||
DATA 4 0x021b001c 0x00008000 |
||||
DATA 4 0x021b002c 0x000026d2 |
||||
DATA 4 0x021b0030 0x006B1023 |
||||
DATA 4 0x021b0040 0x00000047 |
||||
DATA 4 0x021b0000 0x841A0000 |
||||
DATA 4 0x021b001c 0x04008032 |
||||
DATA 4 0x021b001c 0x00008033 |
||||
DATA 4 0x021b001c 0x00048031 |
||||
DATA 4 0x021b001c 0x05208030 |
||||
DATA 4 0x021b001c 0x04008040 |
||||
DATA 4 0x021b0020 0x00005800 |
||||
DATA 4 0x021b0818 0x00011117 |
||||
DATA 4 0x021b4818 0x00011117 |
||||
DATA 4 0x021b0004 0x00025565 |
||||
DATA 4 0x021b0404 0x00011006 |
||||
DATA 4 0x021b001c 0x00000000 |
||||
|
||||
/* set the default clock gate to save power */ |
||||
DATA 4 0x020c4068 0x00C03F3F |
||||
DATA 4 0x020c406c 0x0030FC03 |
||||
DATA 4 0x020c4070 0x0FFFC000 |
||||
DATA 4 0x020c4074 0x3FF00000 |
||||
DATA 4 0x020c4078 0xFFFFF300 |
||||
DATA 4 0x020c407c 0x0F0000C3 |
||||
DATA 4 0x020c4080 0x00000FFF |
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */ |
||||
DATA 4 0x020e0010 0xF00000CF |
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
||||
DATA 4 0x020e0018 0x007F007F |
||||
DATA 4 0x020e001c 0x007F007F |
||||
@ -0,0 +1,89 @@ |
||||
/*
|
||||
* Copyright (C) 2014 Gateworks Corporation |
||||
* Author: Tim Harvey <tharvey@gateworks.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
|
||||
#include "gsc.h" |
||||
#include "ventana_eeprom.h" |
||||
|
||||
/* read ventana EEPROM, check for validity, and return baseboard type */ |
||||
int |
||||
read_eeprom(int bus, struct ventana_board_info *info) |
||||
{ |
||||
int i; |
||||
int chksum; |
||||
char baseboard; |
||||
int type; |
||||
unsigned char *buf = (unsigned char *)info; |
||||
|
||||
memset(info, 0, sizeof(*info)); |
||||
|
||||
/*
|
||||
* On a board with a missing/depleted backup battery for GSC, the |
||||
* board may be ready to probe the GSC before its firmware is |
||||
* running. We will wait here indefinately for the GSC/EEPROM. |
||||
*/ |
||||
while (1) { |
||||
if (0 == i2c_set_bus_num(bus) && |
||||
0 == i2c_probe(GSC_EEPROM_ADDR)) |
||||
break; |
||||
mdelay(1); |
||||
} |
||||
|
||||
/* read eeprom config section */ |
||||
if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) { |
||||
puts("EEPROM: Failed to read EEPROM\n"); |
||||
info->model[0] = 0; |
||||
return GW_UNKNOWN; |
||||
} |
||||
|
||||
/* sanity checks */ |
||||
if (info->model[0] != 'G' || info->model[1] != 'W') { |
||||
puts("EEPROM: Invalid Model in EEPROM\n"); |
||||
info->model[0] = 0; |
||||
return GW_UNKNOWN; |
||||
} |
||||
|
||||
/* validate checksum */ |
||||
for (chksum = 0, i = 0; i < sizeof(*info)-2; i++) |
||||
chksum += buf[i]; |
||||
if ((info->chksum[0] != chksum>>8) || |
||||
(info->chksum[1] != (chksum&0xff))) { |
||||
puts("EEPROM: Failed EEPROM checksum\n"); |
||||
info->model[0] = 0; |
||||
return GW_UNKNOWN; |
||||
} |
||||
|
||||
/* original GW5400-A prototype */ |
||||
baseboard = info->model[3]; |
||||
if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0) |
||||
baseboard = '0'; |
||||
|
||||
switch (baseboard) { |
||||
case '0': /* original GW5400-A prototype */ |
||||
type = GW54proto; |
||||
break; |
||||
case '1': |
||||
type = GW51xx; |
||||
break; |
||||
case '2': |
||||
type = GW52xx; |
||||
break; |
||||
case '3': |
||||
type = GW53xx; |
||||
break; |
||||
case '4': |
||||
type = GW54xx; |
||||
break; |
||||
default: |
||||
printf("EEPROM: Unknown model in EEPROM: %s\n", info->model); |
||||
type = GW_UNKNOWN; |
||||
break; |
||||
} |
||||
return type; |
||||
} |
||||
@ -0,0 +1,419 @@ |
||||
/*
|
||||
* Copyright (C) 2014 Gateworks Corporation |
||||
* Author: Tim Harvey <tharvey@gateworks.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/arch/mx6-ddr.h> |
||||
#include <asm/arch/mx6-pins.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/imx-common/boot_mode.h> |
||||
#include <asm/imx-common/iomux-v3.h> |
||||
#include <asm/imx-common/mxc_i2c.h> |
||||
#include <spl.h> |
||||
|
||||
#include "ventana_eeprom.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ |
||||
#define I2C_GSC 0 |
||||
#define GSC_EEPROM_ADDR 0x51 |
||||
#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */ |
||||
#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */ |
||||
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE | PAD_CTL_SRE_FAST) |
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
|
||||
/* I2C1: GSC */ |
||||
static struct i2c_pads_info mx6q_i2c_pad_info0 = { |
||||
.scl = { |
||||
.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, |
||||
.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, |
||||
.gp = IMX_GPIO_NR(3, 21) |
||||
}, |
||||
.sda = { |
||||
.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, |
||||
.gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, |
||||
.gp = IMX_GPIO_NR(3, 28) |
||||
} |
||||
}; |
||||
static struct i2c_pads_info mx6dl_i2c_pad_info0 = { |
||||
.scl = { |
||||
.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, |
||||
.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, |
||||
.gp = IMX_GPIO_NR(3, 21) |
||||
}, |
||||
.sda = { |
||||
.i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, |
||||
.gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, |
||||
.gp = IMX_GPIO_NR(3, 28) |
||||
} |
||||
}; |
||||
|
||||
static void i2c_setup_iomux(void) |
||||
{ |
||||
if (is_cpu_type(MXC_CPU_MX6Q)) |
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); |
||||
else |
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); |
||||
} |
||||
|
||||
/* configure MX6Q/DUAL mmdc DDR io registers */ |
||||
struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { |
||||
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ |
||||
.dram_sdclk_0 = 0x00020030, |
||||
.dram_sdclk_1 = 0x00020030, |
||||
.dram_cas = 0x00020030, |
||||
.dram_ras = 0x00020030, |
||||
.dram_reset = 0x00020030, |
||||
/* SDCKE[0:1]: 100k pull-up */ |
||||
.dram_sdcke0 = 0x00003000, |
||||
.dram_sdcke1 = 0x00003000, |
||||
/* SDBA2: pull-up disabled */ |
||||
.dram_sdba2 = 0x00000000, |
||||
/* SDODT[0:1]: 100k pull-up, 40 ohm */ |
||||
.dram_sdodt0 = 0x00003030, |
||||
.dram_sdodt1 = 0x00003030, |
||||
/* SDQS[0:7]: Differential input, 40 ohm */ |
||||
.dram_sdqs0 = 0x00000030, |
||||
.dram_sdqs1 = 0x00000030, |
||||
.dram_sdqs2 = 0x00000030, |
||||
.dram_sdqs3 = 0x00000030, |
||||
.dram_sdqs4 = 0x00000030, |
||||
.dram_sdqs5 = 0x00000030, |
||||
.dram_sdqs6 = 0x00000030, |
||||
.dram_sdqs7 = 0x00000030, |
||||
|
||||
/* DQM[0:7]: Differential input, 40 ohm */ |
||||
.dram_dqm0 = 0x00020030, |
||||
.dram_dqm1 = 0x00020030, |
||||
.dram_dqm2 = 0x00020030, |
||||
.dram_dqm3 = 0x00020030, |
||||
.dram_dqm4 = 0x00020030, |
||||
.dram_dqm5 = 0x00020030, |
||||
.dram_dqm6 = 0x00020030, |
||||
.dram_dqm7 = 0x00020030, |
||||
}; |
||||
|
||||
/* configure MX6Q/DUAL mmdc GRP io registers */ |
||||
struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { |
||||
/* DDR3 */ |
||||
.grp_ddr_type = 0x000c0000, |
||||
.grp_ddrmode_ctl = 0x00020000, |
||||
/* disable DDR pullups */ |
||||
.grp_ddrpke = 0x00000000, |
||||
/* ADDR[00:16], SDBA[0:1]: 40 ohm */ |
||||
.grp_addds = 0x00000030, |
||||
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ |
||||
.grp_ctlds = 0x00000030, |
||||
/* DATA[00:63]: Differential input, 40 ohm */ |
||||
.grp_ddrmode = 0x00020000, |
||||
.grp_b0ds = 0x00000030, |
||||
.grp_b1ds = 0x00000030, |
||||
.grp_b2ds = 0x00000030, |
||||
.grp_b3ds = 0x00000030, |
||||
.grp_b4ds = 0x00000030, |
||||
.grp_b5ds = 0x00000030, |
||||
.grp_b6ds = 0x00000030, |
||||
.grp_b7ds = 0x00000030, |
||||
}; |
||||
|
||||
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ |
||||
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { |
||||
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ |
||||
.dram_sdclk_0 = 0x00020030, |
||||
.dram_sdclk_1 = 0x00020030, |
||||
.dram_cas = 0x00020030, |
||||
.dram_ras = 0x00020030, |
||||
.dram_reset = 0x00020030, |
||||
/* SDCKE[0:1]: 100k pull-up */ |
||||
.dram_sdcke0 = 0x00003000, |
||||
.dram_sdcke1 = 0x00003000, |
||||
/* SDBA2: pull-up disabled */ |
||||
.dram_sdba2 = 0x00000000, |
||||
/* SDODT[0:1]: 100k pull-up, 40 ohm */ |
||||
.dram_sdodt0 = 0x00003030, |
||||
.dram_sdodt1 = 0x00003030, |
||||
/* SDQS[0:7]: Differential input, 40 ohm */ |
||||
.dram_sdqs0 = 0x00000030, |
||||
.dram_sdqs1 = 0x00000030, |
||||
.dram_sdqs2 = 0x00000030, |
||||
.dram_sdqs3 = 0x00000030, |
||||
.dram_sdqs4 = 0x00000030, |
||||
.dram_sdqs5 = 0x00000030, |
||||
.dram_sdqs6 = 0x00000030, |
||||
.dram_sdqs7 = 0x00000030, |
||||
|
||||
/* DQM[0:7]: Differential input, 40 ohm */ |
||||
.dram_dqm0 = 0x00020030, |
||||
.dram_dqm1 = 0x00020030, |
||||
.dram_dqm2 = 0x00020030, |
||||
.dram_dqm3 = 0x00020030, |
||||
.dram_dqm4 = 0x00020030, |
||||
.dram_dqm5 = 0x00020030, |
||||
.dram_dqm6 = 0x00020030, |
||||
.dram_dqm7 = 0x00020030, |
||||
}; |
||||
|
||||
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ |
||||
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { |
||||
/* DDR3 */ |
||||
.grp_ddr_type = 0x000c0000, |
||||
/* SDQS[0:7]: Differential input, 40 ohm */ |
||||
.grp_ddrmode_ctl = 0x00020000, |
||||
/* disable DDR pullups */ |
||||
.grp_ddrpke = 0x00000000, |
||||
/* ADDR[00:16], SDBA[0:1]: 40 ohm */ |
||||
.grp_addds = 0x00000030, |
||||
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ |
||||
.grp_ctlds = 0x00000030, |
||||
/* DATA[00:63]: Differential input, 40 ohm */ |
||||
.grp_ddrmode = 0x00020000, |
||||
.grp_b0ds = 0x00000030, |
||||
.grp_b1ds = 0x00000030, |
||||
.grp_b2ds = 0x00000030, |
||||
.grp_b3ds = 0x00000030, |
||||
.grp_b4ds = 0x00000030, |
||||
.grp_b5ds = 0x00000030, |
||||
.grp_b6ds = 0x00000030, |
||||
.grp_b7ds = 0x00000030, |
||||
}; |
||||
|
||||
/* MT41K128M16JT-125 */ |
||||
static struct mx6_ddr3_cfg mt41k128m16jt_125 = { |
||||
.mem_speed = 1600, |
||||
.density = 2, |
||||
.width = 16, |
||||
.banks = 8, |
||||
.rowaddr = 14, |
||||
.coladdr = 10, |
||||
.pagesz = 2, |
||||
.trcd = 1375, |
||||
.trcmin = 4875, |
||||
.trasmin = 3500, |
||||
}; |
||||
|
||||
/* GW54xx specific calibration */ |
||||
static struct mx6_mmdc_calibration gw54xxq_mmdc_calib = { |
||||
/* write leveling calibration determine */ |
||||
.p0_mpwldectrl0 = 0x00190018, |
||||
.p0_mpwldectrl1 = 0x0021001D, |
||||
.p1_mpwldectrl0 = 0x00160027, |
||||
.p1_mpwldectrl1 = 0x0012001E, |
||||
/* Read DQS Gating calibration */ |
||||
.p0_mpdgctrl0 = 0x43370346, |
||||
.p0_mpdgctrl1 = 0x032A0321, |
||||
.p1_mpdgctrl0 = 0x433A034D, |
||||
.p1_mpdgctrl1 = 0x032F0235, |
||||
/* Read Calibration: DQS delay relative to DQ read access */ |
||||
.p0_mprddlctl = 0x3C313539, |
||||
.p1_mprddlctl = 0x37333140, |
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */ |
||||
.p0_mpwrdlctl = 0x37393C38, |
||||
.p1_mpwrdlctl = 0x42334538, |
||||
}; |
||||
|
||||
/* GW53xx specific calibration */ |
||||
static struct mx6_mmdc_calibration gw53xxq_mmdc_calib = { |
||||
/* write leveling calibration determine */ |
||||
.p0_mpwldectrl0 = 0x00160013, |
||||
.p0_mpwldectrl1 = 0x00090024, |
||||
.p1_mpwldectrl0 = 0x001F0018, |
||||
.p1_mpwldectrl1 = 0x000C001C, |
||||
/* Read DQS Gating calibration */ |
||||
.p0_mpdgctrl0 = 0x433A034C, |
||||
.p0_mpdgctrl1 = 0x0336032F, |
||||
.p1_mpdgctrl0 = 0x4343034A, |
||||
.p1_mpdgctrl1 = 0x03370222, |
||||
/* Read Calibration: DQS delay relative to DQ read access */ |
||||
.p0_mprddlctl = 0x3F343638, |
||||
.p1_mprddlctl = 0x38373442, |
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */ |
||||
.p0_mpwrdlctl = 0x343A3E39, |
||||
.p1_mpwrdlctl = 0x44344239, |
||||
}; |
||||
static struct mx6_mmdc_calibration gw53xxdl_mmdc_calib = { |
||||
/* write leveling calibration determine */ |
||||
.p0_mpwldectrl0 = 0x003C003C, |
||||
.p0_mpwldectrl1 = 0x00330038, |
||||
.p1_mpwldectrl0 = 0x001F002A, |
||||
.p1_mpwldectrl1 = 0x0022003F, |
||||
/* Read DQS Gating calibration */ |
||||
.p0_mpdgctrl0 = 0x42410244, |
||||
.p0_mpdgctrl1 = 0x022D022D, |
||||
.p1_mpdgctrl0 = 0x4234023A, |
||||
.p1_mpdgctrl1 = 0x021C0228, |
||||
/* Read Calibration: DQS delay relative to DQ read access */ |
||||
.p0_mprddlctl = 0x484A4C4B, |
||||
.p1_mprddlctl = 0x4B4D4E4B, |
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */ |
||||
.p0_mpwrdlctl = 0x33342B32, |
||||
.p1_mpwrdlctl = 0x3933332B, |
||||
}; |
||||
|
||||
/* GW52xx specific calibration */ |
||||
static struct mx6_mmdc_calibration gw52xxdl_mmdc_calib = { |
||||
/* write leveling calibration determine */ |
||||
.p0_mpwldectrl0 = 0x0040003F, |
||||
.p0_mpwldectrl1 = 0x00370037, |
||||
/* Read DQS Gating calibration */ |
||||
.p0_mpdgctrl0 = 0x42420244, |
||||
.p0_mpdgctrl1 = 0x022F022F, |
||||
/* Read Calibration: DQS delay relative to DQ read access */ |
||||
.p0_mprddlctl = 0x49464B4A, |
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */ |
||||
.p0_mpwrdlctl = 0x32362C32, |
||||
}; |
||||
|
||||
/* GW51xx specific calibration */ |
||||
static struct mx6_mmdc_calibration gw51xxq_mmdc_calib = { |
||||
/* write leveling calibration determine */ |
||||
.p0_mpwldectrl0 = 0x00150016, |
||||
.p0_mpwldectrl1 = 0x001F0017, |
||||
/* Read DQS Gating calibration */ |
||||
.p0_mpdgctrl0 = 0x433D034D, |
||||
.p0_mpdgctrl1 = 0x033D032F, |
||||
/* Read Calibration: DQS delay relative to DQ read access */ |
||||
.p0_mprddlctl = 0x3F313639, |
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */ |
||||
.p0_mpwrdlctl = 0x33393F36, |
||||
}; |
||||
|
||||
static struct mx6_mmdc_calibration gw51xxdl_mmdc_calib = { |
||||
/* write leveling calibration determine */ |
||||
.p0_mpwldectrl0 = 0x003D003F, |
||||
.p0_mpwldectrl1 = 0x002F0038, |
||||
/* Read DQS Gating calibration */ |
||||
.p0_mpdgctrl0 = 0x423A023A, |
||||
.p0_mpdgctrl1 = 0x022A0228, |
||||
/* Read Calibration: DQS delay relative to DQ read access */ |
||||
.p0_mprddlctl = 0x48494C4C, |
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */ |
||||
.p0_mpwrdlctl = 0x34352D31, |
||||
}; |
||||
|
||||
static void spl_dram_init(int width, int size, int board_model) |
||||
{ |
||||
struct mx6_ddr3_cfg *mem = &mt41k128m16jt_125; |
||||
struct mx6_mmdc_calibration *calib; |
||||
struct mx6_ddr_sysinfo sysinfo = { |
||||
/* width of data bus:0=16,1=32,2=64 */ |
||||
.dsize = width/32, |
||||
/* config for full 4GB range so that get_mem_size() works */ |
||||
.cs_density = 32, /* 32Gb per CS */ |
||||
/* single chip select */ |
||||
.ncs = 1, |
||||
.cs1_mirror = 0, |
||||
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ |
||||
#ifdef RTT_NOM_120OHM |
||||
.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ |
||||
#else |
||||
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ |
||||
#endif |
||||
.walat = 1, /* Write additional latency */ |
||||
.ralat = 5, /* Read additional latency */ |
||||
.mif3_mode = 3, /* Command prediction working mode */ |
||||
.bi_on = 1, /* Bank interleaving enabled */ |
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
||||
}; |
||||
|
||||
/*
|
||||
* MMDC Calibration requires the following data: |
||||
* mx6_mmdc_calibration - board-specific calibration (routing delays) |
||||
* mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) |
||||
* mx6_ddr_cfg - chip specific timing/layout details |
||||
*/ |
||||
switch (board_model) { |
||||
default: |
||||
case GW51xx: |
||||
if (is_cpu_type(MXC_CPU_MX6Q)) |
||||
calib = &gw51xxq_mmdc_calib; |
||||
else |
||||
calib = &gw51xxdl_mmdc_calib; |
||||
break; |
||||
case GW52xx: |
||||
calib = &gw52xxdl_mmdc_calib; |
||||
break; |
||||
case GW53xx: |
||||
if (is_cpu_type(MXC_CPU_MX6Q)) |
||||
calib = &gw53xxq_mmdc_calib; |
||||
else |
||||
calib = &gw53xxdl_mmdc_calib; |
||||
break; |
||||
case GW54xx: |
||||
calib = &gw54xxq_mmdc_calib; |
||||
break; |
||||
} |
||||
|
||||
if (is_cpu_type(MXC_CPU_MX6Q)) |
||||
mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, |
||||
&mx6dq_grp_ioregs); |
||||
else |
||||
mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, |
||||
&mx6sdl_grp_ioregs); |
||||
mx6_dram_cfg(&sysinfo, calib, mem); |
||||
} |
||||
|
||||
/*
|
||||
* called from C runtime startup code (arch/arm/lib/crt0.S:_main) |
||||
* - we have a stack and a place to store GD, both in SRAM |
||||
* - no variable global data is available |
||||
*/ |
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
struct ventana_board_info ventana_info; |
||||
int board_model; |
||||
|
||||
/*
|
||||
* Zero out global data: |
||||
* - this shoudl be done by crt0.S |
||||
* - failure to zero it will cause i2c_setup to fail |
||||
*/ |
||||
memset((void *)gd, 0, sizeof(struct global_data)); |
||||
|
||||
/* setup AIPS and disable watchdog */ |
||||
arch_cpu_init(); |
||||
|
||||
/* iomux and setup of i2c */ |
||||
board_early_init_f(); |
||||
i2c_setup_iomux(); |
||||
|
||||
/* setup GP timer */ |
||||
timer_init(); |
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */ |
||||
preloader_console_init(); |
||||
|
||||
/* read/validate EEPROM info to determine board model and SDRAM cfg */ |
||||
board_model = read_eeprom(I2C_GSC, &ventana_info); |
||||
|
||||
/* provide some some default: 32bit 128MB */ |
||||
if (GW_UNKNOWN == board_model) { |
||||
ventana_info.sdram_width = 2; |
||||
ventana_info.sdram_size = 3; |
||||
} |
||||
|
||||
/* configure MMDC for SDRAM width/size and per-model calibration */ |
||||
spl_dram_init(8 << ventana_info.sdram_width, |
||||
16 << ventana_info.sdram_size, |
||||
board_model); |
||||
|
||||
/* Clear the BSS. */ |
||||
memset(__bss_start, 0, __bss_end - __bss_start); |
||||
|
||||
/* load/boot image from boot device */ |
||||
board_init_r(NULL, 0); |
||||
} |
||||
|
||||
void reset_cpu(ulong addr) |
||||
{ |
||||
} |
||||
@ -0,0 +1,231 @@ |
||||
/*
|
||||
* Copyright (C) 2014 Gateworks Corporation |
||||
* Author: Tim Harvey <tharvey@gateworks.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#include <common.h> |
||||
#include <nand.h> |
||||
#include <malloc.h> |
||||
|
||||
static nand_info_t mtd; |
||||
static struct nand_chip nand_chip; |
||||
|
||||
static void mxs_nand_command(struct mtd_info *mtd, unsigned int command, |
||||
int column, int page_addr) |
||||
{ |
||||
register struct nand_chip *chip = mtd->priv; |
||||
u32 timeo, time_start; |
||||
|
||||
/* write out the command to the device */ |
||||
chip->cmd_ctrl(mtd, command, NAND_CLE); |
||||
|
||||
/* Serially input address */ |
||||
if (column != -1) { |
||||
chip->cmd_ctrl(mtd, column, NAND_ALE); |
||||
chip->cmd_ctrl(mtd, column >> 8, NAND_ALE); |
||||
} |
||||
if (page_addr != -1) { |
||||
chip->cmd_ctrl(mtd, page_addr, NAND_ALE); |
||||
chip->cmd_ctrl(mtd, page_addr >> 8, NAND_ALE); |
||||
/* One more address cycle for devices > 128MiB */ |
||||
if (chip->chipsize > (128 << 20)) |
||||
chip->cmd_ctrl(mtd, page_addr >> 16, NAND_ALE); |
||||
} |
||||
chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0); |
||||
|
||||
if (command == NAND_CMD_READ0) { |
||||
chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_CLE); |
||||
chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0); |
||||
} |
||||
|
||||
/* wait for nand ready */ |
||||
ndelay(100); |
||||
timeo = (CONFIG_SYS_HZ * 20) / 1000; |
||||
time_start = get_timer(0); |
||||
while (get_timer(time_start) < timeo) { |
||||
if (chip->dev_ready(mtd)) |
||||
break; |
||||
} |
||||
} |
||||
|
||||
static int mxs_flash_ident(struct mtd_info *mtd) |
||||
{ |
||||
register struct nand_chip *chip = mtd->priv; |
||||
int i; |
||||
u8 mfg_id, dev_id; |
||||
u8 id_data[8]; |
||||
struct nand_onfi_params *p = &chip->onfi_params; |
||||
|
||||
/* Reset the chip */ |
||||
chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
||||
|
||||
/* Send the command for reading device ID */ |
||||
chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
||||
|
||||
/* Read manufacturer and device IDs */ |
||||
mfg_id = chip->read_byte(mtd); |
||||
dev_id = chip->read_byte(mtd); |
||||
|
||||
/* Try again to make sure */ |
||||
chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
||||
for (i = 0; i < 8; i++) |
||||
id_data[i] = chip->read_byte(mtd); |
||||
if (id_data[0] != mfg_id || id_data[1] != dev_id) { |
||||
printf("second ID read did not match"); |
||||
return -1; |
||||
} |
||||
debug("0x%02x:0x%02x ", mfg_id, dev_id); |
||||
|
||||
/* read ONFI */ |
||||
chip->onfi_version = 0; |
||||
chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
||||
if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || |
||||
chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') { |
||||
return -2; |
||||
} |
||||
|
||||
/* we have ONFI, probe it */ |
||||
chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
||||
chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); |
||||
mtd->name = p->model; |
||||
mtd->writesize = le32_to_cpu(p->byte_per_page); |
||||
mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; |
||||
mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); |
||||
chip->chipsize = le32_to_cpu(p->blocks_per_lun); |
||||
chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; |
||||
/* Calculate the address shift from the page size */ |
||||
chip->page_shift = ffs(mtd->writesize) - 1; |
||||
chip->phys_erase_shift = ffs(mtd->erasesize) - 1; |
||||
/* Convert chipsize to number of pages per chip -1 */ |
||||
chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
||||
chip->badblockbits = 8; |
||||
|
||||
debug("erasesize=%d (>>%d)\n", mtd->erasesize, chip->phys_erase_shift); |
||||
debug("writesize=%d (>>%d)\n", mtd->writesize, chip->page_shift); |
||||
debug("oobsize=%d\n", mtd->oobsize); |
||||
debug("chipsize=%lld\n", chip->chipsize); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page) |
||||
{ |
||||
register struct nand_chip *chip = mtd->priv; |
||||
int ret; |
||||
|
||||
chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page); |
||||
ret = nand_chip.ecc.read_page(mtd, chip, buf, 1, page); |
||||
if (ret < 0) { |
||||
printf("read_page failed %d\n", ret); |
||||
return -1; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt) |
||||
{ |
||||
register struct nand_chip *chip = mtd->priv; |
||||
unsigned int block = offs >> chip->phys_erase_shift; |
||||
unsigned int page = offs >> chip->page_shift; |
||||
|
||||
debug("%s offs=0x%08x block:%d page:%d\n", __func__, (int)offs, block, |
||||
page); |
||||
chip->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); |
||||
memset(chip->oob_poi, 0, mtd->oobsize); |
||||
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
||||
|
||||
return chip->oob_poi[0] != 0xff; |
||||
} |
||||
|
||||
/* setup mtd and nand structs and init mxs_nand driver */ |
||||
static int mxs_nand_init(void) |
||||
{ |
||||
/* return if already initalized */ |
||||
if (nand_chip.numchips) |
||||
return 0; |
||||
|
||||
/* init mxs nand driver */ |
||||
board_nand_init(&nand_chip); |
||||
mtd.priv = &nand_chip; |
||||
/* set mtd functions */ |
||||
nand_chip.cmdfunc = mxs_nand_command; |
||||
nand_chip.numchips = 1; |
||||
|
||||
/* identify flash device */ |
||||
puts("NAND : "); |
||||
if (mxs_flash_ident(&mtd)) { |
||||
printf("Failed to identify\n"); |
||||
return -1; |
||||
} |
||||
|
||||
/* allocate and initialize buffers */ |
||||
nand_chip.buffers = memalign(ARCH_DMA_MINALIGN, |
||||
sizeof(*nand_chip.buffers)); |
||||
nand_chip.oob_poi = nand_chip.buffers->databuf + mtd.writesize; |
||||
/* setup flash layout (does not scan as we override that) */ |
||||
mtd.size = nand_chip.chipsize; |
||||
nand_chip.scan_bbt(&mtd); |
||||
|
||||
printf("%llu MiB\n", (mtd.size / (1024 * 1024))); |
||||
return 0; |
||||
} |
||||
|
||||
int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) |
||||
{ |
||||
struct nand_chip *chip; |
||||
unsigned int page; |
||||
unsigned int nand_page_per_block; |
||||
unsigned int sz = 0; |
||||
|
||||
if (mxs_nand_init()) |
||||
return -ENODEV; |
||||
chip = mtd.priv; |
||||
page = offs >> chip->page_shift; |
||||
nand_page_per_block = mtd.erasesize / mtd.writesize; |
||||
|
||||
debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page); |
||||
|
||||
size = roundup(size, mtd.writesize); |
||||
while (sz < size) { |
||||
if (mxs_read_page_ecc(&mtd, buf, page) < 0) |
||||
return -1; |
||||
sz += mtd.writesize; |
||||
offs += mtd.writesize; |
||||
page++; |
||||
buf += mtd.writesize; |
||||
|
||||
/*
|
||||
* Check if we have crossed a block boundary, and if so |
||||
* check for bad block. |
||||
*/ |
||||
if (!(page % nand_page_per_block)) { |
||||
/*
|
||||
* Yes, new block. See if this block is good. If not, |
||||
* loop until we find a good block. |
||||
*/ |
||||
while (is_badblock(&mtd, offs, 1)) { |
||||
page = page + nand_page_per_block; |
||||
/* Check i we've reached the end of flash. */ |
||||
if (page >= mtd.size >> chip->page_shift) |
||||
return -ENOMEM; |
||||
} |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int nand_default_bbt(struct mtd_info *mtd) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
void nand_init(void) |
||||
{ |
||||
} |
||||
|
||||
void nand_deselect(void) |
||||
{ |
||||
} |
||||
|
||||
@ -0,0 +1,71 @@ |
||||
/*
|
||||
* Copyright (C) 2014 Gateworks Corporation |
||||
* Author: Tim Harvey <tharvey@gateworks.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __IMX6_SPL_CONFIG_H |
||||
#define __IMX6_SPL_CONFIG_H |
||||
|
||||
#ifdef CONFIG_SPL |
||||
|
||||
#define CONFIG_SPL_FRAMEWORK |
||||
|
||||
/*
|
||||
* see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals: |
||||
* - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF |
||||
* - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well |
||||
* - BOOT ROM stack is at 0x0091FFB8 |
||||
* - if icache/dcache is enabled (eFuse/strapping controlled) then the |
||||
* IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to |
||||
* fit between 0x00907000 and 0x00918000. |
||||
* - Additionally the BOOT ROM loads what they consider the firmware image |
||||
* which consists of a 4K header in front of us that contains the IVT, DCD |
||||
* and some padding thus 'our' max size is really 0x00908000 - 0x00918000 |
||||
* or 64KB |
||||
*/ |
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" |
||||
#define CONFIG_SPL_TEXT_BASE 0x00908000 |
||||
#define CONFIG_SPL_MAX_SIZE (64 * 1024) |
||||
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7" |
||||
#define CONFIG_SPL_STACK 0x0091FFB8 |
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT |
||||
#define CONFIG_SPL_SERIAL_SUPPORT |
||||
#define CONFIG_SPL_I2C_SUPPORT |
||||
#define CONFIG_SPL_GPIO_SUPPORT |
||||
|
||||
/* NAND support */ |
||||
#if defined(CONFIG_SPL_NAND_SUPPORT) |
||||
#define CONFIG_SPL_NAND_MXS |
||||
#define CONFIG_SPL_DMA_SUPPORT |
||||
#endif |
||||
|
||||
/* MMC support */ |
||||
#if defined(CONFIG_SPL_MMC_SUPPORT) |
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138 /* offset 69KB */ |
||||
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ |
||||
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 |
||||
#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024) |
||||
#endif |
||||
|
||||
/* SATA support */ |
||||
#if defined(CONFIG_SPL_SATA_SUPPORT) |
||||
#define CONFIG_SPL_SATA_BOOT_DEVICE 0 |
||||
#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 |
||||
#endif |
||||
|
||||
/* Define the payload for FAT/EXT support */ |
||||
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) |
||||
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" |
||||
#define CONFIG_SPL_LIBDISK_SUPPORT |
||||
#endif |
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x18200000 |
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ |
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x18300000 |
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3200000 /* 50 MB */ |
||||
#define CONFIG_SYS_TEXT_BASE 0x17800000 |
||||
#endif |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue