Enough time has passed since these boards were moved to Orphan. Remove. - Remove board/mbx8xx/* - Remove include/configs/{MBX.h,MBX860T.h} - Clean-up if defined(CONFIG_MBX) - Move the entries from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>master
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@ -1,8 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = mbx8xx.o flash.o vpd.o pcmcia.o
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@ -1,68 +0,0 @@ |
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IMPORTANT NOTE - read before defining CONFIG_SYS_USE_OSCCLK in your board |
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config file!!! |
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WARNING: Wrong settings of this parameter have the potential to |
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damage hardware by running the MBX's CPU at frequencies that exceed |
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it's rating and/or overdriving the it's SPLL! |
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|
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Ramblings: |
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1) Motorola offered 12 different variants of the MBX, 6 823s and 6 860s. |
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2) Of these 12 variants, only 2 were entry level boards. |
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3) I believe that the 2 entry level boards were the only ones that |
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used OSCM clocking. I can't be completely certain of this at this |
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point. |
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4) Motorola never offered an MBX that ran faster than 50Mhz. |
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5) The 10, non-entry level boards, ran at 40Mhz. |
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6) The EXTCLK input has a minimum clock of 15Mhz for the 823/860. |
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7) Motorola no longer sells MBXs. |
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Based on this information, I can surmise that the default power-on |
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reset clocking was one of the following three options. |
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Multiplier SPLL Options |
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------------------------------------ |
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513 OSCM is SPLL input |
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5 OSCM is SPLL input |
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1 EXTCLK is SPLL input |
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The forth option: |
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5 EXTCLK is SPLL input |
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is not possible on MBXs. This is because the minimum EXTCLK input |
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frequency is 15Mhz. 5 * 15Mhz = 75 Mhz. There was no variant that ran |
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above 50 Mhz. |
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The board I have borrowed definitely uses a multiplier of 1 for |
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EXTCLK and runs at 40Mhz. I even went so far as to put a scope on it. |
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One of the two default OSCM modes are most likely what was used on |
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the entry level boards to cheapen them by eliminating the external |
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crystal oscillator. |
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To add insult to injury, the stupid 860 PLPRCR register retains it's |
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multiplication factor through hard resets. You can't clear it out |
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because it is battery backed and once it is set wrong, it stays |
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wrong. The only way to reset it, so that it takes on it's default |
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multiplier is to disconnect all power including external, batteries, |
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as well discharging caps on the board. This precludes the fact that |
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your 860 may be quite DEAD by this time! |
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|
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If you don't setup the multiplication factor for boards that use the |
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OSCM input, they won't run correctly, but at least they won't be |
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dead. |
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Addtionally, there is no good way to determine the clock input source |
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from CPU register data. The only way to deal with this is either hard |
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code it, determine the correct value with some rather NASTY timing |
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loops, or try to grok it from external data sources. Motorola |
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firmware opts for the NASTY timing loops, but needs to configure the |
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serial ports to do so. |
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You may have a legitimate need to define CONFIG_SYS_USE_OSCCLK if your |
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MBX8xx board is using the OSCM clocking mode. |
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You better know what you are doing here. |
@ -1,44 +0,0 @@ |
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#ifndef __csr_h |
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#define __csr_h |
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/*
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* (C) Copyright 2000 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* Control and Status Register definitions for the MBX |
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* |
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*-------------------------------------------------------------------- |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/* bits for control register #1 / status register #1 */ |
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#define CSR1_ETEN 0x80 /* Ethernet Transceiver Enabled */ |
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#define CSR1_ELEN 0x40 /* Ethernet XCVR in Internal Loopback */ |
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#define CSR1_EAEN 0x20 /* Auto selection TP/AUI Enabled */ |
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#define CSR1_TPEN 0x10 /* TP manually selected */ |
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#define CSR1_FDDIS 0x08 /* Full Duplex Mode disabled */ |
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#define CSR1_FCTEN 0x04 /* Collision Testing of XCVR disabled */ |
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#define CSR1_COM1EN 0x02 /* COM1 signals routed to RS232 Transceiver */ |
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#define CSR1_XCVRDIS 0x01 /* Onboard RS232 Transceiver Disabled */ |
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|
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/* bits for control register #2 */ |
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#define CR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ |
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#define CR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ |
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#define CR2_BRDFAIL 0x08 /* Board fail */ |
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#define CR2_SWS1 0x04 /* Software Status #2 LED */ |
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#define CR2_SWS2 0x02 /* Software Status #2 LED */ |
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#define CR2_QSPANRST 0x01 /* Reset QSPAN */ |
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/* bits for status register #2 */ |
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#define SR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ |
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#define SR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ |
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#define SR2_BATGD 0x08 /* Low Voltage indication for onboard bat */ |
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#define SR2_NVBATGD 0x04 /* Low Voltage indication for NVRAM */ |
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#define SR2_RDY 0x02 /* Flash programming status bit */ |
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#define SR2_FT 0x01 /* Reserved for Factory test purposes */ |
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#define MBX_CSR1 (*((uchar *)CONFIG_SYS_CSR_BASE)) |
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#define MBX_CSR2 (*((uchar *)CONFIG_SYS_CSR_BASE + 1)) |
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#endif /* __csr_h */ |
@ -1,98 +0,0 @@ |
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#ifndef __dimm_h |
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#define __dimm_h |
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/*
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* Module name: %M% |
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* Description: |
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* Serial Presence Detect Definitions Module |
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* SCCS identification: %I% |
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* Branch: %B% |
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* Sequence: %S% |
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* Date newest applied delta was created (MM/DD/YY): %G% |
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* Time newest applied delta was created (HH:MM:SS): %U% |
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* SCCS file name %F% |
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* Fully qualified SCCS file name: |
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* %P% |
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* Copyright: |
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* (C) COPYRIGHT MOTOROLA, INC. 1996 |
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* ALL RIGHTS RESERVED |
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* Notes: |
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* 1. All data was taken from an IBM application note titled |
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* "Serial Presence Detect Definitions". |
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* History: |
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* Date Who |
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* |
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* 10/24/96 Rob Baxter |
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* Initial release. |
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* |
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*/ |
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/*
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* serial PD byte assignment address map (256 byte EEPROM) |
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*/ |
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typedef struct dimm |
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{ |
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uchar n_bytes; /* 00 number of bytes written/used */ |
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uchar t_bytes; /* 01 total number of bytes in serial PD device */ |
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uchar fmt; /* 02 fundamental memory type (FPM/EDO/SDRAM) */ |
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uchar n_row; /* 03 number of rows */ |
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uchar n_col; /* 04 number of columns */ |
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uchar n_banks; /* 05 number of banks */ |
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uchar data_w_lo; /* 06 data width */ |
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uchar data_w_hi; /* 07 data width */ |
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uchar ifl; /* 08 interface levels */ |
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uchar a_ras; /* 09 RAS access */ |
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uchar a_cas; /* 0A CAS access */ |
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uchar ct; /* 0B configuration type (non-parity/parity/ECC) */ |
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uchar refresh_rt; /* 0C refresh rate/type */ |
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uchar p_dram_o; /* 0D primary DRAM organization */ |
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uchar s_dram_o; /* 0E secondary DRAM organization (parity/ECC-checkbits) */ |
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uchar reserved[17]; /* 0F reserved fields for future offerings */ |
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uchar ss_info[32]; /* 20 superset information (may be used in the future) */ |
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uchar m_info[64]; /* 40 manufacturer information (optional) */ |
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uchar unused[128]; /* 80 unused storage locations */ |
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} dimm_t; |
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/*
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* memory type definitions |
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*/ |
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#define DIMM_MT_FPM 1 /* standard FPM (fast page mode) DRAM */ |
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#define DIMM_MT_EDO 2 /* EDO (extended data out) */ |
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#define DIMM_MT_PN 3 /* pipelined nibble */ |
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#define DIMM_MT_SDRAM 4 /* SDRAM (synchronous DRAM) */ |
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/*
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* row addresses definitions |
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*/ |
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#define DIMM_RA_RDNDNT (1<<7) /* redundant addressing */ |
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#define DIMM_RA_MASK 0x7f /* number of row addresses mask */ |
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/*
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* module interface levels definitions |
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*/ |
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#define DIMM_IFL_TTL 0 /* TTL/5V tolerant */ |
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#define DIMM_IFL_LVTTL 1 /* LVTTL (not 5V tolerant) */ |
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#define DIMM_IFL_HSTL15 2 /* HSTL 1.5 */ |
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#define DIMM_IFL_SSTL33 3 /* SSTL 3.3 */ |
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#define DIMM_IFL_SSTL25 4 /* SSTL 2.5 */ |
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/*
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* DIMM configuration type definitions |
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*/ |
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#define DIMM_CT_NONE 0 /* none */ |
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#define DIMM_CT_PARITY 1 /* parity */ |
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#define DIMM_CT_ECC 2 /* ECC */ |
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/*
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* row addresses definitions |
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*/ |
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#define DIMM_RRT_SR (1<<7) /* self refresh flag */ |
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#define DIMM_RRT_MASK 0x7f /* refresh rate mask */ |
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#define DIMM_RRT_NRML 0x00 /* normal (15.625us) */ |
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#define DIMM_RRT_R_3_9 0x01 /* reduced .25x (3.9us) */ |
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#define DIMM_RRT_R_7_8 0x02 /* reduced .5x (7.8us) */ |
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#define DIMM_RRT_E_31_3 0x03 /* extended 2x (31.3us) */ |
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#define DIMM_RRT_E_62_5 0x04 /* extended 4x (62.5us) */ |
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#define DIMM_RRT_E_125 0x05 /* extended 8x (125us) */ |
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#endif /* __dimm_h */ |
@ -1,392 +0,0 @@ |
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/*
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* (C) Copyright 2000 |
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* Marius Groeger <mgroeger@sysgo.de> |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Flash Routines for AM290[48]0B devices |
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* |
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*-------------------------------------------------------------------- |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mpc8xx.h> |
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#include "vpd.h" |
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
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static int write_word (flash_info_t *info, ulong dest, ulong data); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long size, totsize; |
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int i; |
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ulong addr; |
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/* Init: no FLASHes known */ |
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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totsize = 0; |
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addr = 0xfc000000; |
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for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { |
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size = flash_get_size((vu_long *)addr, &flash_info[i]); |
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if (flash_info[i].flash_id == FLASH_UNKNOWN) |
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break; |
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totsize += size; |
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addr += size; |
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} |
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addr = 0xfe000000; |
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for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { |
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size = flash_get_size((vu_long *)addr, &flash_info[i]); |
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if (flash_info[i].flash_id == FLASH_UNKNOWN) |
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break; |
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totsize += size; |
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addr += size; |
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} |
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE |
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/* monitor protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_SYS_MONITOR_BASE, |
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CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, |
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&flash_info[0]); |
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#endif |
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return (totsize); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id >> 16) { |
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case 0x1: |
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printf ("AMD "); |
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break; |
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default: |
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printf ("Unknown Vendor "); |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case AMD_ID_F040B: |
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printf ("AM29F040B (4 Mbit)\n"); |
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break; |
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case AMD_ID_F080B: |
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printf ("AM29F080B (8 Mbit)\n"); |
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break; |
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case AMD_ID_F016D: |
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printf ("AM29F016D (16 Mbit)\n"); |
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break; |
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default: |
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printf ("Unknown Chip Type\n"); |
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break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i=0; i<info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", |
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info->start[i], |
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info->protect[i] ? " (RO)" : " " |
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); |
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} |
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printf ("\n"); |
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return; |
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} |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
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{ |
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short i; |
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ulong vendor, devid; |
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ulong base = (ulong)addr; |
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/* Write auto select command: read Manufacturer ID */ |
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addr[0x0555] = 0xAAAAAAAA; |
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addr[0x02AA] = 0x55555555; |
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addr[0x0555] = 0x90909090; |
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vendor = addr[0]; |
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devid = addr[1] & 0xff; |
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/* only support AMD */ |
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if (vendor != 0x01010101) { |
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return 0; |
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} |
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vendor &= 0xf; |
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devid &= 0xff; |
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if (devid == AMD_ID_F040B) { |
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info->flash_id = vendor << 16 | devid; |
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info->sector_count = 8; |
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info->size = info->sector_count * 0x10000; |
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} |
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else if (devid == AMD_ID_F080B) { |
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info->flash_id = vendor << 16 | devid; |
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info->sector_count = 16; |
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info->size = 4 * info->sector_count * 0x10000; |
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} |
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else if (devid == AMD_ID_F016D) { |
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info->flash_id = vendor << 16 | devid; |
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info->sector_count = 32; |
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info->size = 4 * info->sector_count * 0x10000; |
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} |
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else { |
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printf ("## Unknown Flash Type: %08lx\n", devid); |
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return 0; |
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} |
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/* check for protected sectors */ |
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for (i = 0; i < info->sector_count; i++) { |
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/* sector base address */ |
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info->start[i] = base + i * (info->size / info->sector_count); |
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */ |
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/* D0 = 1 if protected */ |
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addr = (volatile unsigned long *)(info->start[i]); |
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info->protect[i] = addr[2] & 1; |
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} |
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/*
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* Prevent writes to uninitialized FLASH. |
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*/ |
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if (info->flash_id != FLASH_UNKNOWN) { |
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addr = (vu_long *)info->start[0]; |
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addr[0] = 0xF0; /* reset bank */ |
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} |
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return (info->size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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vu_long *addr = (vu_long*)(info->start[0]); |
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int flag, prot, sect, l_sect; |
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ulong start, now, last; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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prot = 0; |
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for (sect = s_first; sect <= s_last; sect++) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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l_sect = -1; |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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addr[0x0555] = 0XAAAAAAAA; |
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addr[0x02AA] = 0x55555555; |
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addr[0x0555] = 0x80808080; |
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addr[0x0555] = 0XAAAAAAAA; |
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addr[0x02AA] = 0x55555555; |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect<=s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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addr = (vu_long*)(info->start[sect]); |
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addr[0] = 0x30303030; |
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l_sect = sect; |
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} |
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} |
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|
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts(); |
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/* wait at least 80us - let's wait 1 ms */ |
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udelay (1000); |
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/*
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* We wait for the last triggered sector |
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*/ |
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if (l_sect < 0) |
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goto DONE; |
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start = get_timer (0); |
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last = start; |
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addr = (vu_long*)(info->start[l_sect]); |
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while ((addr[0] & 0x80808080) != 0x80808080) { |
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if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
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printf ("Timeout\n"); |
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return 1; |
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} |
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/* show that we're waiting */ |
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if ((now - last) > 1000) { /* every second */ |
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serial_putc ('.'); |
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last = now; |
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} |
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} |
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DONE: |
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/* reset to read mode */ |
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addr = (volatile unsigned long *)info->start[0]; |
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addr[0] = 0xF0F0F0F0; /* reset bank */ |
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printf (" done\n"); |
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return 0; |
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} |
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|
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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|
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
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{ |
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ulong cp, wp, data; |
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int i, l, rc; |
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|
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wp = (addr & ~3); /* get lower word aligned address */ |
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|
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/*
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* handle unaligned start bytes |
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*/ |
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if ((l = addr - wp) != 0) { |
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data = 0; |
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for (i=0, cp=wp; i<l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i<4 && cnt>0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i=0; i<4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
return (write_word(info, wp, data)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data) |
||||
{ |
||||
vu_long *addr = (vu_long*)(info->start[0]); |
||||
ulong start; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*((vu_long *)dest) & data) != data) { |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0x0555] = 0xAAAAAAAA; |
||||
addr[0x02AA] = 0x55555555; |
||||
addr[0x0555] = 0xA0A0A0A0; |
||||
|
||||
*((vu_long *)dest) = data; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { |
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
||||
return (1); |
||||
} |
||||
} |
||||
return (0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
@ -1,383 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* Board specific routines for the MBX |
||||
* |
||||
* - initialisation |
||||
* - interface to VPD data (mac address, clock speeds) |
||||
* - memory controller |
||||
* - serial io initialisation |
||||
* - ethernet io initialisation |
||||
* |
||||
* ----------------------------------------------------------------- |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <commproc.h> |
||||
#include <mpc8xx.h> |
||||
#include <net.h> |
||||
#include "dimm.h" |
||||
#include "vpd.h" |
||||
#include "csr.h" |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
static const uint sdram_table_40[] = { |
||||
/* DRAM - single read. (offset 0 in upm RAM)
|
||||
*/ |
||||
0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00, |
||||
0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
||||
|
||||
/* DRAM - burst read. (offset 8 in upm RAM)
|
||||
*/ |
||||
0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08, |
||||
0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08, |
||||
0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005, |
||||
0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
||||
|
||||
/* DRAM - single write. (offset 18 in upm RAM)
|
||||
*/ |
||||
0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x33FF4804, |
||||
0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
||||
|
||||
/* DRAM - burst write. (offset 20 in upm RAM)
|
||||
*/ |
||||
0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, |
||||
0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, |
||||
0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005, |
||||
0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
||||
|
||||
/* refresh (offset 30 in upm RAM)
|
||||
*/ |
||||
0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, |
||||
0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
||||
0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
||||
|
||||
/* exception. (offset 3c in upm RAM)
|
||||
*/ |
||||
0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, |
||||
}; |
||||
|
||||
static const uint sdram_table_50[] = { |
||||
/* DRAM - single read. (offset 0 in upm RAM)
|
||||
*/ |
||||
0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04, |
||||
0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005, |
||||
|
||||
/* DRAM - burst read. (offset 8 in upm RAM)
|
||||
*/ |
||||
0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04, |
||||
/* 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04, */ |
||||
0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, |
||||
0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04, |
||||
/* 0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005, */ |
||||
0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005, |
||||
|
||||
/* DRAM - single write. (offset 18 in upm RAM)
|
||||
*/ |
||||
0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804, |
||||
0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
||||
|
||||
/* DRAM - burst write. (offset 20 in upm RAM)
|
||||
*/ |
||||
0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, |
||||
0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, |
||||
0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005, |
||||
0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
||||
|
||||
/* refresh (offset 30 in upm RAM)
|
||||
*/ |
||||
0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, |
||||
0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, |
||||
0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
||||
|
||||
/* exception. (offset 3c in upm RAM)
|
||||
*/ |
||||
0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, |
||||
}; |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
#ifdef CONFIG_SYS_USE_OSCCLK |
||||
static unsigned int get_reffreq(void); |
||||
#endif |
||||
static unsigned int board_get_cpufreq(void); |
||||
|
||||
void mbx_init (void) |
||||
{ |
||||
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile memctl8xx_t *memctl = &immr->im_memctl; |
||||
ulong speed, plprcr, sccr; |
||||
ulong br0_32 = memctl->memc_br0 & 0x400; |
||||
|
||||
/* real-time clock status and control register */ |
||||
immr->im_sitk.sitk_rtcsck = KAPWR_KEY; |
||||
immr->im_sit.sit_rtcsc = 0x00C3; |
||||
|
||||
/* SIEL and SIMASK Registers (see MBX PRG 2-3) */ |
||||
immr->im_siu_conf.sc_simask = 0x00000000; |
||||
immr->im_siu_conf.sc_siel = 0xAAAA0000; |
||||
immr->im_siu_conf.sc_tesr = 0xFFFFFFFF; |
||||
|
||||
/*
|
||||
* Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus: |
||||
* 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h) |
||||
* 2. RAM Specs (see dimm.h) |
||||
* 2. DIMM Specs (see dimm.h) |
||||
*/ |
||||
vpd_init (); |
||||
|
||||
/* system clock and reset control register */ |
||||
immr->im_clkrstk.cark_sccrk = KAPWR_KEY; |
||||
sccr = immr->im_clkrst.car_sccr; |
||||
sccr &= SCCR_MASK; |
||||
sccr |= CONFIG_SYS_SCCR; |
||||
immr->im_clkrst.car_sccr = sccr; |
||||
|
||||
speed = board_get_cpufreq (); |
||||
|
||||
#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0) |
||||
plprcr = CONFIG_SYS_PLPRCR; |
||||
#else |
||||
plprcr = immr->im_clkrst.car_plprcr; |
||||
plprcr &= PLPRCR_MF_MSK; /* isolate MF field */ |
||||
plprcr |= CONFIG_SYS_PLPRCR; /* reset control bits */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SYS_USE_OSCCLK /* See doc/README.MBX ! */ |
||||
plprcr |= ((speed + get_reffreq() / 2) / refclock - 1) << 20; |
||||
#endif |
||||
|
||||
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; |
||||
immr->im_clkrst.car_plprcr = plprcr; |
||||
|
||||
/*
|
||||
* preliminary setup of memory controller: |
||||
* - map Flash, otherwise configuration/status |
||||
* registers won't be accessible when read |
||||
* by board_init_f. |
||||
* - map NVRAM and configuation/status registers. |
||||
* - map pci registers. |
||||
* - DON'T map ram yet, this is done in initdram(). |
||||
*/ |
||||
switch (speed / 1000000) { |
||||
case 40: |
||||
memctl->memc_br0 = 0xFE000000 | br0_32 | 1; |
||||
memctl->memc_or0 = 0xFF800930; |
||||
memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x920; |
||||
memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401; |
||||
break; |
||||
case 50: |
||||
memctl->memc_br0 = 0xFE000000 | br0_32 | 1; |
||||
memctl->memc_or0 = 0xFF800940; |
||||
memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x930; |
||||
memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401; |
||||
break; |
||||
default: |
||||
hang (); |
||||
break; |
||||
} |
||||
#ifdef CONFIG_USE_PCI |
||||
memctl->memc_or5 = CONFIG_SYS_PCIMEM_OR; |
||||
memctl->memc_br5 = CONFIG_SYS_PCIMEM_BASE | 0x001; |
||||
memctl->memc_or6 = CONFIG_SYS_PCIBRIDGE_OR; |
||||
memctl->memc_br6 = CONFIG_SYS_PCIBRIDGE_BASE | 0x001; |
||||
#endif |
||||
/*
|
||||
* FIXME: I do not understand why I have to call this to |
||||
* initialise the control register here before booting from |
||||
* the PCMCIA card but if I do not the Linux kernel falls |
||||
* over in a big heap. If you can answer this question I |
||||
* would like to know about it. |
||||
*/ |
||||
board_ether_init(); |
||||
} |
||||
|
||||
void board_serial_init (void) |
||||
{ |
||||
MBX_CSR1 &= ~(CSR1_COM1EN | CSR1_XCVRDIS); |
||||
} |
||||
|
||||
void board_ether_init (void) |
||||
{ |
||||
MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN); |
||||
MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS; |
||||
} |
||||
|
||||
static unsigned int board_get_cpufreq (void) |
||||
{ |
||||
#ifndef CONFIG_8xx_GCLK_FREQ |
||||
vpd_packet_t *packet; |
||||
ulong *p; |
||||
|
||||
packet = vpd_find_packet (VPD_PID_ICS); |
||||
p = (ulong *)packet->data; |
||||
return *p; |
||||
#else |
||||
return((unsigned int)CONFIG_8xx_GCLK_FREQ ); |
||||
#endif /* CONFIG_8xx_GCLK_FREQ */ |
||||
} |
||||
|
||||
#ifdef CONFIG_SYS_USE_OSCCLK |
||||
static unsigned int get_reffreq (void) |
||||
{ |
||||
vpd_packet_t *packet; |
||||
ulong *p; |
||||
|
||||
packet = vpd_find_packet (VPD_PID_RCS); |
||||
p = (ulong *)packet->data; |
||||
return *p; |
||||
} |
||||
#endif |
||||
|
||||
static void board_get_enetaddr(uchar *addr) |
||||
{ |
||||
int i; |
||||
vpd_packet_t *packet; |
||||
|
||||
packet = vpd_find_packet (VPD_PID_EA); |
||||
for (i = 0; i < 6; i++) |
||||
addr[i] = packet->data[i]; |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
uchar enetaddr[6]; |
||||
|
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { |
||||
board_get_enetaddr(enetaddr); |
||||
eth_setenv_enetaddr("ethaddr", enetaddr); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
*/ |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
vpd_packet_t *packet; |
||||
int i; |
||||
const char *const fmt = |
||||
"\n *** Warning: Low Battery Status - %s Battery ***"; |
||||
|
||||
puts ("Board: "); |
||||
|
||||
packet = vpd_find_packet (VPD_PID_PID); |
||||
for (i = 0; i < packet->size; i++) { |
||||
serial_putc (packet->data[i]); |
||||
} |
||||
packet = vpd_find_packet (VPD_PID_MT); |
||||
for (i = 0; i < packet->size; i++) { |
||||
serial_putc (packet->data[i]); |
||||
} |
||||
serial_putc ('('); |
||||
packet = vpd_find_packet (VPD_PID_FAN); |
||||
for (i = 0; i < packet->size; i++) { |
||||
serial_putc (packet->data[i]); |
||||
} |
||||
serial_putc (')'); |
||||
|
||||
if (!(MBX_CSR2 & SR2_BATGD)) |
||||
printf (fmt, "On-Board"); |
||||
if (!(MBX_CSR2 & SR2_NVBATGD)) |
||||
printf (fmt, "NVRAM"); |
||||
|
||||
serial_putc ('\n'); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
static ulong get_ramsize (dimm_t * dimm) |
||||
{ |
||||
ulong size = 0; |
||||
|
||||
if (dimm->fmt == 1 || dimm->fmt == 2 || dimm->fmt == 3 |
||||
|| dimm->fmt == 4) { |
||||
size = (1 << (dimm->n_row + dimm->n_col)) * dimm->n_banks * |
||||
((dimm->data_w_hi << 8 | dimm->data_w_lo) / 8); |
||||
} |
||||
|
||||
return size; |
||||
} |
||||
|
||||
phys_size_t initdram (int board_type) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
unsigned long ram_sz = 0; |
||||
unsigned long dimm_sz = 0; |
||||
dimm_t vpd_dimm, vpd_dram; |
||||
unsigned int speed = board_get_cpufreq () / 1000000; |
||||
|
||||
if (vpd_read (0xa2, (uchar *) & vpd_dimm, sizeof (vpd_dimm), 0) > 0) { |
||||
dimm_sz = get_ramsize (&vpd_dimm); |
||||
} |
||||
if (vpd_read (0xa6, (uchar *) & vpd_dram, sizeof (vpd_dram), 0) > 0) { |
||||
ram_sz = get_ramsize (&vpd_dram); |
||||
} |
||||
|
||||
/*
|
||||
* Only initialize memory controller when running from FLASH. |
||||
* When running from RAM, don't touch it. |
||||
*/ |
||||
if ((ulong) initdram & 0xff000000) { |
||||
ulong dimm_bank; |
||||
ulong br0_32 = memctl->memc_br0 & 0x400; |
||||
|
||||
switch (speed) { |
||||
case 40: |
||||
upmconfig (UPMA, (uint *) sdram_table_40, |
||||
sizeof (sdram_table_40) / sizeof (uint)); |
||||
memctl->memc_mptpr = 0x0200; |
||||
memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000; |
||||
memctl->memc_or7 = 0xff800930; |
||||
memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; |
||||
break; |
||||
case 50: |
||||
upmconfig (UPMA, (uint *) sdram_table_50, |
||||
sizeof (sdram_table_50) / sizeof (uint)); |
||||
memctl->memc_mptpr = 0x0200; |
||||
memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100; |
||||
memctl->memc_or7 = 0xff800940; |
||||
memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; |
||||
break; |
||||
default: |
||||
hang (); |
||||
break; |
||||
} |
||||
|
||||
/* now map ram and dimm, largest one first */ |
||||
dimm_bank = dimm_sz / 2; |
||||
if (!dimm_sz) { |
||||
memctl->memc_or1 = ~(ram_sz - 1) | 0x400; |
||||
memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81; |
||||
memctl->memc_br2 = 0; |
||||
memctl->memc_br3 = 0; |
||||
} else if (ram_sz > dimm_bank) { |
||||
memctl->memc_or1 = ~(ram_sz - 1) | 0x400; |
||||
memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81; |
||||
memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; |
||||
memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE + ram_sz) | 0x81; |
||||
memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; |
||||
memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + ram_sz + dimm_bank) \
|
||||
| 0x81; |
||||
} else { |
||||
memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; |
||||
memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x81; |
||||
memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; |
||||
memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + dimm_bank) | 0x81; |
||||
memctl->memc_or1 = ~(ram_sz - 1) | 0x400; |
||||
memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE + dimm_sz) | 0x81; |
||||
} |
||||
} |
||||
|
||||
return ram_sz + dimm_sz; |
||||
} |
@ -1,156 +0,0 @@ |
||||
#include <common.h> |
||||
#include <mpc8xx.h> |
||||
#include <pcmcia.h> |
||||
|
||||
#include "csr.h" |
||||
|
||||
#undef CONFIG_PCMCIA |
||||
|
||||
#if defined(CONFIG_CMD_PCMCIA) |
||||
#define CONFIG_PCMCIA |
||||
#endif |
||||
|
||||
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) |
||||
#define CONFIG_PCMCIA |
||||
#endif |
||||
|
||||
#ifdef CONFIG_PCMCIA |
||||
|
||||
/* A lot of this has been taken from the RPX code in this file it works from me.
|
||||
I have added the voltage selection for the MBX board. */ |
||||
|
||||
/* MBX voltage bit in control register #2 */ |
||||
#define CR2_VPP12 ((uchar)0x10) |
||||
#define CR2_VPPVDD ((uchar)0x20) |
||||
#define CR2_VDD5 ((uchar)0x40) |
||||
#define CR2_VDD3 ((uchar)0x80) |
||||
|
||||
#define PCMCIA_BOARD_MSG "MBX860" |
||||
|
||||
int pcmcia_voltage_set (int slot, int vcc, int vpp) |
||||
{ |
||||
uchar reg = 0; |
||||
|
||||
debug ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", |
||||
'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10); |
||||
|
||||
switch (vcc) { |
||||
case 0: |
||||
break; |
||||
case 33: |
||||
reg |= CR2_VDD3; |
||||
break; |
||||
case 50: |
||||
reg |= CR2_VDD5; |
||||
break; |
||||
default: |
||||
return 1; |
||||
} |
||||
|
||||
switch (vpp) { |
||||
case 0: |
||||
break; |
||||
case 33: |
||||
case 50: |
||||
if (vcc == vpp) { |
||||
reg |= CR2_VPPVDD; |
||||
} else { |
||||
return 1; |
||||
} |
||||
break; |
||||
case 120: |
||||
reg |= CR2_VPP12; |
||||
break; |
||||
default: |
||||
return 1; |
||||
} |
||||
|
||||
/* first, turn off all power */ |
||||
MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL); |
||||
|
||||
/* enable new powersettings */ |
||||
MBX_CSR2 |= reg; |
||||
debug ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
int pcmcia_hardware_enable (int slot) |
||||
{ |
||||
volatile pcmconf8xx_t *pcmp; |
||||
uint reg, mask; |
||||
|
||||
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", |
||||
'A' + slot); |
||||
|
||||
udelay (10000); |
||||
|
||||
pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia)); |
||||
|
||||
/* clear interrupt state, and disable interrupts */ |
||||
pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); |
||||
pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_); |
||||
|
||||
/*
|
||||
* Disable interrupts, DMA, and PCMCIA buffers |
||||
* (isolate the interface) and assert RESET signal |
||||
*/ |
||||
debug ("Disable PCMCIA buffers and assert RESET\n"); |
||||
reg = 0; |
||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ |
||||
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ |
||||
PCMCIA_PGCRX (_slot_) = reg; |
||||
udelay (500); |
||||
|
||||
/* remove all power */ |
||||
pcmcia_voltage_set (slot, 0, 0); |
||||
/*
|
||||
* Make sure there is a card in the slot, then configure the interface. |
||||
*/ |
||||
udelay(10000); |
||||
debug ("[%d] %s: PIPR(%p)=0x%x\n", |
||||
__LINE__,__FUNCTION__, |
||||
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr); |
||||
if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) { |
||||
printf (" No Card found\n"); |
||||
return (1); |
||||
} |
||||
|
||||
/*
|
||||
* Power On. |
||||
*/ |
||||
mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_); |
||||
reg = pcmp->pcmc_pipr; |
||||
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg, |
||||
(reg & PCMCIA_VS1 (slot)) ? "n" : "ff", |
||||
(reg & PCMCIA_VS2 (slot)) ? "n" : "ff"); |
||||
|
||||
if ((reg & mask) == mask) { |
||||
pcmcia_voltage_set (_slot_, 50, 0); |
||||
printf (" 5.0V card found: "); |
||||
} else { |
||||
pcmcia_voltage_set (_slot_, 33, 0); |
||||
printf (" 3.3V card found: "); |
||||
} |
||||
|
||||
debug ("Enable PCMCIA buffers and stop RESET\n"); |
||||
reg = PCMCIA_PGCRX (_slot_); |
||||
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ |
||||
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ |
||||
PCMCIA_PGCRX (_slot_) = reg; |
||||
|
||||
udelay (250000); /* some cards need >150 ms to come up :-( */ |
||||
|
||||
debug ("# hardware_enable done\n"); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
#if defined(CONFIG_CMD_PCMCIA) |
||||
int pcmcia_hardware_disable (int slot) |
||||
{ |
||||
return 0; /* No hardware to disable */ |
||||
} |
||||
#endif |
||||
|
||||
#endif /* CONFIG_PCMCIA */ |
@ -1,82 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2000-2010 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
|
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.text : |
||||
{ |
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*) |
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
||||
|
||||
*(.text*) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
_GOT2_TABLE_ = .; |
||||
KEEP(*(.got2)) |
||||
KEEP(*(.got)) |
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); |
||||
_FIXUP_TABLE_ = .; |
||||
KEEP(*(.fixup)) |
||||
} |
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data*) |
||||
*(.sdata*) |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.bss*) |
||||
*(.sbss*) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,122 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib/vsprintf.o (.text) |
||||
lib/crc32.o (.text) |
||||
arch/powerpc/lib/extable.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/env_embedded.o(.text) |
||||
|
||||
*(.text) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,180 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* Code in faintly related to linux/arch/powerpc/8xx_io: |
||||
* MPC8xx CPM I2C interface. Copyright (c) 1999 Dan Malek (dmalek@jlc.net). |
||||
* |
||||
* This file implements functions to read the MBX's Vital Product Data |
||||
* (VPD). I can't use the more general i2c code in mpc8xx/... since I need |
||||
* the VPD at a time where there is no RAM available yet. Hence the VPD is |
||||
* read into a special area in the DPRAM (see config_MBX.h::CFG_DPRAMVPD). |
||||
* |
||||
* ----------------------------------------------------------------- |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#ifdef CONFIG_8xx |
||||
#include <commproc.h> |
||||
#endif |
||||
#include "vpd.h" |
||||
|
||||
/* Location of receive/transmit buffer descriptors
|
||||
* Allocate one transmit bd and one receive bd. |
||||
* IIC_BD_FREE points to free bd space which we'll use as tx buffer. |
||||
*/ |
||||
#define IIC_BD_TX1 (BD_IIC_START + 0*sizeof(cbd_t)) |
||||
#define IIC_BD_TX2 (BD_IIC_START + 1*sizeof(cbd_t)) |
||||
#define IIC_BD_RX (BD_IIC_START + 2*sizeof(cbd_t)) |
||||
#define IIC_BD_FREE (BD_IIC_START + 3*sizeof(cbd_t)) |
||||
|
||||
/* FIXME -- replace 0x2000 with offsetof */ |
||||
#define VPD_P ((vpd_t *)(CONFIG_SYS_IMMR + 0x2000 + CONFIG_SYS_DPRAMVPD)) |
||||
|
||||
/* transmit/receive buffers */ |
||||
#define IIC_RX_LENGTH 128 |
||||
|
||||
#define WITH_MICROCODE_PATCH |
||||
|
||||
vpd_packet_t * vpd_find_packet(u_char ident) |
||||
{ |
||||
vpd_packet_t *packet; |
||||
vpd_t *vpd = VPD_P; |
||||
|
||||
packet = (vpd_packet_t *)&vpd->packets; |
||||
while ((packet->identifier != ident) && packet->identifier != 0xFF) |
||||
{ |
||||
packet = (vpd_packet_t *)((char *)packet + packet->size + 2); |
||||
} |
||||
return packet; |
||||
} |
||||
|
||||
void vpd_init(void) |
||||
{ |
||||
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
||||
volatile cpm8xx_t *cp = &(im->im_cpm); |
||||
volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); |
||||
volatile iic_t *iip; |
||||
#ifdef WITH_MICROCODE_PATCH |
||||
ulong reloc = 0; |
||||
#endif |
||||
|
||||
iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; |
||||
|
||||
/*
|
||||
* kludge: when running from flash, no microcode patch can be |
||||
* installed. However, the DPMEM usually contains non-zero |
||||
* garbage at the relocatable patch base location, so lets clear |
||||
* it now. This way the rest of the code can support the microcode |
||||
* patch dynamically. |
||||
*/ |
||||
if ((ulong)vpd_init & 0xff000000) |
||||
iip->iic_rpbase = 0; |
||||
|
||||
#ifdef WITH_MICROCODE_PATCH |
||||
/* Check for and use a microcode relocation patch. */ |
||||
if ((reloc = iip->iic_rpbase)) |
||||
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; |
||||
#endif |
||||
/* Initialize Port B IIC pins */ |
||||
cp->cp_pbpar |= 0x00000030; |
||||
cp->cp_pbdir |= 0x00000030; |
||||
cp->cp_pbodr |= 0x00000030; |
||||
|
||||
i2c->i2c_i2mod = 0x04; /* filter clock */ |
||||
i2c->i2c_i2add = 0x34; /* select an arbitrary (unique) address */ |
||||
i2c->i2c_i2brg = 0x07; /* make clock run maximum slow */ |
||||
i2c->i2c_i2cmr = 0x00; /* disable interrupts */ |
||||
i2c->i2c_i2cer = 0x1f; /* clear events */ |
||||
i2c->i2c_i2com = 0x01; /* configure i2c to work as master */ |
||||
|
||||
if (vpd_read(0xa4, (uchar*)VPD_P, VPD_EEPROM_SIZE, 0) != VPD_EEPROM_SIZE) |
||||
{ |
||||
hang(); |
||||
} |
||||
} |
||||
|
||||
|
||||
/* Read from I2C.
|
||||
* This is a two step process. First, we send the "dummy" write |
||||
* to set the device offset for the read. Second, we perform |
||||
* the read operation. |
||||
*/ |
||||
int vpd_read(uint iic_device, uchar *buf, int count, int offset) |
||||
{ |
||||
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
||||
volatile cpm8xx_t *cp = &(im->im_cpm); |
||||
volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); |
||||
volatile iic_t *iip; |
||||
volatile cbd_t *tbdf1, *tbdf2, *rbdf; |
||||
uchar *tb; |
||||
uchar event; |
||||
#ifdef WITH_MICROCODE_PATCH |
||||
ulong reloc = 0; |
||||
#endif |
||||
|
||||
iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; |
||||
#ifdef WITH_MICROCODE_PATCH |
||||
/* Check for and use a microcode relocation patch. */ |
||||
if ((reloc = iip->iic_rpbase)) |
||||
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; |
||||
#endif |
||||
tbdf1 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX1]; |
||||
tbdf2 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX2]; |
||||
rbdf = (cbd_t *)&cp->cp_dpmem[IIC_BD_RX]; |
||||
|
||||
/* Send a "dummy write" operation. This is a write request with
|
||||
* only the offset sent, followed by another start condition. |
||||
* This will ensure we start reading from the first location |
||||
* of the EEPROM. |
||||
*/ |
||||
tb = (uchar*)&cp->cp_dpmem[IIC_BD_FREE]; |
||||
tb[0] = iic_device & 0xfe; /* device address */ |
||||
tb[1] = offset; /* offset */ |
||||
tbdf1->cbd_bufaddr = (uint)tb; |
||||
tbdf1->cbd_datlen = 2; |
||||
tbdf1->cbd_sc = 0x8400; |
||||
|
||||
tb += 2; |
||||
tb[0] = iic_device | 1; /* device address */ |
||||
tbdf2->cbd_bufaddr = (uint)tb; |
||||
tbdf2->cbd_datlen = count+1; |
||||
tbdf2->cbd_sc = 0xbc00; |
||||
|
||||
rbdf->cbd_bufaddr = (uint)buf; |
||||
rbdf->cbd_datlen = 0; |
||||
rbdf->cbd_sc = 0xb000; |
||||
|
||||
iip->iic_tbase = IIC_BD_TX1; |
||||
iip->iic_tbptr = IIC_BD_TX1; |
||||
iip->iic_rbase = IIC_BD_RX; |
||||
iip->iic_rbptr = IIC_BD_RX; |
||||
iip->iic_rfcr = 0x15; |
||||
iip->iic_tfcr = 0x15; |
||||
iip->iic_mrblr = count; |
||||
iip->iic_rstate = 0; |
||||
iip->iic_tstate = 0; |
||||
|
||||
i2c->i2c_i2cer = 0x1f; /* clear event mask */ |
||||
i2c->i2c_i2mod |= 1; /* enable iic operation */ |
||||
i2c->i2c_i2com |= 0x80; /* start master */ |
||||
|
||||
/* wait for IIC transfer */ |
||||
do { |
||||
__asm__ volatile ("eieio"); |
||||
event = i2c->i2c_i2cer; |
||||
} while (event == 0); |
||||
|
||||
if ((event & 0x10) || (event & 0x04)) { |
||||
count = -1; |
||||
goto bailout; |
||||
} |
||||
|
||||
bailout: |
||||
i2c->i2c_i2mod &= ~1; /* turn off iic operation */ |
||||
i2c->i2c_i2cer = 0x1f; /* clear event mask */ |
||||
|
||||
return count; |
||||
} |
@ -1,119 +0,0 @@ |
||||
#ifndef __vpd_h |
||||
#define __vpd_h |
||||
|
||||
/*
|
||||
* Module name: %M% |
||||
* Description: |
||||
* Vital Product Data (VPD) Header Module |
||||
* SCCS identification: %I% |
||||
* Branch: %B% |
||||
* Sequence: %S% |
||||
* Date newest applied delta was created (MM/DD/YY): %G% |
||||
* Time newest applied delta was created (HH:MM:SS): %U% |
||||
* SCCS file name %F% |
||||
* Fully qualified SCCS file name: |
||||
* %P% |
||||
* Copyright: |
||||
* (C) COPYRIGHT MOTOROLA, INC. 1996 |
||||
* ALL RIGHTS RESERVED |
||||
* Notes: |
||||
* History: |
||||
* Date Who |
||||
* |
||||
* 10/24/96 Rob Baxter |
||||
* Initial release. |
||||
* |
||||
*/ |
||||
|
||||
#define VPD_EEPROM_SIZE 256 /* EEPROM size in bytes */ |
||||
|
||||
/*
|
||||
* packet tuple identifiers |
||||
* |
||||
* 0x0D - 0xBF reserved |
||||
* 0xC0 - 0xFE user defined |
||||
*/ |
||||
#define VPD_PID_GI 0x00 /* guaranteed illegal */ |
||||
#define VPD_PID_PID 0x01 /* product identifier (ASCII) */ |
||||
#define VPD_PID_FAN 0x02 /* factory assembly-number (ASCII) */ |
||||
#define VPD_PID_SN 0x03 /* serial-number (ASCII) */ |
||||
#define VPD_PID_PCO 0x04 /* product configuration options(binary) */ |
||||
#define VPD_PID_ICS 0x05 /* internal clock speed in HZ (integer) */ |
||||
#define VPD_PID_ECS 0x06 /* external clock speed in HZ (integer) */ |
||||
#define VPD_PID_RCS 0x07 /* reference clock speed in HZ(integer) */ |
||||
#define VPD_PID_EA 0x08 /* ethernet address (binary) */ |
||||
#define VPD_PID_MT 0x09 /* microprocessor type (ASCII) */ |
||||
#define VPD_PID_CRC 0x0A /* EEPROM CRC (integer) */ |
||||
#define VPD_PID_FMC 0x0B /* FLASH memory configuration (binary) */ |
||||
#define VPD_PID_VLSI 0x0C /* VLSI revisions/versions (binary) */ |
||||
#define VPD_PID_TERM 0xFF /* termination */ |
||||
|
||||
/*
|
||||
* VPD structure (format) |
||||
*/ |
||||
#define VPD_EYE_SIZE 8 /* eyecatcher size */ |
||||
typedef struct vpd_header |
||||
{ |
||||
uchar eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "MOTOROLA" */ |
||||
ushort size; /* size of EEPROM */ |
||||
} vpd_header_t; |
||||
|
||||
#define VPD_DATA_SIZE (VPD_EEPROM_SIZE-sizeof(vpd_header_t)) |
||||
typedef struct vpd |
||||
{ |
||||
vpd_header_t header; /* header */ |
||||
uchar packets[VPD_DATA_SIZE]; /* data */ |
||||
} vpd_t; |
||||
|
||||
/*
|
||||
* packet tuple structure (format) |
||||
*/ |
||||
typedef struct vpd_packet |
||||
{ |
||||
uchar identifier; /* identifier (PIDs above) */ |
||||
uchar size; /* size of the following data area */ |
||||
uchar data[1]; /* data (size is dependent upon PID) */ |
||||
} vpd_packet_t; |
||||
|
||||
/*
|
||||
* MBX product configuration options bit definitions |
||||
* |
||||
* Notes: |
||||
* 1. The bit numbering is reversed in perspective with the C compiler. |
||||
*/ |
||||
#define PCO_BBRAM (1<<0) /* battery-backed RAM (BBRAM) and socket */ |
||||
#define PCO_BOOTROM (1<<1) /* boot ROM and socket (i.e., socketed FLASH) */ |
||||
#define PCO_KAPWR (1<<2) /* keep alive power source (lithium battey) and control circuit */ |
||||
#define PCO_ENET_TP (1<<3) /* ethernet twisted pair (TP) connector (RJ45) */ |
||||
#define PCO_ENET_AUI (1<<4) /* ethernet attachment unit interface (AUI) header */ |
||||
#define PCO_PCMCIA (1<<5) /* PCMCIA socket */ |
||||
#define PCO_DIMM (1<<6) /* DIMM module socket */ |
||||
#define PCO_DTT (1<<7) /* digital thermometer and thermostat (DTT) device */ |
||||
#define PCO_LCD (1<<8) /* liquid crystal display (LCD) device */ |
||||
#define PCO_PCI (1<<9) /* PCI-Bus bridge device (QSpan) and ISA-Bus bridge device (Winbond) */ |
||||
#define PCO_PCIO (1<<10) /* PC I/O (COM1, COM2, FDC, LPT, Keyboard/Mouse) */ |
||||
#define PCO_EIDE (1<<11) /* enhanced IDE (EIDE) header */ |
||||
#define PCO_FDC (1<<12) /* floppy disk controller (FDC) header */ |
||||
#define PCO_LPT_8XX (1<<13) /* parallel port header via MPC8xx */ |
||||
#define PCO_LPT_PCIO (1<<14) /* parallel port header via PC I/O */ |
||||
|
||||
/*
|
||||
* FLASH memory configuration packet data |
||||
*/ |
||||
typedef struct vpd_fmc |
||||
{ |
||||
ushort mid; /* manufacturer's idenitfier */ |
||||
ushort did; /* manufacturer's device idenitfier */ |
||||
uchar ddw; /* device data width (e.g., 8-bits, 16-bits) */ |
||||
uchar nod; /* number of devices present */ |
||||
uchar noc; /* number of columns */ |
||||
uchar cw; /* column width in bits */ |
||||
uchar wedw; /* write/erase data width */ |
||||
} vpd_fmc_t; |
||||
|
||||
/* function prototypes */ |
||||
extern void vpd_init(void); |
||||
extern int vpd_read(uint iic_device, uchar *buf, int count, int offset); |
||||
extern vpd_packet_t *vpd_find_packet(u_char ident); |
||||
|
||||
#endif /* __vpd_h */ |
@ -1,290 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* Configuation settings for the MBX8xx board. |
||||
* |
||||
* ----------------------------------------------------------------- |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
/*
|
||||
* Changed 2002-10-01 |
||||
* Added PCMCIA defines mostly taken from other U-Boot boards that |
||||
* have PCMCIA already working. If you find any bugs, incorrect assumptions |
||||
* feel free to fix them yourself and submit a patch. |
||||
* Rod Boyce <rod_boyce@stratexnet.com. |
||||
*/ |
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ |
||||
#define CONFIG_MBX 1 /* ...on an MBX module */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xfe000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 9600 |
||||
/* Define this to use the PCI bus */ |
||||
#undef CONFIG_USE_PCI |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
#define CONFIG_8xx_GCLK_FREQ (50000000UL) |
||||
#if 1 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
#define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */ |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ |
||||
"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
|
||||
"nfsaddrs=10.0.0.99:10.0.0.2" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_SDRAM |
||||
#define CONFIG_CMD_PCMCIA |
||||
#define CONFIG_CMD_IDE |
||||
|
||||
|
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical memory map as defined by the MBX PGM |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFA200000 /* Internal Memory Mapped Register*/ |
||||
#define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM */ |
||||
#define CONFIG_SYS_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ |
||||
#define CONFIG_SYS_CSR_BASE 0xFA100000 /* Control/Status Registers */ |
||||
#define CONFIG_SYS_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ |
||||
#define CONFIG_SYS_PCIMEM_OR 0xA0000108 |
||||
#define CONFIG_SYS_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ |
||||
#define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ |
||||
#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Offset in DPMEM where we keep the VPD data |
||||
*/ |
||||
#define CONFIG_SYS_DPRAMVPD (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0xfe000000 |
||||
#ifdef DEBUG |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#endif |
||||
#undef CONFIG_SYS_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM Configuration |
||||
* |
||||
* Note: the MBX is special because there is already a firmware on this |
||||
* board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we |
||||
* access the NVRAM at the offset 0x1000. |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000) |
||||
#define CONFIG_ENV_SIZE 0x1000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
/* #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit - leave PLL multiplication factor unchanged ! |
||||
*/ |
||||
#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) |
||||
#define CONFIG_SYS_SCCR SCCR_TBS |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6 |
||||
|
||||
#define CONFIG_PCMCIA_SLOT_A 1 |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Debug Entry Mode |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -1,395 +0,0 @@ |
||||
/*
|
||||
* A collection of structures, addresses, and values associated with |
||||
* the Motorola 860T MBX board. |
||||
* Copied from the FADS stuff, which was originally copied from the MBX stuff! |
||||
* Magnus Damm added defines for 8xxrom and extended bd_info. |
||||
* Helmut Buchsbaum added bitvalues for BCSRx |
||||
* Rob Taylor coverted it back to MBX |
||||
* |
||||
* Copyright (c) 1998 Dan Malek (dmalek@jlc.net) |
||||
*/ |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#include <mpc8xx_irq.h> |
||||
|
||||
#define CONFIG_MPC860 1 |
||||
#define CONFIG_MPC860T 1 |
||||
#define CONFIG_MBX 1 |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xfe000000 |
||||
|
||||
#define CONFIG_8xx_CPUCLOCK 40 |
||||
#define CONFIG_8xx_BUSCLOCK (CONFIG_8xx_CPUCLOCK) |
||||
#define TARGET_SYSTEM_FREQUENCY 40 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
#define MPC8XX_FACT 10 /* Multiply by 10 */ |
||||
#define MPC8XX_XIN 40000000 /* 50 MHz in */ |
||||
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#if 1 |
||||
#define CONFIG_8xx_BOOTDELAY -1 /* autoboot disabled */ |
||||
#define CONFIG_8xx_TFTP_MODE |
||||
#else |
||||
#define CONFIG_8xx_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#undef CONFIG_8xx_TFTP_MODE |
||||
#endif |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_DRAM_SPEED (CONFIG_8xx_BUSCLOCK) /* MHz */ |
||||
#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ |
||||
#define CONFIG_BOOTARGS " " |
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#undef CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0800000 /* 4 ... 8 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFFA00000 |
||||
#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) |
||||
#define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM */ |
||||
#define CONFIG_SYS_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ |
||||
#define CONFIG_SYS_CSR_BASE 0xFA100000 /* Control/Status Registers */ |
||||
#define CONFIG_SYS_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ |
||||
#define CONFIG_SYS_PCIMEM_OR 0xA0000108 |
||||
#define CONFIG_SYS_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ |
||||
#define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ |
||||
#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Offset in DPMEM where we keep the VPD data |
||||
*/ |
||||
#define CONFIG_SYS_DPRAMVPD (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x00000000 |
||||
/*0xFE000000*/ |
||||
#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CONFIG_SYS_HWINFO_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_SYS_HWINFO_LEN) |
||||
#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM Configuration |
||||
* |
||||
* Note: the MBX is special because there is already a firmware on this |
||||
* board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we |
||||
* access the NVRAM at the offset 0x1000. |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000) |
||||
#define CONFIG_ENV_SIZE 0x1000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit - leave PLL multiplication factor unchanged ! |
||||
*/ |
||||
#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) |
||||
#define CONFIG_SYS_SCCR SCCR_TBS |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/* Because of the way the 860 starts up and assigns CS0 the
|
||||
* entire address space, we have to set the memory controller |
||||
* differently. Normally, you write the option register |
||||
* first, and then enable the chip select by writing the |
||||
* base register. For CS0, you must write the base register |
||||
* first, followed by the option register. |
||||
*/ |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
/* the other CS:s are determined by looking at parameters in BCSRx */ |
||||
|
||||
|
||||
#define BCSR_ADDR ((uint) 0xFF010000) |
||||
#define BCSR_SIZE ((uint)(64 * 1024)) |
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0xFF010000 /* FLASH bank #0 */ |
||||
|
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xFFF00000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ |
||||
#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_V ) |
||||
|
||||
/* BCSRx - Board Control and Status Registers */ |
||||
#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
||||
#define CONFIG_SYS_OR1_PRELIM 0xFFC00000 | OR_ACS_DIV4 |
||||
#define CONFIG_SYS_BR1_PRELIM (0x00000000 | BR_MS_UPMA | BR_V ) |
||||
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
#define CONFIG_SYS_MAMR 0x13821000 |
||||
|
||||
/* values according to the manual */ |
||||
|
||||
|
||||
#define PCMCIA_MEM_ADDR ((uint)0xff020000) |
||||
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) |
||||
|
||||
#define BCSR0 ((uint) (BCSR_ADDR + 00)) |
||||
#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) |
||||
#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) |
||||
#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) |
||||
#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) |
||||
|
||||
/* FADS bitvalues by Helmut Buchsbaum
|
||||
* see MPC8xxADS User's Manual for a proper description |
||||
* of the following structures |
||||
*/ |
||||
|
||||
#define BCSR0_ERB ((uint)0x80000000) |
||||
#define BCSR0_IP ((uint)0x40000000) |
||||
#define BCSR0_BDIS ((uint)0x10000000) |
||||
#define BCSR0_BPS_MASK ((uint)0x0C000000) |
||||
#define BCSR0_ISB_MASK ((uint)0x01800000) |
||||
#define BCSR0_DBGC_MASK ((uint)0x00600000) |
||||
#define BCSR0_DBPC_MASK ((uint)0x00180000) |
||||
#define BCSR0_EBDF_MASK ((uint)0x00060000) |
||||
|
||||
#define BCSR1_FLASH_EN ((uint)0x80000000) |
||||
#define BCSR1_DRAM_EN ((uint)0x40000000) |
||||
#define BCSR1_ETHEN ((uint)0x20000000) |
||||
#define BCSR1_IRDEN ((uint)0x10000000) |
||||
#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) |
||||
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) |
||||
#define BCSR1_BCSR_EN ((uint)0x02000000) |
||||
#define BCSR1_RS232EN_1 ((uint)0x01000000) |
||||
#define BCSR1_PCCEN ((uint)0x00800000) |
||||
#define BCSR1_PCCVCC0 ((uint)0x00400000) |
||||
#define BCSR1_PCCVPP_MASK ((uint)0x00300000) |
||||
#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) |
||||
#define BCSR1_RS232EN_2 ((uint)0x00040000) |
||||
#define BCSR1_SDRAM_EN ((uint)0x00020000) |
||||
#define BCSR1_PCCVCC1 ((uint)0x00010000) |
||||
|
||||
#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) |
||||
#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) |
||||
#define BCSR2_DRAM_PD_SHIFT (23) |
||||
#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) |
||||
#define BCSR2_DBREVNR_MASK ((uint)0x00030000) |
||||
|
||||
#define BCSR3_DBID_MASK ((ushort)0x3800) |
||||
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) |
||||
#define BCSR3_BREVNR0 ((ushort)0x0080) |
||||
#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) |
||||
#define BCSR3_BREVN1 ((ushort)0x0008) |
||||
#define BCSR3_BREVN2_MASK ((ushort)0x0003) |
||||
|
||||
#define BCSR4_ETHLOOP ((uint)0x80000000) |
||||
#define BCSR4_TFPLDL ((uint)0x40000000) |
||||
#define BCSR4_TPSQEL ((uint)0x20000000) |
||||
#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_USB_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860SAR |
||||
#define BCSR4_UTOPIA_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC860SAR */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETH_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#define BCSR4_USB_SPEED ((uint)0x04000000) |
||||
#define BCSR4_VCCO ((uint)0x02000000) |
||||
#define BCSR4_VIDEO_ON ((uint)0x00800000) |
||||
#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) |
||||
#define BCSR4_VIDEO_RST ((uint)0x00200000) |
||||
#define BCSR4_MODEM_EN ((uint)0x00100000) |
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000) |
||||
|
||||
#define CONFIG_DRAM_40MHZ 1 |
||||
|
||||
#ifdef CONFIG_MPC860T |
||||
|
||||
/* Interrupt level assignments.
|
||||
*/ |
||||
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ |
||||
|
||||
#endif /* CONFIG_MPC860T */ |
||||
|
||||
/* We don't use the 8259.
|
||||
*/ |
||||
#define NR_8259_INTS 0 |
||||
|
||||
#define CONFIG_CMD_NET |
||||
/*
|
||||
* MPC8xx CPM Options |
||||
*/ |
||||
#define CONFIG_SCC_ENET 1 |
||||
#define CONFIG_SCC1_ENET 1 |
||||
#define CONFIG_FEC_ENET 1 |
||||
#undef CONFIG_CPM_IIC |
||||
#undef CONFIG_UCODE_PATCH |
||||
|
||||
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000 |
||||
|
||||
|
||||
/* PCMCIA configuration */ |
||||
|
||||
#define PCMCIA_MAX_SLOTS 2 |
||||
|
||||
#ifdef CONFIG_MPC860 |
||||
#define PCMCIA_SLOT_A 1 |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue