Last user of this driver went away in June 2015 in commit
d928664f41
("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Acked-by: Heiko Schocher <hs@denx.de>
lime2-spi
parent
ed9072c797
commit
d70c79fa89
@ -1,275 +0,0 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2004 Tundra Semiconductor Corp. |
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* Author: Alex Bounine |
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* |
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* NOTE: This driver should be converted to driver model before June 2017. |
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* Please see doc/driver-model/i2c-howto.txt for instructions. |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <tsi108.h> |
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#if defined(CONFIG_CMD_I2C) |
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#define I2C_DELAY 100000 |
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#undef DEBUG_I2C |
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#ifdef DEBUG_I2C |
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#define DPRINT(x) printf (x) |
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#else |
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#define DPRINT(x) |
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#endif |
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/* All functions assume that Tsi108 I2C block is the only master on the bus */ |
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/* I2C read helper function */ |
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void i2c_init(int speed, int slaveaddr) |
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{ |
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/*
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* The TSI108 has a fixed I2C clock rate and doesn't support slave |
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* operation. This function only exists as a stub to fit into the |
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* U-Boot I2C API. |
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*/ |
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} |
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static int i2c_read_byte ( |
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uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */ |
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uchar chip_addr,/* I2C device address on the bus */ |
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uint byte_addr, /* Byte address within I2C device */ |
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uchar * buffer /* pointer to data buffer */ |
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) |
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{ |
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u32 temp; |
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u32 to_count = I2C_DELAY; |
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u32 op_status = TSI108_I2C_TIMEOUT_ERR; |
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u32 chan_offset = TSI108_I2C_OFFSET; |
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DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n", |
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i2c_chan, chip_addr, byte_addr)); |
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if (0 != i2c_chan) |
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chan_offset = TSI108_I2C_SDRAM_OFFSET; |
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/* Check if I2C operation is in progress */ |
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temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); |
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if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | |
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I2C_CNTRL2_START))) { |
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/* Set device address and operation (read = 0) */ |
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temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) | |
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((chip_addr >> 3) & 0x0F); |
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*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) = |
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temp; |
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/* Issue the read command
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* (at this moment all other parameters are 0 |
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* (size = 1 byte, lane = 0) |
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*/ |
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*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) = |
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(I2C_CNTRL2_START); |
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/* Wait until operation completed */ |
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do { |
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/* Read I2C operation status */ |
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temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); |
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if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) { |
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if (0 == (temp & |
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(I2C_CNTRL2_I2C_CFGERR | |
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I2C_CNTRL2_I2C_TO_ERR)) |
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) { |
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op_status = TSI108_I2C_SUCCESS; |
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temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + |
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chan_offset + |
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I2C_RD_DATA); |
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*buffer = (u8) (temp & 0xFF); |
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} else { |
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/* report HW error */ |
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op_status = TSI108_I2C_IF_ERROR; |
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DPRINT (("I2C HW error reported: 0x%02x\n", temp)); |
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} |
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break; |
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} |
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} while (to_count--); |
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} else { |
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op_status = TSI108_I2C_IF_BUSY; |
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DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); |
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} |
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DPRINT (("I2C read_byte() status: 0x%02x\n", op_status)); |
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return op_status; |
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} |
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/*
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* I2C Read interface as defined in "include/i2c.h" : |
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* chip_addr: I2C chip address, range 0..127 |
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* (to read from SPD channel EEPROM use (0xD0 ... 0xD7) |
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* NOTE: The bit 7 in the chip_addr serves as a channel select. |
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* This hack is for enabling "i2c sdram" command on Tsi108 boards |
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* without changes to common code. Used for I2C reads only. |
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* byte_addr: Memory or register address within the chip |
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* alen: Number of bytes to use for addr (typically 1, 2 for larger |
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* memories, 0 for register type devices with only one |
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* register) |
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* buffer: Pointer to destination buffer for data to be read |
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* len: How many bytes to read |
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* |
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* Returns: 0 on success, not 0 on failure |
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*/ |
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int i2c_read (uchar chip_addr, uint byte_addr, int alen, |
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uchar * buffer, int len) |
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{ |
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u32 op_status = TSI108_I2C_PARAM_ERR; |
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u32 i2c_if = 0; |
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/* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/ |
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if (0xD0 == (chip_addr & ~0x07)) { |
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i2c_if = 1; |
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chip_addr &= 0x7F; |
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} |
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/* Check for valid I2C address */ |
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if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { |
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while (len--) { |
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op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++); |
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if (TSI108_I2C_SUCCESS != op_status) { |
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DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len)); |
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break; |
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} |
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} |
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} |
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DPRINT (("I2C read() status: 0x%02x\n", op_status)); |
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return op_status; |
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} |
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/* I2C write helper function */ |
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static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */ |
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uint byte_addr, /* Byte address within I2C device */ |
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uchar * buffer /* pointer to data buffer */ |
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) |
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{ |
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u32 temp; |
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u32 to_count = I2C_DELAY; |
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u32 op_status = TSI108_I2C_TIMEOUT_ERR; |
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/* Check if I2C operation is in progress */ |
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temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); |
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if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) { |
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/* Place data into the I2C Tx Register */ |
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*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + |
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I2C_TX_DATA) = (u32) * buffer; |
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/* Set device address and operation */ |
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temp = |
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I2C_CNTRL1_I2CWRITE | (byte_addr << 16) | |
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((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F); |
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*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + |
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I2C_CNTRL1) = temp; |
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/* Issue the write command (at this moment all other parameters
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* are 0 (size = 1 byte, lane = 0) |
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*/ |
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*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + |
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I2C_CNTRL2) = (I2C_CNTRL2_START); |
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op_status = TSI108_I2C_TIMEOUT_ERR; |
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/* Wait until operation completed */ |
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do { |
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/* Read I2C operation status */ |
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temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); |
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if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) { |
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if (0 == (temp & |
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(I2C_CNTRL2_I2C_CFGERR | |
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I2C_CNTRL2_I2C_TO_ERR))) { |
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op_status = TSI108_I2C_SUCCESS; |
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} else { |
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/* report detected HW error */ |
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op_status = TSI108_I2C_IF_ERROR; |
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DPRINT (("I2C HW error reported: 0x%02x\n", temp)); |
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} |
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break; |
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} |
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} while (to_count--); |
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} else { |
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op_status = TSI108_I2C_IF_BUSY; |
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DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); |
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} |
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return op_status; |
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} |
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/*
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* I2C Write interface as defined in "include/i2c.h" : |
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* chip_addr: I2C chip address, range 0..127 |
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* byte_addr: Memory or register address within the chip |
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* alen: Number of bytes to use for addr (typically 1, 2 for larger |
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* memories, 0 for register type devices with only one |
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* register) |
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* buffer: Pointer to data to be written |
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* len: How many bytes to write |
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* |
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* Returns: 0 on success, not 0 on failure |
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*/ |
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int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer, |
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int len) |
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{ |
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u32 op_status = TSI108_I2C_PARAM_ERR; |
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/* Check for valid I2C address */ |
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if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { |
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while (len--) { |
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op_status = |
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i2c_write_byte (chip_addr, byte_addr++, buffer++); |
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if (TSI108_I2C_SUCCESS != op_status) { |
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DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len)); |
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break; |
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} |
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} |
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} |
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return op_status; |
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} |
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/*
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* I2C interface function as defined in "include/i2c.h". |
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* Probe the given I2C chip address by reading single byte from offset 0. |
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* Returns 0 if a chip responded, not 0 on failure. |
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*/ |
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int i2c_probe (uchar chip) |
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{ |
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u32 tmp; |
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/*
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* Try to read the first location of the chip. |
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* The Tsi108 HW doesn't support sending just the chip address |
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* and checkong for an <ACK> back. |
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*/ |
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return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); |
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} |
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#endif |
@ -1,207 +0,0 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/*****************************************************************************
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* (C) Copyright 2003; Tundra Semiconductor Corp. |
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* (C) Copyright 2006; Freescale Semiconductor Corp. |
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*****************************************************************************/ |
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/*
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* FILENAME: tsi108.h |
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* |
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* Originator: Alex Bounine |
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* |
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* DESCRIPTION: |
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* Common definitions for the Tundra Tsi108 bridge chip |
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* |
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*/ |
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#ifndef _TSI108_H_ |
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#define _TSI108_H_ |
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#define TSI108_HLP_REG_OFFSET (0x0000) |
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#define TSI108_PCI_REG_OFFSET (0x1000) |
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#define TSI108_CLK_REG_OFFSET (0x2000) |
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#define TSI108_PB_REG_OFFSET (0x3000) |
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#define TSI108_SD_REG_OFFSET (0x4000) |
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#define TSI108_MPIC_REG_OFFSET (0x7400) |
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#define PB_ID (0x000) |
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#define PB_RSR (0x004) |
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#define PB_BUS_MS_SELECT (0x008) |
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#define PB_ISR (0x00C) |
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#define PB_ARB_CTRL (0x018) |
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#define PB_PVT_CTRL2 (0x034) |
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#define PB_SCR (0x400) |
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#define PB_ERRCS (0x404) |
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#define PB_AERR (0x408) |
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#define PB_REG_BAR (0x410) |
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#define PB_OCN_BAR1 (0x414) |
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#define PB_OCN_BAR2 (0x418) |
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#define PB_SDRAM_BAR1 (0x41C) |
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#define PB_SDRAM_BAR2 (0x420) |
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#define PB_MCR (0xC00) |
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#define PB_MCMD (0xC04) |
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#define HLP_B0_ADDR (0x000) |
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#define HLP_B1_ADDR (0x010) |
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#define HLP_B2_ADDR (0x020) |
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#define HLP_B3_ADDR (0x030) |
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#define HLP_B0_MASK (0x004) |
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#define HLP_B1_MASK (0x014) |
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#define HLP_B2_MASK (0x024) |
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#define HLP_B3_MASK (0x034) |
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#define HLP_B0_CTRL0 (0x008) |
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#define HLP_B1_CTRL0 (0x018) |
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#define HLP_B2_CTRL0 (0x028) |
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#define HLP_B3_CTRL0 (0x038) |
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#define HLP_B0_CTRL1 (0x00C) |
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#define HLP_B1_CTRL1 (0x01C) |
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#define HLP_B2_CTRL1 (0x02C) |
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#define HLP_B3_CTRL1 (0x03C) |
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#define PCI_CSR (0x004) |
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#define PCI_P2O_BAR0 (0x010) |
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#define PCI_P2O_BAR0_UPPER (0x014) |
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#define PCI_P2O_BAR2 (0x018) |
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#define PCI_P2O_BAR2_UPPER (0x01C) |
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#define PCI_P2O_BAR3 (0x020) |
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#define PCI_P2O_BAR3_UPPER (0x024) |
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#define PCI_MISC_CSR (0x040) |
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#define PCI_P2O_PAGE_SIZES (0x04C) |
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#define PCI_PCIX_STAT (0x0F4) |
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#define PCI_IRP_STAT (0x184) |
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#define PCI_PFAB_BAR0 (0x204) |
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#define PCI_PFAB_BAR0_UPPER (0x208) |
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#define PCI_PFAB_IO (0x20C) |
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#define PCI_PFAB_IO_UPPER (0x210) |
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#define PCI_PFAB_MEM32 (0x214) |
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#define PCI_PFAB_MEM32_REMAP (0x218) |
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#define PCI_PFAB_MEM32_MASK (0x21C) |
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#define CG_PLL0_CTRL0 (0x210) |
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#define CG_PLL0_CTRL1 (0x214) |
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#define CG_PLL1_CTRL0 (0x220) |
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#define CG_PLL1_CTRL1 (0x224) |
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#define CG_PWRUP_STATUS (0x234) |
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#define MPIC_CSR(n) (0x30C + (n * 0x40)) |
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#define SD_CTRL (0x000) |
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#define SD_STATUS (0x004) |
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#define SD_TIMING (0x008) |
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#define SD_REFRESH (0x00C) |
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#define SD_INT_STATUS (0x010) |
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#define SD_INT_ENABLE (0x014) |
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#define SD_INT_SET (0x018) |
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#define SD_D0_CTRL (0x020) |
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#define SD_D1_CTRL (0x024) |
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#define SD_D0_BAR (0x028) |
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#define SD_D1_BAR (0x02C) |
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#define SD_ECC_CTRL (0x040) |
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#define SD_DLL_STATUS (0x250) |
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#define TS_SD_CTRL_ENABLE (1 << 31) |
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#define PB_ERRCS_ES (1 << 1) |
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#define PB_ISR_PBS_RD_ERR (1 << 8) |
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#define PCI_IRP_STAT_P_CSR (1 << 23) |
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/*
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* I2C : Register address offset definitions |
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*/ |
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#define I2C_CNTRL1 (0x00000000) |
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#define I2C_CNTRL2 (0x00000004) |
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#define I2C_RD_DATA (0x00000008) |
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#define I2C_TX_DATA (0x0000000c) |
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/*
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* I2C : Register Bit Masks and Reset Values |
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* definitions for every register |
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*/ |
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/* I2C_CNTRL1 : Reset Value */ |
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#define I2C_CNTRL1_RESET_VALUE (0x0000000a) |
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/* I2C_CNTRL1 : Register Bits Masks Definitions */ |
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#define I2C_CNTRL1_DEVCODE (0x0000000f) |
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#define I2C_CNTRL1_PAGE (0x00000700) |
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#define I2C_CNTRL1_BYTADDR (0x00ff0000) |
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#define I2C_CNTRL1_I2CWRITE (0x01000000) |
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/* I2C_CNTRL1 : Read/Write Bit Mask Definition */ |
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#define I2C_CNTRL1_RWMASK (0x01ff070f) |
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/* I2C_CNTRL1 : Unused/Reserved bits Definition */ |
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#define I2C_CNTRL1_RESERVED (0xfe00f8f0) |
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/* I2C_CNTRL2 : Reset Value */ |
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#define I2C_CNTRL2_RESET_VALUE (0x00000000) |
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/* I2C_CNTRL2 : Register Bits Masks Definitions */ |
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#define I2C_CNTRL2_SIZE (0x00000003) |
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#define I2C_CNTRL2_LANE (0x0000000c) |
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#define I2C_CNTRL2_MULTIBYTE (0x00000010) |
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#define I2C_CNTRL2_START (0x00000100) |
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#define I2C_CNTRL2_WR_STATUS (0x00010000) |
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#define I2C_CNTRL2_RD_STATUS (0x00020000) |
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#define I2C_CNTRL2_I2C_TO_ERR (0x04000000) |
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#define I2C_CNTRL2_I2C_CFGERR (0x08000000) |
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#define I2C_CNTRL2_I2C_CMPLT (0x10000000) |
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/* I2C_CNTRL2 : Read/Write Bit Mask Definition */ |
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#define I2C_CNTRL2_RWMASK (0x0000011f) |
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/* I2C_CNTRL2 : Unused/Reserved bits Definition */ |
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#define I2C_CNTRL2_RESERVED (0xe3fcfee0) |
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/* I2C_RD_DATA : Reset Value */ |
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#define I2C_RD_DATA_RESET_VALUE (0x00000000) |
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/* I2C_RD_DATA : Register Bits Masks Definitions */ |
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#define I2C_RD_DATA_RBYTE0 (0x000000ff) |
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#define I2C_RD_DATA_RBYTE1 (0x0000ff00) |
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#define I2C_RD_DATA_RBYTE2 (0x00ff0000) |
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#define I2C_RD_DATA_RBYTE3 (0xff000000) |
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/* I2C_RD_DATA : Read/Write Bit Mask Definition */ |
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#define I2C_RD_DATA_RWMASK (0x00000000) |
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/* I2C_RD_DATA : Unused/Reserved bits Definition */ |
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#define I2C_RD_DATA_RESERVED (0x00000000) |
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/* I2C_TX_DATA : Reset Value */ |
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#define I2C_TX_DATA_RESET_VALUE (0x00000000) |
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/* I2C_TX_DATA : Register Bits Masks Definitions */ |
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#define I2C_TX_DATA_TBYTE0 (0x000000ff) |
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#define I2C_TX_DATA_TBYTE1 (0x0000ff00) |
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#define I2C_TX_DATA_TBYTE2 (0x00ff0000) |
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#define I2C_TX_DATA_TBYTE3 (0xff000000) |
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/* I2C_TX_DATA : Read/Write Bit Mask Definition */ |
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#define I2C_TX_DATA_RWMASK (0xffffffff) |
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/* I2C_TX_DATA : Unused/Reserved bits Definition */ |
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#define I2C_TX_DATA_RESERVED (0x00000000) |
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|
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#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */ |
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#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */ |
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|
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#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */ |
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/* I2C status codes */ |
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#define TSI108_I2C_SUCCESS 0 |
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#define TSI108_I2C_PARAM_ERR 1 |
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#define TSI108_I2C_TIMEOUT_ERR 2 |
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#define TSI108_I2C_IF_BUSY 3 |
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#define TSI108_I2C_IF_ERROR 4 |
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|
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#endif /* _TSI108_H_ */ |
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Reference in new issue