Tom Rini
9 years ago
commit
d8c4eb60f8
@ -0,0 +1,54 @@ |
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <fdt_support.h> |
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#include <fdtdec.h> |
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#include <asm/arch/tegra.h> |
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extern unsigned long nvtboot_boot_x0; |
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/*
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* Attempt to use /chosen/nvidia,ether-mac in the nvtboot DTB to U-Boot's |
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* ethaddr environment variable if possible. |
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*/ |
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static int set_ethaddr_from_nvtboot(void) |
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{ |
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const void *nvtboot_blob = (void *)nvtboot_boot_x0; |
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int ret, node, len; |
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const u32 *prop; |
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/* Already a valid address in the environment? If so, keep it */ |
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if (getenv("ethaddr")) |
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return 0; |
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node = fdt_path_offset(nvtboot_blob, "/chosen"); |
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if (node < 0) { |
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printf("Can't find /chosen node in nvtboot DTB\n"); |
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return node; |
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} |
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prop = fdt_getprop(nvtboot_blob, node, "nvidia,ether-mac", &len); |
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if (!prop) { |
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printf("Can't find nvidia,ether-mac property in nvtboot DTB\n"); |
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return -ENOENT; |
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} |
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ret = setenv("ethaddr", (void *)prop); |
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if (ret) { |
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printf("Failed to set ethaddr from nvtboot DTB: %d\n", ret); |
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return ret; |
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} |
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return 0; |
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} |
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int tegra_soc_board_init_late(void) |
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{ |
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/* Ignore errors here; not all cases care about Ethernet addresses */ |
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set_ethaddr_from_nvtboot(); |
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return 0; |
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} |
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@ -0,0 +1,166 @@ |
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* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC) |
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This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service) |
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IP block. The IP supports multiple options for bus type, clocking and reset |
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structure, and feature list. Consequently, a number of properties and list |
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entries in properties are marked as optional, or only required in specific HW |
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configurations. |
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Required properties: |
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- compatible: One of: |
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- "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10" |
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Represents the IP core when integrated into the Axis ARTPEC-6 SoC. |
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- "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10" |
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Represents the IP core when integrated into the NVIDIA Tegra186 SoC. |
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- "snps,dwc-qos-ethernet-4.10" |
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This combination is deprecated. It should be treated as equivalent to |
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"axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be |
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compatible with earlier revisions of this binding. |
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- reg: Address and length of the register set for the device |
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- clocks: Phandle and clock specifiers for each entry in clock-names, in the |
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same order. See ../clock/clock-bindings.txt. |
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- clock-names: May contain any/all of the following depending on the IP |
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configuration, in any order: |
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- "tx" |
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The EQOS transmit path clock. The HW signal name is clk_tx_i. |
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In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX |
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path. In other configurations, other clocks (such as tx_125, rmii) may |
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drive the PHY TX path. |
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- "rx" |
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The EQOS receive path clock. The HW signal name is clk_rx_i. |
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In some configurations (e.g. GMII/RGMII), this clock is derived from the |
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PHY's RX clock output. In other configurations, other clocks (such as |
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rx_125, rmii) may drive the EQOS RX path. |
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In cases where the PHY clock is directly fed into the EQOS receive path |
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without intervening logic, the DT need not represent this clock, since it |
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is assumed to be fully under the control of the PHY device/driver. In |
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cases where SoC integration adds additional logic to this path, such as a |
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SW-controlled clock gate, this clock should be represented in DT. |
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- "slave_bus" |
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The CPU/slave-bus (CSR) interface clock. This applies to any bus type; |
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APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other |
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buses). |
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- "master_bus" |
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The master bus interface clock. Only required in configurations that use a |
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separate clock for the master and slave bus interfaces. The HW signal name |
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is hclk_i (AHB) or aclk_i (AXI). |
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- "ptp_ref" |
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The PTP reference clock. The HW signal name is clk_ptp_ref_i. |
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- "phy_ref_clk" |
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This clock is deprecated and should not be used by new compatible values. |
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It is equivalent to "tx". |
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- "apb_pclk" |
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This clock is deprecated and should not be used by new compatible values. |
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It is equivalent to "slave_bus". |
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Note: Support for additional IP configurations may require adding the |
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following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i, |
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clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i. |
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Configurations exist where multiple similar clocks are used at once, e.g. all |
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of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to |
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extend the binding with a separate clock-names entry for each of those RX |
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clocks, rather than repurposing the existing "rx" clock-names entry as a |
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generic/logical clock in a similar fashion to "master_bus" and "slave_bus". |
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This will allow easy support for configurations that support multiple PHY |
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interfaces using a mux, and hence need to have explicit control over |
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specific RX clocks. |
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The following compatible values require the following set of clocks: |
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- "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": |
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- "slave_bus" |
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- "master_bus" |
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- "rx" |
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- "tx" |
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- "ptp_ref" |
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- "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": |
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- "slave_bus" |
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- "master_bus" |
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- "tx" |
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- "ptp_ref" |
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- "snps,dwc-qos-ethernet-4.10" (deprecated): |
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- "phy_ref_clk" |
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- "apb_clk" |
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- interrupt-parent: Should be the phandle for the interrupt controller |
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that services interrupts for this device |
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- interrupts: Should contain the core's combined interrupt signal |
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- phy-mode: See ethernet.txt file in the same directory |
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- resets: Phandle and reset specifiers for each entry in reset-names, in the |
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same order. See ../reset/reset.txt. |
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- reset-names: May contain any/all of the following depending on the IP |
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configuration, in any order: |
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- "eqos". The reset to the entire module. The HW signal name is hreset_n |
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(AHB) or aresetn_i (AXI). |
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The following compatible values require the following set of resets: |
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(the reset properties may be omitted if empty) |
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- "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": |
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- "eqos". |
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- "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": |
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- None. |
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- "snps,dwc-qos-ethernet-4.10" (deprecated): |
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- None. |
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Optional properties: |
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- dma-coherent: Present if dma operations are coherent |
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- mac-address: See ethernet.txt in the same directory |
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- local-mac-address: See ethernet.txt in the same directory |
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- phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY. |
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See ../gpio/gpio.txt. |
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- snps,en-lpi: If present it enables use of the AXI low-power interface |
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- snps,write-requests: Number of write requests that the AXI port can issue. |
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It depends on the SoC configuration. |
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- snps,read-requests: Number of read requests that the AXI port can issue. |
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It depends on the SoC configuration. |
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- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB |
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representing 4, then 8 etc. |
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- snps,txpbl: DMA Programmable burst length for the TX DMA |
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- snps,rxpbl: DMA Programmable burst length for the RX DMA |
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- snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during |
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TX low-power mode. |
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- phy-handle: See ethernet.txt file in the same directory |
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- mdio device tree subnode: When the GMAC has a phy connected to its local |
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mdio, there must be device tree subnode with the following |
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required properties: |
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- compatible: Must be "snps,dwc-qos-ethernet-mdio". |
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- #address-cells: Must be <1>. |
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- #size-cells: Must be <0>. |
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For each phy on the mdio bus, there must be a node with the following |
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fields: |
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- reg: phy id used to communicate to phy. |
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- device_type: Must be "ethernet-phy". |
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- fixed-mode device tree subnode: see fixed-link.txt in the same directory |
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Examples: |
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ethernet2@40010000 { |
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clock-names = "phy_ref_clk", "apb_pclk"; |
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clocks = <&clkc 17>, <&clkc 15>; |
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compatible = "snps,dwc-qos-ethernet-4.10"; |
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interrupt-parent = <&intc>; |
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interrupts = <0x0 0x1e 0x4>; |
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reg = <0x40010000 0x4000>; |
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phy-handle = <&phy2>; |
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phy-mode = "gmii"; |
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phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>; |
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snps,en-tx-lpi-clockgating; |
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snps,en-lpi; |
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snps,write-requests = <2>; |
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snps,read-requests = <16>; |
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snps,burst-map = <0x7>; |
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snps,txpbl = <8>; |
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snps,rxpbl = <2>; |
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dma-coherent; |
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mdio { |
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#address-cells = <0x1>; |
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#size-cells = <0x0>; |
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phy2: phy@1 { |
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compatible = "ethernet-phy-ieee802.3-c22"; |
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device_type = "ethernet-phy"; |
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reg = <0x1>; |
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}; |
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}; |
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}; |
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