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@ -89,7 +89,7 @@ |
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| CFG_CMD_PING \
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| CFG_CMD_DHCP \
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| CFG_CMD_IMMAP \
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| CFG_CMD_I2C \
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| CFG_CMD_I2C \
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| CFG_CMD_MII) |
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/* & ~( CFG_CMD_NET)) */ |
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@ -217,9 +217,9 @@ |
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#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
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#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
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#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
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else immr->im_cpm.cp_pbdat &= ~PB_SDA |
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else immr->im_cpm.cp_pbdat &= ~PB_SDA |
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#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
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else immr->im_cpm.cp_pbdat &= ~PB_SCL |
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else immr->im_cpm.cp_pbdat &= ~PB_SCL |
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#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
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#endif /* CONFIG_SOFT_I2C */ |
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#endif |
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@ -386,9 +386,11 @@ |
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#define HPI_HPID_NOINC_2 HPI_REG(0x3000000 + 2) |
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#endif /* CONFIG_SPC1920_HPI_TEST */ |
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/* PLD CS5 */ |
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/*
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* PLD CS5
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*/ |
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#define CFG_SPC1920_PLD_BASE 0x80000000 |
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#define CFG_PRELIM_OR5_AM 0xffff8000 |
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#define CFG_PRELIM_OR5_AM 0xfff00000 |
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#define CFG_OR5_PRELIM (CFG_PRELIM_OR5_AM | \ |
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OR_CSNT_SAM | \
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@ -399,10 +401,6 @@ |
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#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); |
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/* #define CFG_PLD_BASE 0x30000000 */ |
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/* #define CFG_OR5_PRELIM 0xffff1110 */ |
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/* #define CFG_BR5_PRELIM 0x30000401 */ |
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/*
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* Internal Definitions |
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* |
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