Bring in required device tree files for ls2085a from Linux. These are initially unchanged and have a number of pieces not needed by U-Boot. Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>master
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/* |
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* Freescale ls2085a SOC common device tree source |
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* |
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* Copyright 2013-2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/ { |
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compatible = "fsl,ls2085a"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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/* |
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* We expect the enable-method for cpu's to be "psci", but this |
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* is dependent on the SoC FW, which will fill this in. |
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* |
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* Currently supported enable-method is psci v0.2 |
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*/ |
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/* We have 4 clusters having 2 Cortex-A57 cores each */ |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x0 0x0>; |
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}; |
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cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x0 0x1>; |
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}; |
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cpu@100 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x0 0x100>; |
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}; |
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cpu@101 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x0 0x101>; |
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}; |
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cpu@200 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x0 0x200>; |
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}; |
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cpu@201 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x0 0x201>; |
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}; |
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cpu@300 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x0 0x300>; |
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}; |
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cpu@301 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x0 0x301>; |
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}; |
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}; |
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memory@80000000 { |
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device_type = "memory"; |
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reg = <0x00000000 0x80000000 0 0x80000000>; |
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/* DRAM space - 1, size : 2 GB DRAM */ |
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}; |
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gic: interrupt-controller@6000000 { |
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compatible = "arm,gic-v3"; |
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reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ |
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<0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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interrupts = <1 9 0x4>; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ |
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<1 14 0x8>, /* Physical Non-Secure PPI, active-low */ |
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<1 11 0x8>, /* Virtual PPI, active-low */ |
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<1 10 0x8>; /* Hypervisor PPI, active-low */ |
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}; |
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serial0: serial@21c0500 { |
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device_type = "serial"; |
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compatible = "fsl,ns16550", "ns16550a"; |
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reg = <0x0 0x21c0500 0x0 0x100>; |
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clock-frequency = <0>; /* Updated by bootloader */ |
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interrupts = <0 32 0x1>; /* edge triggered */ |
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}; |
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serial1: serial@21c0600 { |
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device_type = "serial"; |
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compatible = "fsl,ns16550", "ns16550a"; |
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reg = <0x0 0x21c0600 0x0 0x100>; |
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clock-frequency = <0>; /* Updated by bootloader */ |
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interrupts = <0 32 0x1>; /* edge triggered */ |
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}; |
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fsl_mc: fsl-mc@80c000000 { |
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compatible = "fsl,qoriq-mc"; |
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ |
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<0x00000000 0x08340000 0 0x40000>; /* MC control reg */ |
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}; |
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}; |
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