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@ -96,7 +96,7 @@ long int initdram (int board_type) |
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{ |
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volatile immap_t *immap = (immap_t *)CFG_IMMR; |
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volatile memctl8xx_t *memctl = &immap->im_memctl; |
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long int size10 ; |
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long int size9 ; |
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upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); |
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@ -109,7 +109,7 @@ long int initdram (int board_type) |
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memctl->memc_or1 = CFG_OR1_PRELIM; |
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memctl->memc_br1 = CFG_BR1_PRELIM; |
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memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ |
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memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ |
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udelay(200); |
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@ -122,13 +122,20 @@ long int initdram (int board_type) |
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udelay (1000); |
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/* Check Bank 0 Memory Size
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* try 10 column mode |
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/* Check Bank 0 Memory Size,
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* 9 column mode |
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*/ |
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size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ; |
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size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ; |
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return (size10); |
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/*
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* Final mapping: |
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*/ |
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memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; |
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udelay (1000); |
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return (size9); |
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} |
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/* ------------------------------------------------------------------------- */ |
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