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@ -432,12 +432,12 @@ static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) |
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int ret; |
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/* AIF(1/0) register adress offset calculated */ |
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if (aif) |
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if (aif-1) |
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offset = 4; |
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else |
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offset = 0; |
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switch (wm8994->sysclk[aif]) { |
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switch (wm8994->sysclk[aif-1]) { |
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case WM8994_SYSCLK_MCLK1: |
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reg1 |= SEL_MCLK1; |
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rate = wm8994->mclk[0]; |
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@ -460,7 +460,7 @@ static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) |
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default: |
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debug("%s: Invalid input clock selection [%d]\n", |
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__func__, wm8994->sysclk[aif]); |
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__func__, wm8994->sysclk[aif-1]); |
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return -1; |
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} |
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@ -470,13 +470,18 @@ static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) |
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reg1 |= WM8994_AIF1CLK_DIV; |
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} |
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wm8994->aifclk[aif] = rate; |
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wm8994->aifclk[aif-1] = rate; |
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ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset, |
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WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, |
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reg1); |
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ret |= wm8994_update_bits(WM8994_CLOCKING_1, |
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if (aif == WM8994_AIF1) |
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ret |= wm8994_update_bits(WM8994_CLOCKING_1, |
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WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK, |
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WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA); |
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else if (aif == WM8994_AIF2) |
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ret |= wm8994_update_bits(WM8994_CLOCKING_1, |
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WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK | |
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WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC | |
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WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA); |
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@ -536,7 +541,7 @@ static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id, |
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break; |
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if (i == ARRAY_SIZE(opclk_divs)) { |
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debug("%s frequency divisor not found\n", |
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__func__); |
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__func__); |
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return -1; |
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} |
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ret = wm8994_update_bits(WM8994_CLOCKING_2, |
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@ -554,7 +559,7 @@ static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id, |
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return -1; |
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} |
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ret |= configure_aif_clock(wm8994, aif_id - 1); |
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ret |= configure_aif_clock(wm8994, aif_id); |
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if (ret < 0) { |
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debug("%s: codec register access error\n", __func__); |
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@ -608,13 +613,46 @@ static int wm8994_init_volume_aif2_dac1(void) |
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} |
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/*
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* Initializes Volume for AIF1 to HP path |
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* |
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* @returns -1 for error and 0 Success. |
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* |
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*/ |
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static int wm8994_init_volume_aif1_dac1(void) |
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{ |
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int ret = 0; |
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/* Unmute AIF1DAC */ |
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ret |= wm8994_i2c_write(WM8994_AIF1_DAC_FILTERS_1, 0x0000); |
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ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME, |
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WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK | |
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WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0); |
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ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME, |
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WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK | |
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WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0); |
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/* Head Phone Volume */ |
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ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D); |
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ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D); |
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if (ret < 0) { |
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debug("%s: codec register access error\n", __func__); |
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return -1; |
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} |
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return 0; |
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} |
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/*
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* Intialise wm8994 codec device |
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* |
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* @param wm8994 wm8994 information |
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* |
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* @returns -1 for error and 0 Success. |
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*/ |
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static int wm8994_device_init(struct wm8994_priv *wm8994) |
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static int wm8994_device_init(struct wm8994_priv *wm8994, |
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enum en_audio_interface aif_id) |
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{ |
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const char *devname; |
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unsigned short reg_data; |
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@ -661,13 +699,30 @@ static int wm8994_device_init(struct wm8994_priv *wm8994) |
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ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, |
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WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA); |
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/* Power enable for AIF2 and DAC1 */ |
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ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5, |
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WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK | |
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WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK, |
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WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA | |
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WM8994_DAC1R_ENA); |
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if (aif_id == WM8994_AIF1) { |
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ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_2, |
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WM8994_TSHUT_ENA | WM8994_MIXINL_ENA | |
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WM8994_MIXINR_ENA | WM8994_IN2L_ENA | |
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WM8994_IN2R_ENA); |
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ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_4, |
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WM8994_ADCL_ENA | WM8994_ADCR_ENA | |
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WM8994_AIF1ADC1R_ENA | |
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WM8994_AIF1ADC1L_ENA); |
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/* Power enable for AIF1 and DAC1 */ |
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ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_5, |
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WM8994_AIF1DACL_ENA | |
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WM8994_AIF1DACR_ENA | |
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WM8994_DAC1L_ENA | WM8994_DAC1R_ENA); |
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} else if (aif_id == WM8994_AIF2) { |
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/* Power enable for AIF2 and DAC1 */ |
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ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5, |
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WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK | |
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WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK, |
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WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | |
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WM8994_DAC1L_ENA | WM8994_DAC1R_ENA); |
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} |
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/* Head Phone Initialisation */ |
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ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1, |
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WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK, |
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@ -695,35 +750,49 @@ static int wm8994_device_init(struct wm8994_priv *wm8994) |
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ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2, |
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WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R); |
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/* Routing AIF2 to DAC1 */ |
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ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING, |
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WM8994_AIF2DACL_TO_DAC1L_MASK, |
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WM8994_AIF2DACL_TO_DAC1L); |
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ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING, |
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WM8994_AIF2DACR_TO_DAC1R_MASK, |
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WM8994_AIF2DACR_TO_DAC1R); |
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/* GPIO Settings for AIF2 */ |
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/* B CLK */ |
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ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK | |
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WM8994_GPIO_FUNCTION_MASK , |
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WM8994_GPIO_DIR_OUTPUT | |
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WM8994_GPIO_FUNCTION_I2S_CLK); |
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/* LR CLK */ |
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ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK | |
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WM8994_GPIO_FUNCTION_MASK, |
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WM8994_GPIO_DIR_OUTPUT | |
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WM8994_GPIO_FUNCTION_I2S_CLK); |
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/* DATA */ |
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ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK | |
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WM8994_GPIO_FUNCTION_MASK, |
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WM8994_GPIO_DIR_OUTPUT | |
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WM8994_GPIO_FUNCTION_I2S_CLK); |
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ret |= wm8994_init_volume_aif2_dac1(); |
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if (aif_id == WM8994_AIF1) { |
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/* Routing AIF1 to DAC1 */ |
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ret |= wm8994_i2c_write(WM8994_DAC1_LEFT_MIXER_ROUTING, |
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WM8994_AIF1DAC1L_TO_DAC1L); |
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ret |= wm8994_i2c_write(WM8994_DAC1_RIGHT_MIXER_ROUTING, |
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WM8994_AIF1DAC1R_TO_DAC1R); |
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/* GPIO Settings for AIF1 */ |
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ret |= wm8994_i2c_write(WM8994_GPIO_1, WM8994_GPIO_DIR_OUTPUT |
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| WM8994_GPIO_FUNCTION_I2S_CLK |
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| WM8994_GPIO_INPUT_DEBOUNCE); |
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ret |= wm8994_init_volume_aif1_dac1(); |
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} else if (aif_id == WM8994_AIF2) { |
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/* Routing AIF2 to DAC1 */ |
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ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING, |
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WM8994_AIF2DACL_TO_DAC1L_MASK, |
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WM8994_AIF2DACL_TO_DAC1L); |
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ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING, |
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WM8994_AIF2DACR_TO_DAC1R_MASK, |
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WM8994_AIF2DACR_TO_DAC1R); |
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/* GPIO Settings for AIF2 */ |
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/* B CLK */ |
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ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK | |
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WM8994_GPIO_FUNCTION_MASK , |
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WM8994_GPIO_DIR_OUTPUT); |
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/* LR CLK */ |
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ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK | |
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WM8994_GPIO_FUNCTION_MASK, |
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WM8994_GPIO_DIR_OUTPUT); |
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/* DATA */ |
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ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK | |
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WM8994_GPIO_FUNCTION_MASK, |
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WM8994_GPIO_DIR_OUTPUT); |
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ret |= wm8994_init_volume_aif2_dac1(); |
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} |
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if (ret < 0) |
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goto err; |
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@ -795,7 +864,7 @@ static int get_codec_values(struct sound_codec_info *pcodec_info, |
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return 0; |
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} |
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/*wm8994 Device Initialisation */ |
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/* WM8994 Device Initialisation */ |
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int wm8994_init(const void *blob, enum en_audio_interface aif_id, |
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int sampling_rate, int mclk_freq, |
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int bits_per_sample, unsigned int channels) |
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@ -813,15 +882,15 @@ int wm8994_init(const void *blob, enum en_audio_interface aif_id, |
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g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr; |
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wm8994_i2c_init(pcodec_info->i2c_bus); |
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if (pcodec_info->codec_type == CODEC_WM_8994) |
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if (pcodec_info->codec_type == CODEC_WM_8994) { |
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g_wm8994_info.type = WM8994; |
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else { |
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} else { |
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debug("%s: Codec id [%d] not defined\n", __func__, |
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pcodec_info->codec_type); |
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pcodec_info->codec_type); |
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return -1; |
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} |
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ret = wm8994_device_init(&g_wm8994_info); |
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ret = wm8994_device_init(&g_wm8994_info, aif_id); |
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if (ret < 0) { |
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debug("%s: wm8994 codec chip init failed\n", __func__); |
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return ret; |
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