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@ -10,11 +10,11 @@ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <net.h> |
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#include <netdev.h> |
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#include <config.h> |
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#include <fdtdec.h> |
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#include <libfdt.h> |
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#include <console.h> |
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#include <malloc.h> |
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#include <asm/io.h> |
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#include <phy.h> |
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@ -25,6 +25,8 @@ |
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#include <asm/arch/sys_proto.h> |
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#include <asm-generic/errno.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#if !defined(CONFIG_PHYLIB) |
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# error XILINX_GEM_ETHERNET requires PHYLIB |
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#endif |
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@ -167,14 +169,14 @@ struct zynq_gem_priv { |
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int phyaddr; |
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u32 emio; |
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int init; |
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struct zynq_gem_regs *iobase; |
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phy_interface_t interface; |
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struct phy_device *phydev; |
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struct mii_dev *bus; |
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}; |
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static inline int mdio_wait(struct eth_device *dev) |
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static inline int mdio_wait(struct zynq_gem_regs *regs) |
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{ |
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; |
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u32 timeout = 20000; |
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/* Wait till MDIO interface is ready to accept a new transaction. */ |
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@ -192,13 +194,13 @@ static inline int mdio_wait(struct eth_device *dev) |
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return 0; |
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} |
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static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, |
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u32 op, u16 *data) |
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static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, |
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u32 op, u16 *data) |
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{ |
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u32 mgtcr; |
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; |
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struct zynq_gem_regs *regs = priv->iobase; |
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if (mdio_wait(dev)) |
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if (mdio_wait(regs)) |
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return 1; |
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/* Construct mgtcr mask for the operation */ |
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@ -209,7 +211,7 @@ static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, |
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/* Write mgtcr and wait for completion */ |
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writel(mgtcr, ®s->phymntnc); |
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if (mdio_wait(dev)) |
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if (mdio_wait(regs)) |
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return 1; |
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if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) |
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@ -218,12 +220,13 @@ static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, |
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return 0; |
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} |
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static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) |
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static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, |
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u32 regnum, u16 *val) |
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{ |
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u32 ret; |
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ret = phy_setup_op(dev, phy_addr, regnum, |
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ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); |
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ret = phy_setup_op(priv, phy_addr, regnum, |
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ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); |
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if (!ret) |
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debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, |
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@ -232,29 +235,30 @@ static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) |
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return ret; |
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} |
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static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) |
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static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, |
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u32 regnum, u16 data) |
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{ |
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debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, |
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regnum, data); |
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return phy_setup_op(dev, phy_addr, regnum, |
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ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); |
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return phy_setup_op(priv, phy_addr, regnum, |
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ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); |
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} |
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static void phy_detection(struct eth_device *dev) |
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static int phy_detection(struct udevice *dev) |
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{ |
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int i; |
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u16 phyreg; |
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struct zynq_gem_priv *priv = dev->priv; |
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if (priv->phyaddr != -1) { |
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phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg); |
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phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); |
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if ((phyreg != 0xFFFF) && |
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { |
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/* Found a valid PHY address */ |
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debug("Default phy address %d is valid\n", |
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priv->phyaddr); |
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return; |
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return 0; |
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} else { |
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debug("PHY address is not setup correctly %d\n", |
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priv->phyaddr); |
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@ -266,33 +270,36 @@ static void phy_detection(struct eth_device *dev) |
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if (priv->phyaddr == -1) { |
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/* detect the PHY address */ |
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for (i = 31; i >= 0; i--) { |
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phyread(dev, i, PHY_DETECT_REG, &phyreg); |
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phyread(priv, i, PHY_DETECT_REG, &phyreg); |
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if ((phyreg != 0xFFFF) && |
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { |
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/* Found a valid PHY address */ |
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priv->phyaddr = i; |
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debug("Found valid phy address, %d\n", i); |
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return; |
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return 0; |
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} |
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} |
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} |
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printf("PHY is not detected\n"); |
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return -1; |
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} |
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static int zynq_gem_setup_mac(struct eth_device *dev) |
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static int zynq_gem_setup_mac(struct udevice *dev) |
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{ |
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u32 i, macaddrlow, macaddrhigh; |
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; |
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struct eth_pdata *pdata = dev_get_platdata(dev); |
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struct zynq_gem_priv *priv = dev_get_priv(dev); |
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struct zynq_gem_regs *regs = priv->iobase; |
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/* Set the MAC bits [31:0] in BOT */ |
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macaddrlow = dev->enetaddr[0]; |
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macaddrlow |= dev->enetaddr[1] << 8; |
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macaddrlow |= dev->enetaddr[2] << 16; |
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macaddrlow |= dev->enetaddr[3] << 24; |
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macaddrlow = pdata->enetaddr[0]; |
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macaddrlow |= pdata->enetaddr[1] << 8; |
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macaddrlow |= pdata->enetaddr[2] << 16; |
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macaddrlow |= pdata->enetaddr[3] << 24; |
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/* Set MAC bits [47:32] in TOP */ |
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macaddrhigh = dev->enetaddr[4]; |
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macaddrhigh |= dev->enetaddr[5] << 8; |
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macaddrhigh = pdata->enetaddr[4]; |
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macaddrhigh |= pdata->enetaddr[5] << 8; |
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for (i = 0; i < 4; i++) { |
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writel(0, ®s->laddr[i][LADDR_LOW]); |
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@ -307,15 +314,11 @@ static int zynq_gem_setup_mac(struct eth_device *dev) |
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return 0; |
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} |
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static int zynq_gem_init(struct eth_device *dev, bd_t * bis) |
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static int zynq_phy_init(struct udevice *dev) |
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{ |
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u32 i; |
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unsigned long clk_rate = 0; |
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struct phy_device *phydev; |
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; |
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struct zynq_gem_priv *priv = dev->priv; |
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struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; |
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struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; |
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int ret; |
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struct zynq_gem_priv *priv = dev_get_priv(dev); |
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struct zynq_gem_regs *regs = priv->iobase; |
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const u32 supported = SUPPORTED_10baseT_Half | |
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SUPPORTED_10baseT_Full | |
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SUPPORTED_100baseT_Half | |
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@ -323,6 +326,37 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) |
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SUPPORTED_1000baseT_Half | |
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SUPPORTED_1000baseT_Full; |
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/* Enable only MDIO bus */ |
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writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); |
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ret = phy_detection(dev); |
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if (ret) { |
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printf("GEM PHY init failed\n"); |
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return ret; |
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} |
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priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, |
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priv->interface); |
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if (!priv->phydev) |
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return -ENODEV; |
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priv->phydev->supported = supported | ADVERTISED_Pause | |
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ADVERTISED_Asym_Pause; |
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priv->phydev->advertising = priv->phydev->supported; |
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phy_config(priv->phydev); |
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return 0; |
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} |
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static int zynq_gem_init(struct udevice *dev) |
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{ |
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u32 i; |
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unsigned long clk_rate = 0; |
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struct zynq_gem_priv *priv = dev_get_priv(dev); |
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struct zynq_gem_regs *regs = priv->iobase; |
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struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; |
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struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; |
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if (!priv->init) { |
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/* Disable all interrupts */ |
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writel(0xFFFFFFFF, ®s->idr); |
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@ -384,25 +418,14 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) |
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priv->init++; |
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} |
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phy_detection(dev); |
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/* interface - look at tsec */ |
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phydev = phy_connect(priv->bus, priv->phyaddr, dev, |
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priv->interface); |
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phydev->supported = supported | ADVERTISED_Pause | |
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ADVERTISED_Asym_Pause; |
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phydev->advertising = phydev->supported; |
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priv->phydev = phydev; |
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phy_config(phydev); |
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phy_startup(phydev); |
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phy_startup(priv->phydev); |
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if (!phydev->link) { |
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printf("%s: No link.\n", phydev->dev->name); |
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if (!priv->phydev->link) { |
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printf("%s: No link.\n", priv->phydev->dev->name); |
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return -1; |
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} |
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switch (phydev->speed) { |
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switch (priv->phydev->speed) { |
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case SPEED_1000: |
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writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, |
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®s->nwcfg); |
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@ -420,7 +443,7 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) |
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/* Change the rclk and clk only not using EMIO interface */ |
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if (!priv->emio) |
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zynq_slcr_gem_clk_setup(dev->iobase != |
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zynq_slcr_gem_clk_setup((ulong)priv->iobase != |
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ZYNQ_GEM_BASEADDR0, clk_rate); |
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setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | |
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@ -447,6 +470,11 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask, |
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if (get_timer(start) > timeout) |
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break; |
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if (ctrlc()) { |
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puts("Abort\n"); |
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return -EINTR; |
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} |
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udelay(1); |
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} |
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@ -456,11 +484,11 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask, |
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return -ETIMEDOUT; |
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} |
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static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) |
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static int zynq_gem_send(struct udevice *dev, void *ptr, int len) |
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{ |
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u32 addr, size; |
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struct zynq_gem_priv *priv = dev->priv; |
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; |
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struct zynq_gem_priv *priv = dev_get_priv(dev); |
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struct zynq_gem_regs *regs = priv->iobase; |
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struct emac_bd *current_bd = &priv->tx_bd[1]; |
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/* Setup Tx BD */ |
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@ -501,10 +529,10 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) |
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} |
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/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ |
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static int zynq_gem_recv(struct eth_device *dev) |
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static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) |
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{ |
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int frame_len; |
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struct zynq_gem_priv *priv = dev->priv; |
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struct zynq_gem_priv *priv = dev_get_priv(dev); |
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struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; |
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struct emac_bd *first_bd; |
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@ -544,51 +572,41 @@ static int zynq_gem_recv(struct eth_device *dev) |
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return frame_len; |
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} |
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static void zynq_gem_halt(struct eth_device *dev) |
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static void zynq_gem_halt(struct udevice *dev) |
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{ |
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; |
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struct zynq_gem_priv *priv = dev_get_priv(dev); |
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struct zynq_gem_regs *regs = priv->iobase; |
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clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | |
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ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); |
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} |
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static int zynq_gem_miiphyread(const char *devname, uchar addr, |
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uchar reg, ushort *val) |
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static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, |
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int devad, int reg) |
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{ |
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struct eth_device *dev = eth_get_dev(); |
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struct zynq_gem_priv *priv = bus->priv; |
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int ret; |
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u16 val; |
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ret = phyread(dev, addr, reg, val); |
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debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); |
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return ret; |
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ret = phyread(priv, addr, reg, &val); |
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debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); |
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return val; |
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} |
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static int zynq_gem_miiphy_write(const char *devname, uchar addr, |
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uchar reg, ushort val) |
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static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, |
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int reg, u16 value) |
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{ |
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struct eth_device *dev = eth_get_dev(); |
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struct zynq_gem_priv *priv = bus->priv; |
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debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); |
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return phywrite(dev, addr, reg, val); |
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debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); |
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return phywrite(priv, addr, reg, value); |
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} |
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int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, |
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int phy_addr, u32 emio) |
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static int zynq_gem_probe(struct udevice *dev) |
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{ |
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struct eth_device *dev; |
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struct zynq_gem_priv *priv; |
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void *bd_space; |
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dev = calloc(1, sizeof(*dev)); |
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if (dev == NULL) |
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return -1; |
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dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); |
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if (dev->priv == NULL) { |
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free(dev); |
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return -1; |
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} |
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priv = dev->priv; |
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struct zynq_gem_priv *priv = dev_get_priv(dev); |
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int ret; |
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/* Align rxbuffers to ARCH_DMA_MINALIGN */ |
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priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); |
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@ -603,69 +621,87 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, |
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priv->tx_bd = (struct emac_bd *)bd_space; |
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priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); |
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priv->phyaddr = phy_addr; |
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priv->emio = emio; |
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#ifndef CONFIG_ZYNQ_GEM_INTERFACE |
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priv->interface = PHY_INTERFACE_MODE_MII; |
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#else |
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priv->interface = CONFIG_ZYNQ_GEM_INTERFACE; |
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#endif |
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priv->bus = mdio_alloc(); |
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priv->bus->read = zynq_gem_miiphy_read; |
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priv->bus->write = zynq_gem_miiphy_write; |
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priv->bus->priv = priv; |
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strcpy(priv->bus->name, "gem"); |
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sprintf(dev->name, "Gem.%lx", base_addr); |
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ret = mdio_register(priv->bus); |
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if (ret) |
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return ret; |
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dev->iobase = base_addr; |
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zynq_phy_init(dev); |
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dev->init = zynq_gem_init; |
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dev->halt = zynq_gem_halt; |
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dev->send = zynq_gem_send; |
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dev->recv = zynq_gem_recv; |
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dev->write_hwaddr = zynq_gem_setup_mac; |
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return 0; |
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} |
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|
eth_register(dev); |
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static int zynq_gem_remove(struct udevice *dev) |
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|
{ |
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struct zynq_gem_priv *priv = dev_get_priv(dev); |
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miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); |
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priv->bus = miiphy_get_dev_by_name(dev->name); |
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|
free(priv->phydev); |
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|
mdio_unregister(priv->bus); |
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|
mdio_free(priv->bus); |
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return 1; |
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|
return 0; |
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|
} |
|
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|
#if CONFIG_IS_ENABLED(OF_CONTROL) |
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|
int zynq_gem_of_init(const void *blob) |
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|
static const struct eth_ops zynq_gem_ops = { |
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|
.start = zynq_gem_init, |
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.send = zynq_gem_send, |
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|
.recv = zynq_gem_recv, |
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|
.stop = zynq_gem_halt, |
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|
.write_hwaddr = zynq_gem_setup_mac, |
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|
}; |
|
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|
|
static int zynq_gem_ofdata_to_platdata(struct udevice *dev) |
|
|
|
|
{ |
|
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|
|
struct eth_pdata *pdata = dev_get_platdata(dev); |
|
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|
|
struct zynq_gem_priv *priv = dev_get_priv(dev); |
|
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|
|
int offset = 0; |
|
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|
|
u32 ret = 0; |
|
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|
|
u32 reg, phy_reg; |
|
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|
|
|
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|
|
debug("ZYNQ GEM: Initialization\n"); |
|
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|
|
do { |
|
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|
|
offset = fdt_node_offset_by_compatible(blob, offset, |
|
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|
|
"xlnx,ps7-ethernet-1.00.a"); |
|
|
|
|
if (offset != -1) { |
|
|
|
|
reg = fdtdec_get_addr(blob, offset, "reg"); |
|
|
|
|
if (reg != FDT_ADDR_T_NONE) { |
|
|
|
|
offset = fdtdec_lookup_phandle(blob, offset, |
|
|
|
|
"phy-handle"); |
|
|
|
|
if (offset != -1) |
|
|
|
|
phy_reg = fdtdec_get_addr(blob, offset, |
|
|
|
|
"reg"); |
|
|
|
|
else |
|
|
|
|
phy_reg = 0; |
|
|
|
|
|
|
|
|
|
debug("ZYNQ GEM: addr %x, phyaddr %x\n", |
|
|
|
|
reg, phy_reg); |
|
|
|
|
|
|
|
|
|
ret |= zynq_gem_initialize(NULL, reg, |
|
|
|
|
phy_reg, 0); |
|
|
|
|
|
|
|
|
|
} else { |
|
|
|
|
debug("ZYNQ GEM: Can't get base address\n"); |
|
|
|
|
return -1; |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
} while (offset != -1); |
|
|
|
|
const char *phy_mode; |
|
|
|
|
|
|
|
|
|
pdata->iobase = (phys_addr_t)dev_get_addr(dev); |
|
|
|
|
priv->iobase = (struct zynq_gem_regs *)pdata->iobase; |
|
|
|
|
/* Hardcode for now */ |
|
|
|
|
priv->emio = 0; |
|
|
|
|
|
|
|
|
|
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, |
|
|
|
|
"phy-handle"); |
|
|
|
|
if (offset > 0) |
|
|
|
|
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0); |
|
|
|
|
|
|
|
|
|
phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); |
|
|
|
|
if (phy_mode) |
|
|
|
|
pdata->phy_interface = phy_get_interface_by_name(phy_mode); |
|
|
|
|
if (pdata->phy_interface == -1) { |
|
|
|
|
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); |
|
|
|
|
return -EINVAL; |
|
|
|
|
} |
|
|
|
|
priv->interface = pdata->phy_interface; |
|
|
|
|
|
|
|
|
|
return ret; |
|
|
|
|
printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, |
|
|
|
|
priv->phyaddr, phy_string_for_interface(priv->interface)); |
|
|
|
|
|
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
static const struct udevice_id zynq_gem_ids[] = { |
|
|
|
|
{ .compatible = "cdns,zynqmp-gem" }, |
|
|
|
|
{ .compatible = "cdns,zynq-gem" }, |
|
|
|
|
{ .compatible = "cdns,gem" }, |
|
|
|
|
{ } |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(zynq_gem) = { |
|
|
|
|
.name = "zynq_gem", |
|
|
|
|
.id = UCLASS_ETH, |
|
|
|
|
.of_match = zynq_gem_ids, |
|
|
|
|
.ofdata_to_platdata = zynq_gem_ofdata_to_platdata, |
|
|
|
|
.probe = zynq_gem_probe, |
|
|
|
|
.remove = zynq_gem_remove, |
|
|
|
|
.ops = &zynq_gem_ops, |
|
|
|
|
.priv_auto_alloc_size = sizeof(struct zynq_gem_priv), |
|
|
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata), |
|
|
|
|
}; |
|
|
|
|
|
Tom Rini
9 years ago