Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Fix warnings about vtp things in emif4.c, adapt AM43XX] Signed-off-by: Tom Rini <trini@ti.com>master
TENART Antoine
11 years ago
committed by
Tom Rini
parent
9ed6e41239
commit
dcf846d5da
@ -0,0 +1,445 @@ |
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/*
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* clock_ti816x.c |
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* |
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* Clocks for TI816X based boards |
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* |
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* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> |
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* Antoine Tenart, <atenart@adeneo-embedded.com> |
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* |
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* Based on TI-PSP-04.00.02.14 : |
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* |
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* Copyright (C) 2009, Texas Instruments, Incorporated |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#include <common.h> |
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#include <asm/arch/ddr_defs.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/io.h> |
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#include <asm/emif.h> |
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#define CM_PLL_BASE (CTRL_BASE + 0x0400) |
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/* Main PLL */ |
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#define MAIN_N 64 |
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#define MAIN_P 0x1 |
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#define MAIN_INTFREQ1 0x8 |
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#define MAIN_FRACFREQ1 0x800000 |
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#define MAIN_MDIV1 0x2 |
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#define MAIN_INTFREQ2 0xE |
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#define MAIN_FRACFREQ2 0x0 |
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#define MAIN_MDIV2 0x1 |
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#define MAIN_INTFREQ3 0x8 |
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#define MAIN_FRACFREQ3 0xAAAAB0 |
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#define MAIN_MDIV3 0x3 |
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#define MAIN_INTFREQ4 0x9 |
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#define MAIN_FRACFREQ4 0x55554F |
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#define MAIN_MDIV4 0x3 |
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#define MAIN_INTFREQ5 0x9 |
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#define MAIN_FRACFREQ5 0x374BC6 |
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#define MAIN_MDIV5 0xC |
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#define MAIN_MDIV6 0x48 |
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#define MAIN_MDIV7 0x4 |
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/* DDR PLL */ |
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#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */ |
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#define DDR_N 59 |
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#define DDR_P 0x1 |
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#define DDR_MDIV1 0x4 |
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#define DDR_INTFREQ2 0x8 |
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#define DDR_FRACFREQ2 0xD99999 |
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#define DDR_MDIV2 0x1E |
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#define DDR_INTFREQ3 0x8 |
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#define DDR_FRACFREQ3 0x0 |
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#define DDR_MDIV3 0x4 |
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#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ |
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#define DDR_FRACFREQ4 0x0 |
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#define DDR_MDIV4 0x4 |
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#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ |
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#define DDR_FRACFREQ5 0x0 |
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#define DDR_MDIV5 0x4 |
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#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */ |
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#define DDR_N 59 |
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#define DDR_P 0x1 |
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#define DDR_MDIV1 0x3 |
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#define DDR_INTFREQ2 0x8 |
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#define DDR_FRACFREQ2 0xD99999 |
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#define DDR_MDIV2 0x1E |
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#define DDR_INTFREQ3 0x8 |
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#define DDR_FRACFREQ3 0x0 |
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#define DDR_MDIV3 0x4 |
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#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ |
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#define DDR_FRACFREQ4 0x0 |
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#define DDR_MDIV4 0x4 |
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#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ |
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#define DDR_FRACFREQ5 0x0 |
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#define DDR_MDIV5 0x4 |
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#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */ |
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#define DDR_N 50 |
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#define DDR_P 0x1 |
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#define DDR_MDIV1 0x2 |
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#define DDR_INTFREQ2 0x9 |
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#define DDR_FRACFREQ2 0x0 |
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#define DDR_MDIV2 0x19 |
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#define DDR_INTFREQ3 0x13 |
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#define DDR_FRACFREQ3 0x800000 |
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#define DDR_MDIV3 0x2 |
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#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ |
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#define DDR_FRACFREQ4 0x0 |
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#define DDR_MDIV4 0x4 |
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#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ |
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#define DDR_FRACFREQ5 0x0 |
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#define DDR_MDIV5 0x4 |
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#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */ |
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#define DDR_N 59 |
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#define DDR_P 0x1 |
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#define DDR_MDIV1 0x2 |
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#define DDR_INTFREQ2 0x8 |
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#define DDR_FRACFREQ2 0xD99999 |
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#define DDR_MDIV2 0x1E |
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#define DDR_INTFREQ3 0x8 |
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#define DDR_FRACFREQ3 0x0 |
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#define DDR_MDIV3 0x4 |
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#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ |
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#define DDR_FRACFREQ4 0x0 |
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#define DDR_MDIV4 0x4 |
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#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ |
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#define DDR_FRACFREQ5 0x0 |
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#define DDR_MDIV5 0x4 |
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#endif |
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#define CONTROL_STATUS (CTRL_BASE + 0x40) |
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#define DDR_RCD (CTRL_BASE + 0x070C) |
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#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390) |
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#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) |
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#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628) |
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#define INTCPS_SYSCONFIG 0x48200010 |
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#define CM_SYSCLK10_CLKSEL 0x48180324 |
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struct cm_pll { |
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unsigned int mainpll_ctrl; /* offset 0x400 */ |
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unsigned int mainpll_pwd; |
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unsigned int mainpll_freq1; |
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unsigned int mainpll_div1; |
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unsigned int mainpll_freq2; |
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unsigned int mainpll_div2; |
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unsigned int mainpll_freq3; |
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unsigned int mainpll_div3; |
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unsigned int mainpll_freq4; |
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unsigned int mainpll_div4; |
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unsigned int mainpll_freq5; |
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unsigned int mainpll_div5; |
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unsigned int resv0[1]; |
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unsigned int mainpll_div6; |
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unsigned int resv1[1]; |
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unsigned int mainpll_div7; |
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unsigned int ddrpll_ctrl; /* offset 0x440 */ |
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unsigned int ddrpll_pwd; |
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unsigned int resv2[1]; |
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unsigned int ddrpll_div1; |
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unsigned int ddrpll_freq2; |
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unsigned int ddrpll_div2; |
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unsigned int ddrpll_freq3; |
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unsigned int ddrpll_div3; |
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unsigned int ddrpll_freq4; |
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unsigned int ddrpll_div4; |
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unsigned int ddrpll_freq5; |
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unsigned int ddrpll_div5; |
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unsigned int videopll_ctrl; /* offset 0x470 */ |
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unsigned int videopll_pwd; |
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unsigned int videopll_freq1; |
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unsigned int videopll_div1; |
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unsigned int videopll_freq2; |
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unsigned int videopll_div2; |
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unsigned int videopll_freq3; |
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unsigned int videopll_div3; |
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unsigned int resv3[4]; |
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unsigned int audiopll_ctrl; /* offset 0x4A0 */ |
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unsigned int audiopll_pwd; |
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unsigned int resv4[2]; |
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unsigned int audiopll_freq2; |
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unsigned int audiopll_div2; |
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unsigned int audiopll_freq3; |
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unsigned int audiopll_div3; |
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unsigned int audiopll_freq4; |
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unsigned int audiopll_div4; |
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unsigned int audiopll_freq5; |
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unsigned int audiopll_div5; |
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}; |
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const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; |
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const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; |
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const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE; |
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const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; |
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void enable_dmm_clocks(void) |
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{ |
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writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); |
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writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); |
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writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); |
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/* Wait for clocks to be active */ |
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while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) |
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; |
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/* Wait for emif0 to be fully functional, including OCP */ |
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while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) |
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; |
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/* Wait for emif1 to be fully functional, including OCP */ |
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while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) |
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; |
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writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); |
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/* Wait for dmm to be fully functional, including OCP */ |
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while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) |
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; |
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/* Enable Tiled Access */ |
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writel(0x80000000, DMM_PAT_BASE_ADDR); |
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} |
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/* assume delay is aprox at least 1us */ |
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static void ddr_delay(int d) |
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{ |
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int i; |
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/*
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* read a control register. |
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* this is a bit more delay and cannot be optimized by the compiler |
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* assuming one read takes 200 cycles and A8 is runing 1 GHz |
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* somewhat conservative setting |
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*/ |
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for (i = 0; i < 50*d; i++) |
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readl(CONTROL_STATUS); |
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} |
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static void main_pll_init_ti816x(void) |
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{ |
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u32 main_pll_ctrl = 0; |
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/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ |
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main_pll_ctrl = readl(&cmpll->mainpll_ctrl); |
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main_pll_ctrl &= 0xFFFFFFFB; |
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main_pll_ctrl |= BIT(2); |
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writel(main_pll_ctrl, &cmpll->mainpll_ctrl); |
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/* Enable PLL by setting BIT3 in its ctrl reg */ |
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main_pll_ctrl = readl(&cmpll->mainpll_ctrl); |
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main_pll_ctrl &= 0xFFFFFFF7; |
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main_pll_ctrl |= BIT(3); |
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writel(main_pll_ctrl, &cmpll->mainpll_ctrl); |
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/* Write the values of N,P in the CTRL reg */ |
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main_pll_ctrl = readl(&cmpll->mainpll_ctrl); |
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main_pll_ctrl &= 0xFF; |
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main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8); |
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writel(main_pll_ctrl, &cmpll->mainpll_ctrl); |
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/* Power up clock1-7 */ |
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writel(0x0, &cmpll->mainpll_pwd); |
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/* Program the freq and divider values for clock1-7 */ |
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writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1), |
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&cmpll->mainpll_freq1); |
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writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1); |
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writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2), |
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&cmpll->mainpll_freq2); |
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writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2); |
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writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3), |
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&cmpll->mainpll_freq3); |
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writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3); |
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writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4), |
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&cmpll->mainpll_freq4); |
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writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4); |
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writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5), |
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&cmpll->mainpll_freq5); |
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writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5); |
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writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6); |
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writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7); |
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/* Wait for PLL to lock */ |
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while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) |
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; |
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/* Put the PLL in normal mode, disable bypass */ |
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main_pll_ctrl = readl(&cmpll->mainpll_ctrl); |
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main_pll_ctrl &= 0xFFFFFFFB; |
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writel(main_pll_ctrl, &cmpll->mainpll_ctrl); |
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} |
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static void ddr_pll_bypass_ti816x(void) |
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{ |
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u32 ddr_pll_ctrl = 0; |
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/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ |
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ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); |
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ddr_pll_ctrl &= 0xFFFFFFFB; |
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ddr_pll_ctrl |= BIT(2); |
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writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); |
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} |
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static void ddr_pll_init_ti816x(void) |
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{ |
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u32 ddr_pll_ctrl = 0; |
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/* Enable PLL by setting BIT3 in its ctrl reg */ |
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ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); |
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ddr_pll_ctrl &= 0xFFFFFFF7; |
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ddr_pll_ctrl |= BIT(3); |
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writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); |
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/* Write the values of N,P in the CTRL reg */ |
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ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); |
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ddr_pll_ctrl &= 0xFF; |
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ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8); |
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writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); |
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ddr_delay(10); |
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/* Power up clock1-5 */ |
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writel(0x0, &cmpll->ddrpll_pwd); |
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/* Program the freq and divider values for clock1-3 */ |
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writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); |
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ddr_delay(1); |
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writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); |
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writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2), |
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&cmpll->ddrpll_freq2); |
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writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2); |
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writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); |
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ddr_delay(1); |
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writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); |
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ddr_delay(1); |
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writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), |
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&cmpll->ddrpll_freq3); |
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ddr_delay(1); |
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writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), |
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&cmpll->ddrpll_freq3); |
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ddr_delay(5); |
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/* Wait for PLL to lock */ |
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while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7)) |
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; |
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/* Power up RCD */ |
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writel(BIT(0), DDR_RCD); |
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} |
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static void peripheral_enable(void) |
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{ |
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/* Wake-up the l3_slow clock */ |
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writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); |
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/*
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* Note on Timers: |
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* There are 8 timers(0-7) out of which timer 0 is a secure timer. |
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* Timer 0 mux should not be changed |
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* |
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* To access the timer registers we need the to be |
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* enabled which is what we do in the first step |
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*/ |
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/* Enable timer1 */ |
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writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl); |
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/* Select timer1 clock to be CLKIN (27MHz) */ |
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writel(BIT(1), CM_TIMER1_CLKSEL); |
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/* Wait for timer1 to be ON-ACTIVE */ |
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while (((readl(&cmalwon->l3slowclkstctrl) |
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& (0x80000<<1))>>20) != 1) |
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; |
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/* Wait for timer1 to be enabled */ |
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while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0) |
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; |
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/* Active posted mode */ |
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writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54)); |
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while (readl(DM_TIMER1_BASE + 0x10) & BIT(0)) |
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; |
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/* Start timer1 */ |
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writel(BIT(0), (DM_TIMER1_BASE + 0x38)); |
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/* eFuse */ |
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writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL); |
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while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN) |
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; |
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/* Enable gpio0 */ |
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writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl); |
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while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN) |
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; |
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writel((BIT(8)), &cmalwon->gpio0clkctrl); |
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/* Enable spi */ |
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writel(PRCM_MOD_EN, &cmalwon->spiclkctrl); |
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while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN) |
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; |
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/* Enable i2c0 */ |
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writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl); |
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while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN) |
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; |
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/* Enable ethernet0 */ |
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writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); |
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writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); |
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writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); |
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/* Enable hsmmc */ |
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writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl); |
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while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN) |
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; |
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} |
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void setup_clocks_for_console(void) |
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{ |
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/* Fix ROM code bug - from TI-PSP-04.00.02.14 */ |
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writel(0x0, CM_SYSCLK10_CLKSEL); |
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ddr_pll_bypass_ti816x(); |
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/* Enable uart0-2 */ |
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writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); |
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while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) |
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; |
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writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl); |
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while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN) |
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; |
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writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl); |
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while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN) |
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; |
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while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) |
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; |
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} |
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void prcm_init(void) |
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{ |
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/* Enable the control */ |
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writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); |
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main_pll_init_ti816x(); |
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ddr_pll_init_ti816x(); |
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/*
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* With clk freqs setup to desired values, |
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* enable the required peripherals |
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*/ |
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peripheral_enable(); |
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} |
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@ -0,0 +1,142 @@ |
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/*
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* ti81xx.h |
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* |
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* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> |
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* Antoine Tenart, <atenart@adeneo-embedded.com> |
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* |
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* This file is released under the terms of GPL v2 and any later version. |
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* See the file COPYING in the root directory of the source tree for details. |
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*/ |
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#ifndef _CLOCK_TI81XX_H_ |
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#define _CLOCK_TI81XX_H_ |
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#define PRCM_MOD_EN 0x2 |
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|
||||
#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) |
||||
#define CM_ALWON_BASE (PRCM_BASE + 0x1400) |
||||
|
||||
struct cm_def { |
||||
unsigned int resv0[2]; |
||||
unsigned int l3fastclkstctrl; |
||||
unsigned int resv1[1]; |
||||
unsigned int pciclkstctrl; |
||||
unsigned int resv2[1]; |
||||
unsigned int ducaticlkstctrl; |
||||
unsigned int resv3[1]; |
||||
unsigned int emif0clkctrl; |
||||
unsigned int emif1clkctrl; |
||||
unsigned int dmmclkctrl; |
||||
unsigned int fwclkctrl; |
||||
unsigned int resv4[10]; |
||||
unsigned int usbclkctrl; |
||||
unsigned int resv5[1]; |
||||
unsigned int sataclkctrl; |
||||
unsigned int resv6[4]; |
||||
unsigned int ducaticlkctrl; |
||||
unsigned int pciclkctrl; |
||||
}; |
||||
|
||||
struct cm_alwon { |
||||
unsigned int l3slowclkstctrl; |
||||
unsigned int ethclkstctrl; |
||||
unsigned int l3medclkstctrl; |
||||
unsigned int mmu_clkstctrl; |
||||
unsigned int mmucfg_clkstctrl; |
||||
unsigned int ocmc0clkstctrl; |
||||
#if defined(CONFIG_TI814X) |
||||
unsigned int vcpclkstctrl; |
||||
#elif defined(CONFIG_TI816X) |
||||
unsigned int ocmc1clkstctrl; |
||||
#endif |
||||
unsigned int mpuclkstctrl; |
||||
unsigned int sysclk4clkstctrl; |
||||
unsigned int sysclk5clkstctrl; |
||||
unsigned int sysclk6clkstctrl; |
||||
unsigned int rtcclkstctrl; |
||||
unsigned int l3fastclkstctrl; |
||||
unsigned int resv0[67]; |
||||
unsigned int mcasp0clkctrl; |
||||
unsigned int mcasp1clkctrl; |
||||
unsigned int mcasp2clkctrl; |
||||
unsigned int mcbspclkctrl; |
||||
unsigned int uart0clkctrl; |
||||
unsigned int uart1clkctrl; |
||||
unsigned int uart2clkctrl; |
||||
unsigned int gpio0clkctrl; |
||||
unsigned int gpio1clkctrl; |
||||
unsigned int i2c0clkctrl; |
||||
unsigned int i2c1clkctrl; |
||||
#if defined(CONFIG_TI814X) |
||||
unsigned int mcasp345clkctrl; |
||||
unsigned int atlclkctrl; |
||||
unsigned int mlbclkctrl; |
||||
unsigned int pataclkctrl; |
||||
unsigned int resv1[1]; |
||||
unsigned int uart3clkctrl; |
||||
unsigned int uart4clkctrl; |
||||
unsigned int uart5clkctrl; |
||||
#elif defined(CONFIG_TI816X) |
||||
unsigned int resv1[1]; |
||||
unsigned int timer1clkctrl; |
||||
unsigned int timer2clkctrl; |
||||
unsigned int timer3clkctrl; |
||||
unsigned int timer4clkctrl; |
||||
unsigned int timer5clkctrl; |
||||
unsigned int timer6clkctrl; |
||||
unsigned int timer7clkctrl; |
||||
#endif |
||||
unsigned int wdtimerclkctrl; |
||||
unsigned int spiclkctrl; |
||||
unsigned int mailboxclkctrl; |
||||
unsigned int spinboxclkctrl; |
||||
unsigned int mmudataclkctrl; |
||||
unsigned int resv2[2]; |
||||
unsigned int mmucfgclkctrl; |
||||
#if defined(CONFIG_TI814X) |
||||
unsigned int resv3[2]; |
||||
#elif defined(CONFIG_TI816X) |
||||
unsigned int resv3[1]; |
||||
unsigned int sdioclkctrl; |
||||
#endif |
||||
unsigned int ocmc0clkctrl; |
||||
#if defined(CONFIG_TI814X) |
||||
unsigned int vcpclkctrl; |
||||
#elif defined(CONFIG_TI816X) |
||||
unsigned int ocmc1clkctrl; |
||||
#endif |
||||
unsigned int resv4[2]; |
||||
unsigned int controlclkctrl; |
||||
unsigned int resv5[2]; |
||||
unsigned int gpmcclkctrl; |
||||
unsigned int ethernet0clkctrl; |
||||
unsigned int ethernet1clkctrl; |
||||
unsigned int mpuclkctrl; |
||||
#if defined(CONFIG_TI814X) |
||||
unsigned int debugssclkctrl; |
||||
#elif defined(CONFIG_TI816X) |
||||
unsigned int resv6[1]; |
||||
#endif |
||||
unsigned int l3clkctrl; |
||||
unsigned int l4hsclkctrl; |
||||
unsigned int l4lsclkctrl; |
||||
unsigned int rtcclkctrl; |
||||
unsigned int tpccclkctrl; |
||||
unsigned int tptc0clkctrl; |
||||
unsigned int tptc1clkctrl; |
||||
unsigned int tptc2clkctrl; |
||||
unsigned int tptc3clkctrl; |
||||
#if defined(CONFIG_TI814X) |
||||
unsigned int resv6[4]; |
||||
unsigned int dcan01clkctrl; |
||||
unsigned int mmchs0clkctrl; |
||||
unsigned int mmchs1clkctrl; |
||||
unsigned int mmchs2clkctrl; |
||||
unsigned int custefuseclkctrl; |
||||
#elif defined(CONFIG_TI816X) |
||||
unsigned int sr0clkctrl; |
||||
unsigned int sr1clkctrl; |
||||
#endif |
||||
}; |
||||
|
||||
#endif /* _CLOCK_TI81XX_H_ */ |
||||
@ -0,0 +1,61 @@ |
||||
/*
|
||||
* hardware_ti816x.h |
||||
* |
||||
* TI816x hardware specific header |
||||
* |
||||
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> |
||||
* Antoine Tenart, <atenart@adeneo-embedded.com> |
||||
* Based on TI-PSP-04.00.02.14 |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#ifndef __AM33XX_HARDWARE_TI816X_H |
||||
#define __AM33XX_HARDWARE_TI816X_H |
||||
|
||||
/* UART */ |
||||
#define UART0_BASE 0x48020000 |
||||
#define UART1_BASE 0x48022000 |
||||
#define UART2_BASE 0x48024000 |
||||
|
||||
/* Watchdog Timer */ |
||||
#define WDT_BASE 0x480C2000 |
||||
|
||||
/* Control Module Base Address */ |
||||
#define CTRL_BASE 0x48140000 |
||||
|
||||
/* PRCM Base Address */ |
||||
#define PRCM_BASE 0x48180000 |
||||
|
||||
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) |
||||
#define PRM_RSTST (PRM_RSTCTRL + 8) |
||||
|
||||
/* VTP Base address */ |
||||
#define VTP0_CTRL_ADDR 0x48198358 |
||||
#define VTP1_CTRL_ADDR 0x4819A358 |
||||
|
||||
/* DDR Base address */ |
||||
#define DDR_PHY_CMD_ADDR 0x48198000 |
||||
#define DDR_PHY_DATA_ADDR 0x481980C8 |
||||
#define DDR_PHY_CMD_ADDR2 0x4819A000 |
||||
#define DDR_PHY_DATA_ADDR2 0x4819A0C8 |
||||
#define DDR_DATA_REGS_NR 4 |
||||
|
||||
|
||||
#define DDRPHY_0_CONFIG_BASE 0x48198000 |
||||
#define DDRPHY_1_CONFIG_BASE 0x4819A000 |
||||
#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ |
||||
DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) |
||||
|
||||
/* RTC base address */ |
||||
#define RTC_BASE 0x480C0000 |
||||
|
||||
#endif /* __AM33XX_HARDWARE_TI816X_H */ |
||||
@ -0,0 +1,363 @@ |
||||
/*
|
||||
* mux_ti816x.h |
||||
* |
||||
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> |
||||
* Antoine Tenart, <atenart@adeneo-embedded.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation version 2. |
||||
* |
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
||||
* kind, whether express or implied; without even the implied warranty |
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#ifndef _MUX_TI816X_H_ |
||||
#define _MUX_TI816X_H_ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
|
||||
#define MUX_CFG(value, offset) \ |
||||
__raw_writel(value, (CTRL_BASE + offset)); |
||||
|
||||
#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ |
||||
#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ |
||||
#define PULLUDEN (0x0 << 3) /* Pull up enabled */ |
||||
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ |
||||
#define MODE(val) (val) /* used for Readability */ |
||||
|
||||
|
||||
/*
|
||||
* PAD CONTROL OFFSETS |
||||
* Field names corresponds to the pad signal name |
||||
*/ |
||||
struct pad_signals { |
||||
int pincntl1; |
||||
int pincntl2; |
||||
int pincntl3; |
||||
int pincntl4; |
||||
int pincntl5; |
||||
int pincntl6; |
||||
int pincntl7; |
||||
int pincntl8; |
||||
int pincntl9; |
||||
int pincntl10; |
||||
int pincntl11; |
||||
int pincntl12; |
||||
int pincntl13; |
||||
int pincntl14; |
||||
int pincntl15; |
||||
int pincntl16; |
||||
int pincntl17; |
||||
int pincntl18; |
||||
int pincntl19; |
||||
int pincntl20; |
||||
int pincntl21; |
||||
int pincntl22; |
||||
int pincntl23; |
||||
int pincntl24; |
||||
int pincntl25; |
||||
int pincntl26; |
||||
int pincntl27; |
||||
int pincntl28; |
||||
int pincntl29; |
||||
int pincntl30; |
||||
int pincntl31; |
||||
int pincntl32; |
||||
int pincntl33; |
||||
int pincntl34; |
||||
int pincntl35; |
||||
int pincntl36; |
||||
int pincntl37; |
||||
int pincntl38; |
||||
int pincntl39; |
||||
int pincntl40; |
||||
int pincntl41; |
||||
int pincntl42; |
||||
int pincntl43; |
||||
int pincntl44; |
||||
int pincntl45; |
||||
int pincntl46; |
||||
int pincntl47; |
||||
int pincntl48; |
||||
int pincntl49; |
||||
int pincntl50; |
||||
int pincntl51; |
||||
int pincntl52; |
||||
int pincntl53; |
||||
int pincntl54; |
||||
int pincntl55; |
||||
int pincntl56; |
||||
int pincntl57; |
||||
int pincntl58; |
||||
int pincntl59; |
||||
int pincntl60; |
||||
int pincntl61; |
||||
int pincntl62; |
||||
int pincntl63; |
||||
int pincntl64; |
||||
int pincntl65; |
||||
int pincntl66; |
||||
int pincntl67; |
||||
int pincntl68; |
||||
int pincntl69; |
||||
int pincntl70; |
||||
int pincntl71; |
||||
int pincntl72; |
||||
int pincntl73; |
||||
int pincntl74; |
||||
int pincntl75; |
||||
int pincntl76; |
||||
int pincntl77; |
||||
int pincntl78; |
||||
int pincntl79; |
||||
int pincntl80; |
||||
int pincntl81; |
||||
int pincntl82; |
||||
int pincntl83; |
||||
int pincntl84; |
||||
int pincntl85; |
||||
int pincntl86; |
||||
int pincntl87; |
||||
int pincntl88; |
||||
int pincntl89; |
||||
int pincntl90; |
||||
int pincntl91; |
||||
int pincntl92; |
||||
int pincntl93; |
||||
int pincntl94; |
||||
int pincntl95; |
||||
int pincntl96; |
||||
int pincntl97; |
||||
int pincntl98; |
||||
int pincntl99; |
||||
int pincntl100; |
||||
int pincntl101; |
||||
int pincntl102; |
||||
int pincntl103; |
||||
int pincntl104; |
||||
int pincntl105; |
||||
int pincntl106; |
||||
int pincntl107; |
||||
int pincntl108; |
||||
int pincntl109; |
||||
int pincntl110; |
||||
int pincntl111; |
||||
int pincntl112; |
||||
int pincntl113; |
||||
int pincntl114; |
||||
int pincntl115; |
||||
int pincntl116; |
||||
int pincntl117; |
||||
int pincntl118; |
||||
int pincntl119; |
||||
int pincntl120; |
||||
int pincntl121; |
||||
int pincntl122; |
||||
int pincntl123; |
||||
int pincntl124; |
||||
int pincntl125; |
||||
int pincntl126; |
||||
int pincntl127; |
||||
int pincntl128; |
||||
int pincntl129; |
||||
int pincntl130; |
||||
int pincntl131; |
||||
int pincntl132; |
||||
int pincntl133; |
||||
int pincntl134; |
||||
int pincntl135; |
||||
int pincntl136; |
||||
int pincntl137; |
||||
int pincntl138; |
||||
int pincntl139; |
||||
int pincntl140; |
||||
int pincntl141; |
||||
int pincntl142; |
||||
int pincntl143; |
||||
int pincntl144; |
||||
int pincntl145; |
||||
int pincntl146; |
||||
int pincntl147; |
||||
int pincntl148; |
||||
int pincntl149; |
||||
int pincntl150; |
||||
int pincntl151; |
||||
int pincntl152; |
||||
int pincntl153; |
||||
int pincntl154; |
||||
int pincntl155; |
||||
int pincntl156; |
||||
int pincntl157; |
||||
int pincntl158; |
||||
int pincntl159; |
||||
int pincntl160; |
||||
int pincntl161; |
||||
int pincntl162; |
||||
int pincntl163; |
||||
int pincntl164; |
||||
int pincntl165; |
||||
int pincntl166; |
||||
int pincntl167; |
||||
int pincntl168; |
||||
int pincntl169; |
||||
int pincntl170; |
||||
int pincntl171; |
||||
int pincntl172; |
||||
int pincntl173; |
||||
int pincntl174; |
||||
int pincntl175; |
||||
int pincntl176; |
||||
int pincntl177; |
||||
int pincntl178; |
||||
int pincntl179; |
||||
int pincntl180; |
||||
int pincntl181; |
||||
int pincntl182; |
||||
int pincntl183; |
||||
int pincntl184; |
||||
int pincntl185; |
||||
int pincntl186; |
||||
int pincntl187; |
||||
int pincntl188; |
||||
int pincntl189; |
||||
int pincntl190; |
||||
int pincntl191; |
||||
int pincntl192; |
||||
int pincntl193; |
||||
int pincntl194; |
||||
int pincntl195; |
||||
int pincntl196; |
||||
int pincntl197; |
||||
int pincntl198; |
||||
int pincntl199; |
||||
int pincntl200; |
||||
int pincntl201; |
||||
int pincntl202; |
||||
int pincntl203; |
||||
int pincntl204; |
||||
int pincntl205; |
||||
int pincntl206; |
||||
int pincntl207; |
||||
int pincntl208; |
||||
int pincntl209; |
||||
int pincntl210; |
||||
int pincntl211; |
||||
int pincntl212; |
||||
int pincntl213; |
||||
int pincntl214; |
||||
int pincntl215; |
||||
int pincntl216; |
||||
int pincntl217; |
||||
int pincntl218; |
||||
int pincntl219; |
||||
int pincntl220; |
||||
int pincntl221; |
||||
int pincntl222; |
||||
int pincntl223; |
||||
int pincntl224; |
||||
int pincntl225; |
||||
int pincntl226; |
||||
int pincntl227; |
||||
int pincntl228; |
||||
int pincntl229; |
||||
int pincntl230; |
||||
int pincntl231; |
||||
int pincntl232; |
||||
int pincntl233; |
||||
int pincntl234; |
||||
int pincntl235; |
||||
int pincntl236; |
||||
int pincntl237; |
||||
int pincntl238; |
||||
int pincntl239; |
||||
int pincntl240; |
||||
int pincntl241; |
||||
int pincntl242; |
||||
int pincntl243; |
||||
int pincntl244; |
||||
int pincntl245; |
||||
int pincntl246; |
||||
int pincntl247; |
||||
int pincntl248; |
||||
int pincntl249; |
||||
int pincntl250; |
||||
int pincntl251; |
||||
int pincntl252; |
||||
int pincntl253; |
||||
int pincntl254; |
||||
int pincntl255; |
||||
int pincntl256; |
||||
int pincntl257; |
||||
int pincntl258; |
||||
int pincntl259; |
||||
int pincntl260; |
||||
int pincntl261; |
||||
int pincntl262; |
||||
int pincntl263; |
||||
int pincntl264; |
||||
int pincntl265; |
||||
int pincntl266; |
||||
int pincntl267; |
||||
int pincntl268; |
||||
int pincntl269; |
||||
int pincntl270; |
||||
int pincntl271; |
||||
int pincntl272; |
||||
int pincntl273; |
||||
int pincntl274; |
||||
int pincntl275; |
||||
int pincntl276; |
||||
int pincntl277; |
||||
int pincntl278; |
||||
int pincntl279; |
||||
int pincntl280; |
||||
int pincntl281; |
||||
int pincntl282; |
||||
int pincntl283; |
||||
int pincntl284; |
||||
int pincntl285; |
||||
int pincntl286; |
||||
int pincntl287; |
||||
int pincntl288; |
||||
int pincntl289; |
||||
int pincntl290; |
||||
int pincntl291; |
||||
int pincntl292; |
||||
int pincntl293; |
||||
int pincntl294; |
||||
int pincntl295; |
||||
int pincntl296; |
||||
int pincntl297; |
||||
int pincntl298; |
||||
int pincntl299; |
||||
int pincntl300; |
||||
int pincntl301; |
||||
int pincntl302; |
||||
int pincntl303; |
||||
int pincntl304; |
||||
int pincntl305; |
||||
int pincntl306; |
||||
int pincntl307; |
||||
int pincntl308; |
||||
int pincntl309; |
||||
int pincntl310; |
||||
int pincntl311; |
||||
int pincntl312; |
||||
int pincntl313; |
||||
int pincntl314; |
||||
int pincntl315; |
||||
int pincntl316; |
||||
int pincntl317; |
||||
int pincntl318; |
||||
int pincntl319; |
||||
int pincntl320; |
||||
int pincntl321; |
||||
int pincntl322; |
||||
int pincntl323; |
||||
}; |
||||
|
||||
#endif /* endif _MUX_TI816X_H_ */ |
||||
Loading…
Reference in new issue