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x86: Move CONFIG_X86_SERIAL to Kconfig

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Move this config option to Kconfig and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
master
Simon Glass 10 years ago
parent ca4435ef28
commit dcfe4a54ed
7 changed files with 11 additions and 10 deletions
  1. 10
      drivers/serial/Kconfig
  2. 2
      include/configs/bayleybay.h
  3. 1
      include/configs/crownbay.h
  4. 2
      include/configs/galileo.h
  5. 2
      include/configs/minnowmax.h
  6. 2
      include/configs/qemu-x86.h
  7. 2
      include/configs/x86-chromebook.h

10
drivers/serial/Kconfig
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@ -102,3 +102,13 @@ config UNIPHIER_SERIAL
help
If you have a UniPhier based board and want to use the on-chip
serial ports, say Y to this option. If unsure, say N.
config X86_SERIAL
bool "Support for 16550 serial port on x86 machines"
depends on X86
default y
help
Most x86 machines have a ns16550 UART or compatible. This can be
enabled in the device tree with the correct input clock frequency
provided (default 1843200). Enable this to obtain serial console
output.

2
include/configs/bayleybay.h
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@ -16,8 +16,6 @@
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_X86_SERIAL
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
#define CONFIG_SYS_EARLY_PCI_INIT
#define CONFIG_PCI_PNP

1
include/configs/crownbay.h
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@ -17,7 +17,6 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_X86_SERIAL
#define CONFIG_SMSC_LPC47M
#define CONFIG_PCI_MEM_BUS 0x40000000

2
include/configs/galileo.h
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@ -17,8 +17,6 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_X86_SERIAL
/* ns16550 UART is memory-mapped in Quark SoC */
#undef CONFIG_SYS_NS16550_PORT_MAPPED

2
include/configs/minnowmax.h
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@ -16,7 +16,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_X86_SERIAL
#define CONFIG_SMSC_LPC47M
#define CONFIG_PCI_MEM_BUS 0xd0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS

2
include/configs/qemu-x86.h
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@ -16,8 +16,6 @@
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_X86_SERIAL
#define CONFIG_PCI_MEM_BUS 0xc0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000

2
include/configs/x86-chromebook.h
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@ -17,8 +17,6 @@
#define CONFIG_X86_MRC_ADDR 0xfffa0000
#define CONFIG_CACHE_MRC_SIZE_KB 512
#define CONFIG_X86_SERIAL
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \

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