Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>master
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/*
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* (C) Copyright 2009 |
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* Heiko Schocher, DENX Software Engineering, hs@denx.de |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <nand.h> |
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#include <asm/io.h> |
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#define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000) |
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#define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000) |
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#define read_mode() in_8(CONFIG_NAND_MODE_REG) |
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#define write_mode(val) out_8(CONFIG_NAND_MODE_REG, val) |
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#define read_data() in_8(CONFIG_NAND_DATA_REG) |
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#define write_data(val) out_8(CONFIG_NAND_DATA_REG, val) |
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#define KPN_RDY2 (1 << 7) |
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#define KPN_RDY1 (1 << 6) |
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#define KPN_WPN (1 << 4) |
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#define KPN_CE2N (1 << 3) |
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#define KPN_CE1N (1 << 2) |
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#define KPN_ALE (1 << 1) |
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#define KPN_CLE (1 << 0) |
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#define KPN_DEFAULT_CHIP_DELAY 50 |
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static int kpn_chip_ready(void) |
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{ |
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if (read_mode() & KPN_RDY1) |
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return 1; |
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return 0; |
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} |
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static void kpn_wait_rdy(void) |
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{ |
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int cnt = 1000000; |
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while (--cnt && !kpn_chip_ready()) |
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udelay(1); |
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if (!cnt) |
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printf ("timeout while waiting for RDY\n"); |
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} |
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static void kpn_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
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{ |
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u8 reg_val = read_mode(); |
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if (ctrl & NAND_CTRL_CHANGE) { |
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reg_val = reg_val & ~(KPN_ALE + KPN_CLE); |
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if (ctrl & NAND_CLE) |
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reg_val = reg_val | KPN_CLE; |
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if (ctrl & NAND_ALE) |
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reg_val = reg_val | KPN_ALE; |
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if (ctrl & NAND_NCE) |
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reg_val = reg_val & ~KPN_CE1N; |
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else |
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reg_val = reg_val | KPN_CE1N; |
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write_mode(reg_val); |
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} |
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if (cmd != NAND_CMD_NONE) |
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write_data(cmd); |
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/* wait until flash is ready */ |
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kpn_wait_rdy(); |
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} |
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static u_char kpn_nand_read_byte(struct mtd_info *mtd) |
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{ |
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return read_data(); |
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} |
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static void kpn_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
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{ |
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int i; |
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for (i = 0; i < len; i++) { |
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write_data(buf[i]); |
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kpn_wait_rdy(); |
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} |
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} |
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static void kpn_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
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{ |
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int i; |
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for (i = 0; i < len; i++) |
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buf[i] = read_data(); |
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} |
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static int kpn_nand_dev_ready(struct mtd_info *mtd) |
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{ |
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kpn_wait_rdy(); |
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return 1; |
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} |
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int board_nand_init(struct nand_chip *nand) |
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{ |
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nand->ecc.mode = NAND_ECC_SOFT; |
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/* Reference hardware control function */ |
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nand->cmd_ctrl = kpn_nand_hwcontrol; |
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nand->read_byte = kpn_nand_read_byte; |
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nand->write_buf = kpn_nand_write_buf; |
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nand->read_buf = kpn_nand_read_buf; |
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nand->dev_ready = kpn_nand_dev_ready; |
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nand->chip_delay = KPN_DEFAULT_CHIP_DELAY; |
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/* reset mode register */ |
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write_mode(KPN_CE1N + KPN_CE2N + KPN_WPN); |
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return 0; |
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} |
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