parent
76544f80e4
commit
debb7354d1
@ -0,0 +1,57 @@ |
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o oftree.o
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SOBJS := init.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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%.dtb: %.dts |
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dtc -f -V 0x10 -I dts -O dtb $< >$@
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%.c: %.dtb |
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xxd -i $< \
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| sed -e "s/^unsigned char/const unsigned char/g" \
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| sed -e "s/^unsigned int/const unsigned int/g" > $@
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clean: |
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rm -f $(OBJS) $(SOBJS) *.dtb oftree.c
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.PHONY: distclean |
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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ifeq ($(filter distclean, $(MAKECMDGOALS)),) |
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-include .depend |
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endif |
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#########################################################################
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@ -0,0 +1,32 @@ |
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# Copyright 2004 Freescale Semiconductor.
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# Modified by Jeff Brown (jeffrey@freescale.com)
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# mpc8641hpcn board
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# default CCSRBAR is at 0xff700000
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# assume U-Boot is less than 0.5MB
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#
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#TEXT_BASE = 0xfff01000
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TEXT_BASE = 0x00400000
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PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
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PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
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@ -0,0 +1,550 @@ |
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/*
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* (C) Copyright 2003 Motorola Inc. |
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* Xianghua Xiao,(X.Xiao@motorola.com) |
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* |
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* (C) Copyright 2000, 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com |
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* Add support the Sharp chips on the mpc8260ads. |
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* I started with board/ip860/flash.c and made changes I found in |
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* the MTD project by David Schleef. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#if !defined(CFG_NO_FLASH) |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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#if defined(CFG_ENV_IS_IN_FLASH) |
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# ifndef CFG_ENV_ADDR |
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# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) |
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# endif |
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# ifndef CFG_ENV_SIZE |
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# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE |
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# endif |
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# ifndef CFG_ENV_SECT_SIZE |
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# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE |
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# endif |
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#endif |
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#undef DEBUG |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
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static int write_word (flash_info_t *info, ulong dest, ulong data); |
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static int clear_block_lock_bit(vu_long * addr); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long size; |
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int i; |
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/* Init: enable write,
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* or we cannot even write flash commands |
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*/ |
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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/* set the default sector offset */ |
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} |
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/* Static FLASH Bank configuration here - FIXME XXX */ |
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size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size, size<<20); |
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} |
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/* Re-do sizing to get full correct info */ |
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size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); |
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flash_info[0].size = size; |
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#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
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/* monitor protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_MONITOR_BASE, |
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CFG_MONITOR_BASE+monitor_flash_len-1, |
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&flash_info[0]); |
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#ifdef CFG_ENV_IS_IN_FLASH |
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/* ENV protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_ENV_ADDR, |
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CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, |
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&flash_info[0]); |
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#endif |
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#endif |
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return (size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: printf ("Intel "); break; |
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case FLASH_MAN_SHARP: printf ("Sharp "); break; |
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default: printf ("Unknown Vendor "); break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); |
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break; |
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case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); |
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break; |
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case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); |
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break; |
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case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); |
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break; |
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case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n"); |
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break; |
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default: printf ("Unknown Chip Type\n"); |
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break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i=0; i<info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", |
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info->start[i], |
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info->protect[i] ? " (RO)" : " " |
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); |
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} |
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printf ("\n"); |
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} |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
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{ |
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short i; |
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ulong value; |
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ulong base = (ulong)addr; |
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ulong sector_offset; |
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#ifdef DEBUG |
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printf("Check flash at 0x%08x\n",(uint)addr); |
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#endif |
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/* Write "Intelligent Identifier" command: read Manufacturer ID */ |
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*addr = 0x90909090; |
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udelay(20); |
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asm("sync"); |
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value = addr[0] & 0x00FF00FF; |
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#ifdef DEBUG |
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printf("manufacturer=0x%x\n",(uint)value); |
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#endif |
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switch (value) { |
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case MT_MANUFACT: /* SHARP, MT or => Intel */ |
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case INTEL_ALT_MANU: |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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#if defined(CONFIG_MPC8641_SIM) |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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#else |
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printf("unknown manufacturer: %x\n", (unsigned int)value); |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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return (0); /* no or unknown flash */ |
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#endif |
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} |
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value = addr[1] & 0x00FF00FF; /* device ID */ |
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#ifdef DEBUG |
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printf("deviceID=0x%x\n",(uint)value); |
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#endif |
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switch (value) { |
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case (INTEL_ID_28F016S): |
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info->flash_id += FLASH_28F016SV; |
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info->sector_count = 32; |
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info->size = 0x00400000; |
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sector_offset = 0x20000; |
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break; /* => 2x2 MB */ |
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case (INTEL_ID_28F160S3): |
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info->flash_id += FLASH_28F160S3; |
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info->sector_count = 32; |
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info->size = 0x00400000; |
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sector_offset = 0x20000; |
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break; /* => 2x2 MB */ |
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case (INTEL_ID_28F320S3): |
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info->flash_id += FLASH_28F320S3; |
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info->sector_count = 64; |
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info->size = 0x00800000; |
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sector_offset = 0x20000; |
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break; /* => 2x4 MB */ |
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case (INTEL_ID_28F640J3A): |
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info->flash_id += FLASH_28F640J3A; |
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info->sector_count = 64; |
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info->size = 0x01000000; |
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sector_offset = 0x40000; |
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break; /* => 2x8 MB */ |
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case SHARP_ID_28F016SCL: |
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case SHARP_ID_28F016SCZ: |
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info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; |
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info->sector_count = 32; |
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info->size = 0x00800000; |
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sector_offset = 0x40000; |
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break; /* => 4x2 MB */ |
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default: |
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#if defined(CONFIG_MPC8641_SIM) |
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info->flash_id += FLASH_28F640J3A; |
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info->sector_count = 64; |
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info->size = 0x01000000; |
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sector_offset = 0x40000; |
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break; /* => 2x8 MB */ |
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#else |
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info->flash_id = FLASH_UNKNOWN; |
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return (0); /* => no or unknown flash */ |
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#endif |
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|
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} |
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/* set up sector start address table */ |
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for (i = 0; i < info->sector_count; i++) { |
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info->start[i] = base; |
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base += sector_offset; |
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/* don't know how to check sector protection */ |
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info->protect[i] = 0; |
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} |
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|
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/*
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* Prevent writes to uninitialized FLASH. |
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*/ |
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if (info->flash_id != FLASH_UNKNOWN) { |
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addr = (vu_long *)info->start[0]; |
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*addr = 0xFFFFFF; /* reset bank to read array mode */ |
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asm("sync"); |
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} |
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return (info->size); |
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} |
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|
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|
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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int flag, prot, sect; |
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ulong start, now, last; |
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|
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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|
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if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) |
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&& ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { |
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printf ("Can't erase unknown flash type %08lx - aborted\n", |
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info->flash_id); |
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return 1; |
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} |
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|
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prot = 0; |
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for (sect=s_first; sect<=s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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|
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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|
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#ifdef DEBUG |
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printf("\nFlash Erase:\n"); |
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#endif |
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/* Make Sure Block Lock Bit is not set. */ |
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if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ |
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return 1; |
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} |
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|
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/* Start erase on unprotected sectors */ |
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#if defined(DEBUG) |
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printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); |
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#endif |
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for (sect = s_first; sect<=s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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vu_long *addr = (vu_long *)(info->start[sect]); |
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asm("sync"); |
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|
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last = start = get_timer (0); |
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|
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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|
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/* Reset Array */ |
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*addr = 0xffffffff; |
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asm("sync"); |
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/* Clear Status Register */ |
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*addr = 0x50505050; |
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asm("sync"); |
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/* Single Block Erase Command */ |
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*addr = 0x20202020; |
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asm("sync"); |
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/* Confirm */ |
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*addr = 0xD0D0D0D0; |
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asm("sync"); |
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|
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if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { |
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/* Resume Command, as per errata update */ |
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*addr = 0xD0D0D0D0; |
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asm("sync"); |
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} |
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|
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts(); |
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|
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/* wait at least 80us - let's wait 1 ms */ |
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udelay (1000); |
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while ((*addr & 0x00800080) != 0x00800080) { |
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if(*addr & 0x00200020){ |
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printf("Error in Block Erase - Lock Bit may be set!\n"); |
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printf("Status Register = 0x%X\n", (uint)*addr); |
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*addr = 0xFFFFFFFF; /* reset bank */ |
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asm("sync"); |
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return 1; |
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} |
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if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
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printf ("Timeout\n"); |
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*addr = 0xFFFFFFFF; /* reset bank */ |
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asm("sync"); |
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return 1; |
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} |
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/* show that we're waiting */ |
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if ((now - last) > 1000) { /* every second */ |
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putc ('.'); |
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last = now; |
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} |
||||
} |
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|
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/* reset to read mode */ |
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*addr = 0xFFFFFFFF; |
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asm("sync"); |
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} |
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} |
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|
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printf ("flash erase done\n"); |
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return 0; |
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} |
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|
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/*-----------------------------------------------------------------------
|
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* Copy memory to flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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|
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
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{ |
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ulong cp, wp, data; |
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int i, l, rc; |
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|
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wp = (addr & ~3); /* get lower word aligned address */ |
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|
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/*
|
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* handle unaligned start bytes |
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*/ |
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if ((l = addr - wp) != 0) { |
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data = 0; |
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for (i=0, cp=wp; i<l; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *)cp); |
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} |
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for (; i<4 && cnt>0; ++i) { |
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data = (data << 8) | *src++; |
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--cnt; |
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++cp; |
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} |
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for (; cnt==0 && i<4; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *)cp); |
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} |
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|
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if ((rc = write_word(info, wp, data)) != 0) { |
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return (rc); |
||||
} |
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wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
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while (cnt >= 4) { |
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data = 0; |
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for (i=0; i<4; ++i) { |
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data = (data << 8) | *src++; |
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} |
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if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
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} |
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wp += 4; |
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cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
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for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
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data = (data << 8) | *src++; |
||||
--cnt; |
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} |
||||
for (; i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
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|
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return (write_word(info, wp, data)); |
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} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data) |
||||
{ |
||||
vu_long *addr = (vu_long *)dest; |
||||
ulong start, csr; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*addr & data) != data) { |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
/* Write Command */ |
||||
*addr = 0x10101010; |
||||
asm("sync"); |
||||
|
||||
/* Write Data */ |
||||
*addr = data; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
flag = 0; |
||||
|
||||
while (((csr = *addr) & 0x00800080) != 0x00800080) { |
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
||||
flag = 1; |
||||
break; |
||||
} |
||||
} |
||||
if (csr & 0x40404040) { |
||||
printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); |
||||
flag = 1; |
||||
} |
||||
|
||||
/* Clear Status Registers Command */ |
||||
*addr = 0x50505050; |
||||
asm("sync"); |
||||
/* Reset to read array mode */ |
||||
*addr = 0xFFFFFFFF; |
||||
asm("sync"); |
||||
|
||||
return (flag); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Clear Block Lock Bit, returns: |
||||
* 0 - OK |
||||
* 1 - Timeout |
||||
*/ |
||||
|
||||
static int clear_block_lock_bit(vu_long * addr) |
||||
{ |
||||
ulong start, now; |
||||
|
||||
/* Reset Array */ |
||||
*addr = 0xffffffff; |
||||
asm("sync"); |
||||
/* Clear Status Register */ |
||||
*addr = 0x50505050; |
||||
asm("sync"); |
||||
|
||||
*addr = 0x60606060; |
||||
asm("sync"); |
||||
*addr = 0xd0d0d0d0; |
||||
asm("sync"); |
||||
|
||||
start = get_timer (0); |
||||
while((*addr & 0x00800080) != 0x00800080){ |
||||
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout on clearing Block Lock Bit\n"); |
||||
*addr = 0xFFFFFFFF; /* reset bank */ |
||||
asm("sync"); |
||||
return 1; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
#endif /* !CFG_NO_FLASH */ |
@ -0,0 +1,172 @@ |
||||
/* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Jeff Brown (jeffrey@freescale.com)
|
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc86xx.h> |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
||||
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
#else |
||||
#define LAWBAR1 0 |
||||
#define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) |
||||
/*#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) */ |
||||
#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))) |
||||
|
||||
/* |
||||
* This is not so much the SDRAM map as it is the whole localbus map. |
||||
*/ |
||||
#define LAWBAR4 ((0xf8100000>>12) & 0xffffff) |
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) |
||||
|
||||
#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff) |
||||
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
||||
|
||||
#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff) |
||||
/*#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */ |
||||
#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) |
||||
|
||||
#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) |
||||
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) |
||||
|
||||
|
||||
/* |
||||
* Rapid IO at 0xc000_0000 for 512 M |
||||
*/ |
||||
/* |
||||
#ifdef CFG_INIT_RAM_LOCK |
||||
#define LAWBAR7 ((CFG_RIO_MEM_BASE>>12) & 0xffffff) |
||||
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
#endif |
||||
*/ |
||||
/* |
||||
* Stack at 0xfc00_0000 for 32M on LBC |
||||
*/ |
||||
#if !defined(CFG_INIT_RAM_LOCK) |
||||
#define LAWBAR7 ((CFG_INIT_RAM_ADDR>>12) & 0xffffff) |
||||
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) |
||||
#endif |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
lis r7,CFG_CCSRBAR@h
|
||||
ori r7,r7,CFG_CCSRBAR@l
|
||||
|
||||
addi r4,r7,0 |
||||
addi r5,r7,0 |
||||
|
||||
/* Skip LAWAR0, start at LAWAR1 */ |
||||
lis r6,LAWBAR1@h
|
||||
ori r6,r6,LAWBAR1@l
|
||||
stwu r6, 0xc28(r4) |
||||
|
||||
lis r6,LAWAR1@h
|
||||
ori r6,r6,LAWAR1@l
|
||||
stwu r6, 0xc30(r5) |
||||
|
||||
/* LAWBAR2, LAWAR2 */ |
||||
lis r6,LAWBAR2@h
|
||||
ori r6,r6,LAWBAR2@l
|
||||
stwu r6, 0x20(r4) |
||||
|
||||
lis r6,LAWAR2@h
|
||||
ori r6,r6,LAWAR2@l
|
||||
stwu r6, 0x20(r5) |
||||
|
||||
/* LAWBAR3, LAWAR3 */ |
||||
lis r6,LAWBAR3@h
|
||||
ori r6,r6,LAWBAR3@l
|
||||
stwu r6, 0x20(r4) |
||||
|
||||
lis r6,LAWAR3@h
|
||||
ori r6,r6,LAWAR3@l
|
||||
stwu r6, 0x20(r5) |
||||
|
||||
/* LAWBAR4, LAWAR4 */ |
||||
lis r6,LAWBAR4@h
|
||||
ori r6,r6,LAWBAR4@l
|
||||
stwu r6, 0x20(r4) |
||||
|
||||
lis r6,LAWAR4@h
|
||||
ori r6,r6,LAWAR4@l
|
||||
stwu r6, 0x20(r5) |
||||
/* LAWBAR5, LAWAR5 */ |
||||
lis r6,LAWBAR5@h
|
||||
ori r6,r6,LAWBAR5@l
|
||||
stwu r6, 0x20(r4) |
||||
|
||||
lis r6,LAWAR5@h
|
||||
ori r6,r6,LAWAR5@l
|
||||
stwu r6, 0x20(r5) |
||||
|
||||
/* LAWBAR6, LAWAR6 */ |
||||
lis r6,LAWBAR6@h
|
||||
ori r6,r6,LAWBAR6@l
|
||||
stwu r6, 0x20(r4) |
||||
|
||||
lis r6,LAWAR6@h
|
||||
ori r6,r6,LAWAR6@l
|
||||
stwu r6, 0x20(r5) |
||||
|
||||
/* LAWBAR7, LAWAR7 */ |
||||
lis r6,LAWBAR7@h
|
||||
ori r6,r6,LAWBAR7@l
|
||||
stwu r6, 0x20(r4) |
||||
|
||||
lis r6,LAWAR7@h
|
||||
ori r6,r6,LAWAR7@l
|
||||
stwu r6, 0x20(r5) |
||||
|
||||
blr |
||||
|
@ -0,0 +1,315 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Jeff Brown (jeffrey@freescale.com) |
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
||||
* |
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <pci.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_86xx.h> |
||||
#include <spd.h> |
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) |
||||
#include <ft_build.h> |
||||
extern void ft_cpu_setup(void *blob, bd_t *bd); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
||||
extern void ddr_enable_ecc(unsigned int dram_size); |
||||
#endif |
||||
|
||||
extern long int spd_sdram(void); |
||||
|
||||
void local_bus_init(void); |
||||
void sdram_init(void); |
||||
long int fixed_sdram(void); |
||||
|
||||
|
||||
int board_early_init_f (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
puts("Board: MPC8641HPCN\n"); |
||||
|
||||
#ifdef CONFIG_PCI |
||||
|
||||
/* Sri: Note that at this point we will only test on PCI1
|
||||
*/ |
||||
|
||||
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; |
||||
volatile ccsr_gur_t *gur = &immap->im_gur; |
||||
volatile ccsr_pex_t *pex1 = &immap->im_pex1; |
||||
|
||||
uint devdisr = gur->devdisr; |
||||
uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; |
||||
uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; |
||||
uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); |
||||
|
||||
|
||||
if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ |
||||
debug ("PCI-EXPRESS 1: %s \n", |
||||
pex1_agent ? "Agent" : "Host"); |
||||
debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); |
||||
if (pex1->pme_msg_det) { |
||||
pex1->pme_msg_det = 0xffffffff; |
||||
debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det); |
||||
} |
||||
debug ("\n"); |
||||
} else { |
||||
printf ("PCI-EXPRESS 1: Disabled\n"); |
||||
} |
||||
|
||||
#else |
||||
printf("PCI-EXPRESS1: Disabled\n"); |
||||
#endif |
||||
|
||||
/*
|
||||
* Initialize local bus. |
||||
*/ |
||||
local_bus_init(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
long int |
||||
initdram(int board_type) |
||||
{ |
||||
long dram_size = 0; |
||||
extern long spd_sdram (void); |
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
dram_size = spd_sdram (); |
||||
#else |
||||
dram_size = fixed_sdram (); |
||||
#endif |
||||
|
||||
#if defined(CFG_RAMBOOT) |
||||
puts(" DDR: "); |
||||
return dram_size; |
||||
#endif |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
||||
/*
|
||||
* Initialize and enable DDR ECC. |
||||
*/ |
||||
ddr_enable_ecc(dram_size); |
||||
#endif |
||||
|
||||
/*
|
||||
* Initialize SDRAM. Currently HPCN doesn't have |
||||
* SDRAM but we'll leave this here for now |
||||
* in case someone changes their mind |
||||
*/ |
||||
#if !defined(CONFIG_MPC8641HPCN) |
||||
// sdram_init();
|
||||
#endif |
||||
|
||||
puts(" DDR: "); |
||||
return dram_size; |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Initialize Local Bus |
||||
*/ |
||||
|
||||
void |
||||
local_bus_init(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc; |
||||
|
||||
uint clkdiv; |
||||
uint lbc_hz; |
||||
sys_info_t sysinfo; |
||||
|
||||
/*
|
||||
* Errata LBC11. |
||||
* Fix Local Bus clock glitch when DLL is enabled. |
||||
* |
||||
* If localbus freq is < 66Mhz, DLL bypass mode must be used. |
||||
* If localbus freq is > 133Mhz, DLL can be safely enabled. |
||||
* Between 66 and 133, the DLL is enabled with an override workaround. |
||||
*/ |
||||
|
||||
get_sys_info(&sysinfo); |
||||
clkdiv = lbc->lcrr & 0x0f; |
||||
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; |
||||
} |
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int testdram (void) |
||||
{ |
||||
uint *pstart = (uint *) CFG_MEMTEST_START; |
||||
uint *pend = (uint *) CFG_MEMTEST_END; |
||||
uint *p; |
||||
|
||||
printf("SDRAM test phase 1:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0xaaaaaaaa; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0xaaaaaaaa) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf("SDRAM test phase 2:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0x55555555; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0x55555555) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf("SDRAM test passed.\n"); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect. |
||||
************************************************************************/ |
||||
long int fixed_sdram (void) |
||||
{ |
||||
#if !defined(CFG_RAMBOOT) |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr1; |
||||
|
||||
ddr->cs0_bnds = CFG_DDR_CS0_BNDS; |
||||
ddr->cs0_config = CFG_DDR_CS0_CONFIG; |
||||
ddr->ext_refrec = CFG_DDR_EXT_REFRESH; |
||||
ddr->timing_cfg_0 = CFG_DDR_TIMING_0; |
||||
ddr->timing_cfg_1 = CFG_DDR_TIMING_1; |
||||
ddr->timing_cfg_2 = CFG_DDR_TIMING_2; |
||||
ddr->sdram_mode_1 = CFG_DDR_MODE_1; |
||||
ddr->sdram_mode_2 = CFG_DDR_MODE_2; |
||||
ddr->sdram_interval = CFG_DDR_INTERVAL; |
||||
ddr->sdram_data_init = CFG_DDR_DATA_INIT; |
||||
ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; |
||||
ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
|
||||
ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; |
||||
|
||||
#if defined (CONFIG_DDR_ECC) |
||||
ddr->err_disable = 0x0000008D; |
||||
ddr->err_sbe = 0x00ff0000; |
||||
#endif |
||||
asm("sync;isync"); |
||||
|
||||
udelay(500); |
||||
|
||||
#if defined (CONFIG_DDR_ECC) |
||||
/* Enable ECC checking */ |
||||
ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000); |
||||
#else |
||||
ddr->sdram_cfg_1 = CFG_DDR_CONTROL; |
||||
ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; |
||||
#endif |
||||
asm("sync; isync"); |
||||
|
||||
udelay(500); |
||||
#endif |
||||
return CFG_SDRAM_SIZE * 1024 * 1024; |
||||
} |
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */ |
||||
|
||||
|
||||
#if defined(CONFIG_PCI) |
||||
/*
|
||||
* Initialize PCI Devices, report devices found. |
||||
*/ |
||||
|
||||
#ifndef CONFIG_PCI_PNP |
||||
static struct pci_config_table pci_fsl86xxads_config_table[] = { |
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
||||
} }, |
||||
{ } |
||||
}; |
||||
#endif |
||||
|
||||
|
||||
static struct pci_controller hose = { |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table: pci_mpc86xxcts_config_table, |
||||
#endif |
||||
}; |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
void |
||||
pci_init_board(void) |
||||
{ |
||||
#ifdef CONFIG_PCI |
||||
extern void pci_mpc86xx_init(struct pci_controller *hose); |
||||
|
||||
pci_mpc86xx_init(&hose); |
||||
#endif /* CONFIG_PCI */ |
||||
} |
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) |
||||
void |
||||
ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
u32 *p; |
||||
int len; |
||||
|
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
p = ft_get_prop(blob, "/memory/reg", &len); |
||||
if (p != NULL) { |
||||
*p++ = cpu_to_be32(bd->bi_memstart); |
||||
*p = cpu_to_be32(bd->bi_memsize); |
||||
} |
||||
|
||||
} |
||||
#endif |
||||
|
||||
void |
||||
after_reloc(ulong dest_addr) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* now, jump to the main U-Boot board init code */ |
||||
board_init_r ((gd_t *)gd, dest_addr); |
||||
|
||||
/* NOTREACHED */ |
||||
} |
||||
|
||||
|
||||
|
@ -0,0 +1,186 @@ |
||||
/* |
||||
* MPC8641 HPCn Device Tree Source |
||||
* |
||||
* Copyright 2006 Freescale Semiconductor Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms of the GNU General Public License as published by the |
||||
* Free Software Foundation; either version 2 of the License, or (at your |
||||
* option) any later version. |
||||
*/ |
||||
|
||||
|
||||
/ { |
||||
model = "MPC8641HPCN"; |
||||
compatible = "mpc86xx"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
linux,phandle = <100>; |
||||
|
||||
cpus { |
||||
#cpus = <1>; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
linux,phandle = <200>; |
||||
|
||||
PowerPC,8641@0 { |
||||
device_type = "cpu"; |
||||
reg = <0>; |
||||
d-cache-line-size = <20>; // 32 bytes |
||||
i-cache-line-size = <20>; // 32 bytes |
||||
d-cache-size = <8000>; // L1, 32K |
||||
i-cache-size = <8000>; // L1, 32K |
||||
timebase-frequency = <0>; // 33 MHz, from uboot |
||||
bus-frequency = <0>; // 166 MHz |
||||
clock-frequency = <0>; // 825 MHz, from uboot |
||||
32-bit; |
||||
linux,phandle = <201>; |
||||
linux,boot-cpu; |
||||
}; |
||||
}; |
||||
|
||||
memory { |
||||
device_type = "memory"; |
||||
linux,phandle = <300>; |
||||
reg = <00000000 10000000>; // 256M at 0x0 |
||||
}; |
||||
|
||||
soc8641@f8000000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
#interrupt-cells = <2>; |
||||
device_type = "soc"; |
||||
ranges = <0 f8000000 00100000>; |
||||
reg = <f8000000 00100000>; // CCSRBAR 1M |
||||
bus-frequency = <0>; |
||||
|
||||
i2c@3000 { |
||||
device_type = "i2c"; |
||||
compatible = "fsl-i2c"; |
||||
reg = <3000 100>; |
||||
interrupts = <1b 0>; |
||||
interrupt-parent = <40000>; |
||||
dfsrr; |
||||
}; |
||||
|
||||
mdio@24520 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
device_type = "mdio"; |
||||
compatible = "gianfar"; |
||||
reg = <24520 20>; |
||||
linux,phandle = <24520>; |
||||
ethernet-phy@0 { |
||||
linux,phandle = <2452000>; |
||||
interrupt-parent = <40000>; |
||||
interrupts = <35 0>; |
||||
reg = <0>; |
||||
device_type = "ethernet-phy"; |
||||
}; |
||||
ethernet-phy@1 { |
||||
linux,phandle = <2452001>; |
||||
interrupt-parent = <40000>; |
||||
interrupts = <35 0>; |
||||
reg = <1>; |
||||
device_type = "ethernet-phy"; |
||||
}; |
||||
ethernet-phy@2 { |
||||
linux,phandle = <2452002>; |
||||
interrupt-parent = <40000>; |
||||
interrupts = <35 0>; |
||||
reg = <2>; |
||||
device_type = "ethernet-phy"; |
||||
}; |
||||
ethernet-phy@3 { |
||||
linux,phandle = <2452003>; |
||||
interrupt-parent = <40000>; |
||||
interrupts = <35 0>; |
||||
reg = <3>; |
||||
device_type = "ethernet-phy"; |
||||
}; |
||||
}; |
||||
|
||||
ethernet@24000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
device_type = "network"; |
||||
model = "TSEC"; |
||||
compatible = "gianfar"; |
||||
reg = <24000 1000>; |
||||
address = [ 00 E0 0C 00 73 00 ]; |
||||
interrupts = <d 3 e 3 12 3>; |
||||
interrupt-parent = <40000>; |
||||
phy-handle = <2452000>; |
||||
}; |
||||
|
||||
ethernet@25000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
device_type = "network"; |
||||
model = "TSEC"; |
||||
compatible = "gianfar"; |
||||
reg = <25000 1000>; |
||||
address = [ 00 E0 0C 00 73 01 ]; |
||||
interrupts = <13 3 14 3 18 3>; |
||||
interrupt-parent = <40000>; |
||||
phy-handle = <2452001>; |
||||
}; |
||||
|
||||
ethernet@26000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
device_type = "network"; |
||||
model = "TSEC"; |
||||
compatible = "gianfar"; |
||||
reg = <26000 1000>; |
||||
address = [ 00 E0 0C 00 02 FD ]; |
||||
interrupts = <F 3 10 3 11 3>; |
||||
interrupt-parent = <40000>; |
||||
phy-handle = <2452002>; |
||||
}; |
||||
|
||||
ethernet@27000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
device_type = "network"; |
||||
model = "TSEC"; |
||||
compatible = "gianfar"; |
||||
reg = <27000 1000>; |
||||
address = [ 00 E0 0C 00 03 FD ]; |
||||
interrupts = <15 3 16 3 17 3>; |
||||
interrupt-parent = <40000>; |
||||
phy-handle = <2452003>; |
||||
}; |
||||
serial@4500 { |
||||
device_type = "serial"; |
||||
compatible = "ns16550"; |
||||
reg = <4500 100>; // reg base, size |
||||
clock-frequency = <0>; // should we fill in in uboot? |
||||
interrupts = <1a 3>; |
||||
interrupt-parent = <40000>; |
||||
}; |
||||
|
||||
serial@4600 { |
||||
device_type = "serial"; |
||||
compatible = "ns16550"; |
||||
reg = <4600 100>; // reg base, size |
||||
clock-frequency = <0>; // should we fill in in uboot? |
||||
interrupts = <1a 3>; |
||||
interrupt-parent = <40000>; |
||||
}; |
||||
|
||||
pic@40000 { |
||||
linux,phandle = <40000>; |
||||
clock-frequency = <0>; |
||||
interrupt-controller; |
||||
#address-cells = <0>; |
||||
#interrupt-cells = <2>; |
||||
reg = <40000 40000>; |
||||
built-in; |
||||
compatible = "chrp,open-pic"; |
||||
device_type = "open-pic"; |
||||
big-endian; |
||||
}; |
||||
}; |
||||
}; |
||||
|
@ -0,0 +1,148 @@ |
||||
/* |
||||
* (C) Copyright 2004, Freescale, Inc. |
||||
* (C) Copyright 2002,2003, Motorola,Inc. |
||||
* Jeff Brown (jeffrey@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* .resetvec 0xFFF00100 : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFF70000 : |
||||
{ |
||||
cpu/mpc86xx/start.o (.bootpg) |
||||
board/mpc8641hpcn/init.o (.bootpg) |
||||
} = 0xffff |
||||
*/ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + 1024; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc86xx/start.o (.text) |
||||
board/mpc8641hpcn/init.o (.text) |
||||
cpu/mpc86xx/traps.o (.text) |
||||
cpu/mpc86xx/interrupts.o (.text) |
||||
cpu/mpc86xx/cpu_init.o (.text) |
||||
cpu/mpc86xx/cpu.o (.text) |
||||
cpu/mpc86xx/speed.o (.text) |
||||
cpu/mpc86xx/pci.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,48 @@ |
||||
#
|
||||
# (C) Copyright 2002,2003 Motorola Inc.
|
||||
# Xianghua Xiao,X.Xiao@motorola.com
|
||||
#
|
||||
# (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port)
|
||||
# Jeff Brown (Jeffrey@freescale.com)
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(CPU).a
|
||||
|
||||
START = start.o #resetvec.o
|
||||
ASOBJS = cache.o
|
||||
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
|
||||
pci.o i2c.o spd_sdram.o
|
||||
OBJS = $(COBJS)
|
||||
|
||||
all: .depend $(START) $(ASOBJS) $(LIB) |
||||
|
||||
$(LIB): $(OBJS) |
||||
$(AR) crv $@ $(ASOBJS) $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(START:.o=.S) $(ASOBJS:.o=.S) $(COBJS:.o=.c) |
||||
$(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(COBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,368 @@ |
||||
#include <config.h> |
||||
#include <mpc86xx.h> |
||||
#include <version.h> |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
|
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
#ifndef CACHE_LINE_SIZE |
||||
# define CACHE_LINE_SIZE L1_CACHE_BYTES |
||||
#endif |
||||
|
||||
#if CACHE_LINE_SIZE == 128 |
||||
#define LG_CACHE_LINE_SIZE 7 |
||||
#elif CACHE_LINE_SIZE == 32 |
||||
#define LG_CACHE_LINE_SIZE 5 |
||||
#elif CACHE_LINE_SIZE == 16 |
||||
#define LG_CACHE_LINE_SIZE 4 |
||||
#elif CACHE_LINE_SIZE == 8 |
||||
#define LG_CACHE_LINE_SIZE 3 |
||||
#else |
||||
# error "Invalid cache line size!" |
||||
#endif |
||||
|
||||
/* |
||||
* Most of this code is taken from 74xx_7xx/cache.S |
||||
* and then cleaned up a bit |
||||
*/ |
||||
|
||||
/* |
||||
* Invalidate L1 instruction cache. |
||||
*/ |
||||
_GLOBAL(invalidate_l1_instruction_cache) |
||||
/* use invalidate-all bit in HID0 */ |
||||
mfspr r3,HID0 |
||||
ori r3,r3,HID0_ICFI |
||||
mtspr HID0,r3 |
||||
isync |
||||
blr |
||||
|
||||
/* |
||||
* Invalidate L1 data cache. |
||||
*/ |
||||
_GLOBAL(invalidate_l1_data_cache) |
||||
mfspr r3,HID0 |
||||
ori r3,r3,HID0_DCFI |
||||
mtspr HID0,r3 |
||||
isync |
||||
blr |
||||
|
||||
/* |
||||
* Flush data cache. |
||||
*/ |
||||
_GLOBAL(flush_data_cache) |
||||
lis r3,0 |
||||
lis r5,CACHE_LINE_SIZE |
||||
flush: |
||||
cmp 0,1,r3,r5 |
||||
bge done |
||||
lwz r5,0(r3) |
||||
lis r5,CACHE_LINE_SIZE |
||||
addi r3,r3,0x4 |
||||
b flush |
||||
done: |
||||
blr |
||||
/* |
||||
* Write any modified data cache blocks out to memory |
||||
* and invalidate the corresponding instruction cache blocks. |
||||
* This is a no-op on the 601. |
||||
* |
||||
* flush_icache_range(unsigned long start, unsigned long stop) |
||||
*/ |
||||
_GLOBAL(flush_icache_range) |
||||
li r5,CACHE_LINE_SIZE-1 |
||||
andc r3,r3,r5 |
||||
subf r4,r3,r4 |
||||
add r4,r4,r5 |
||||
srwi. r4,r4,LG_CACHE_LINE_SIZE |
||||
beqlr |
||||
mtctr r4 |
||||
mr r6,r3 |
||||
1: dcbst 0,r3 |
||||
addi r3,r3,CACHE_LINE_SIZE |
||||
bdnz 1b |
||||
sync /* wait for dcbst's to get to ram */ |
||||
mtctr r4 |
||||
2: icbi 0,r6 |
||||
addi r6,r6,CACHE_LINE_SIZE |
||||
bdnz 2b |
||||
sync /* additional sync needed on g4 */ |
||||
isync |
||||
blr |
||||
/* |
||||
* Write any modified data cache blocks out to memory. |
||||
* Does not invalidate the corresponding cache lines (especially for |
||||
* any corresponding instruction cache). |
||||
* |
||||
* clean_dcache_range(unsigned long start, unsigned long stop) |
||||
*/ |
||||
_GLOBAL(clean_dcache_range) |
||||
li r5,CACHE_LINE_SIZE-1 |
||||
andc r3,r3,r5 /* align r3 down to cache line */ |
||||
subf r4,r3,r4 /* r4 = offset of stop from start of cache line */ |
||||
add r4,r4,r5 /* r4 += cache_line_size-1 */ |
||||
srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */ |
||||
beqlr /* if r4 == 0 return */ |
||||
mtctr r4 /* ctr = r4 */ |
||||
|
||||
sync |
||||
1: dcbst 0,r3 |
||||
addi r3,r3,CACHE_LINE_SIZE |
||||
bdnz 1b |
||||
sync /* wait for dcbst's to get to ram */ |
||||
blr |
||||
|
||||
/* |
||||
* Write any modified data cache blocks out to memory |
||||
* and invalidate the corresponding instruction cache blocks. |
||||
* |
||||
* flush_dcache_range(unsigned long start, unsigned long stop) |
||||
*/ |
||||
_GLOBAL(flush_dcache_range) |
||||
li r5,CACHE_LINE_SIZE-1 |
||||
andc r3,r3,r5 |
||||
subf r4,r3,r4 |
||||
add r4,r4,r5 |
||||
srwi. r4,r4,LG_CACHE_LINE_SIZE |
||||
beqlr |
||||
mtctr r4 |
||||
|
||||
sync |
||||
1: dcbf 0,r3 |
||||
addi r3,r3,CACHE_LINE_SIZE |
||||
bdnz 1b |
||||
sync /* wait for dcbf's to get to ram */ |
||||
blr |
||||
|
||||
/* |
||||
* Like above, but invalidate the D-cache. This is used by the 8xx |
||||
* to invalidate the cache so the PPC core doesn't get stale data |
||||
* from the CPM (no cache snooping here :-). |
||||
* |
||||
* invalidate_dcache_range(unsigned long start, unsigned long stop) |
||||
*/ |
||||
_GLOBAL(invalidate_dcache_range) |
||||
li r5,CACHE_LINE_SIZE-1 |
||||
andc r3,r3,r5 |
||||
subf r4,r3,r4 |
||||
add r4,r4,r5 |
||||
srwi. r4,r4,LG_CACHE_LINE_SIZE |
||||
beqlr |
||||
mtctr r4 |
||||
|
||||
sync |
||||
1: dcbi 0,r3 |
||||
addi r3,r3,CACHE_LINE_SIZE |
||||
bdnz 1b |
||||
sync /* wait for dcbi's to get to ram */ |
||||
blr |
||||
|
||||
/* |
||||
* Flush a particular page from the data cache to RAM. |
||||
* Note: this is necessary because the instruction cache does *not* |
||||
* snoop from the data cache. |
||||
* |
||||
* void __flush_page_to_ram(void *page) |
||||
*/ |
||||
_GLOBAL(__flush_page_to_ram) |
||||
rlwinm r3,r3,0,0,19 /* Get page base address */ |
||||
li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ |
||||
mtctr r4 |
||||
mr r6,r3 |
||||
0: dcbst 0,r3 /* Write line to ram */ |
||||
addi r3,r3,CACHE_LINE_SIZE |
||||
bdnz 0b |
||||
sync |
||||
mtctr r4 |
||||
1: icbi 0,r6 |
||||
addi r6,r6,CACHE_LINE_SIZE |
||||
bdnz 1b |
||||
sync |
||||
isync |
||||
blr |
||||
|
||||
/* |
||||
* Flush a particular page from the instruction cache. |
||||
* Note: this is necessary because the instruction cache does *not* |
||||
* snoop from the data cache. |
||||
* |
||||
* void __flush_icache_page(void *page) |
||||
*/ |
||||
_GLOBAL(__flush_icache_page) |
||||
li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ |
||||
mtctr r4 |
||||
1: icbi 0,r3 |
||||
addi r3,r3,CACHE_LINE_SIZE |
||||
bdnz 1b |
||||
sync |
||||
isync |
||||
blr |
||||
|
||||
/* |
||||
* Clear a page using the dcbz instruction, which doesn't cause any |
||||
* memory traffic (except to write out any cache lines which get |
||||
* displaced). This only works on cacheable memory. |
||||
*/ |
||||
_GLOBAL(clear_page) |
||||
li r0,4096/CACHE_LINE_SIZE |
||||
mtctr r0 |
||||
1: dcbz 0,r3 |
||||
addi r3,r3,CACHE_LINE_SIZE |
||||
bdnz 1b |
||||
blr |
||||
|
||||
/* |
||||
* Enable L1 Instruction cache |
||||
*/ |
||||
_GLOBAL(icache_enable) |
||||
mfspr r3, HID0 |
||||
li r5, HID0_ICFI|HID0_ILOCK |
||||
andc r3, r3, r5 |
||||
ori r3, r3, HID0_ICE |
||||
ori r5, r3, HID0_ICFI |
||||
mtspr HID0, r5 |
||||
mtspr HID0, r3 |
||||
isync |
||||
blr |
||||
|
||||
/* |
||||
* Disable L1 Instruction cache |
||||
*/ |
||||
_GLOBAL(icache_disable) |
||||
mfspr r3, HID0 |
||||
li r5, 0 |
||||
ori r5, r5, HID0_ICE |
||||
andc r3, r3, r5 |
||||
mtspr HID0, r3 |
||||
isync |
||||
blr |
||||
|
||||
/* |
||||
* Is instruction cache enabled? |
||||
*/ |
||||
_GLOBAL(icache_status) |
||||
mfspr r3, HID0 |
||||
andi. r3, r3, HID0_ICE |
||||
blr |
||||
|
||||
|
||||
_GLOBAL(l1dcache_enable) |
||||
mfspr r3, HID0 |
||||
li r5, HID0_DCFI|HID0_DLOCK |
||||
andc r3, r3, r5 |
||||
mtspr HID0, r3 /* no invalidate, unlock */ |
||||
ori r3, r3, HID0_DCE |
||||
ori r5, r3, HID0_DCFI |
||||
mtspr HID0, r5 /* enable + invalidate */ |
||||
mtspr HID0, r3 /* enable */ |
||||
sync |
||||
blr |
||||
|
||||
/* |
||||
* Enable data cache(s) - L1 and optionally L2 |
||||
* Calls l2cache_enable. LR saved in r5 |
||||
*/ |
||||
_GLOBAL(dcache_enable) |
||||
mfspr r3, HID0 |
||||
li r5, HID0_DCFI|HID0_DLOCK |
||||
andc r3, r3, r5 |
||||
mtspr HID0, r3 /* no invalidate, unlock */ |
||||
ori r3, r3, HID0_DCE |
||||
ori r5, r3, HID0_DCFI |
||||
mtspr HID0, r5 /* enable + invalidate */ |
||||
mtspr HID0, r3 /* enable */ |
||||
sync |
||||
#ifdef CFG_L2 |
||||
mflr r5 |
||||
bl l2cache_enable /* uses r3 and r4 */ |
||||
sync |
||||
mtlr r5 |
||||
#endif |
||||
blr |
||||
|
||||
|
||||
/* |
||||
* Disable data cache(s) - L1 and optionally L2 |
||||
* Calls flush_data_cache and l2cache_disable_no_flush. |
||||
* LR saved in r4 |
||||
*/ |
||||
_GLOBAL(dcache_disable) |
||||
mflr r4 /* save link register */ |
||||
bl flush_data_cache /* uses r3 and r5 */ |
||||
sync |
||||
mfspr r3, HID0 |
||||
li r5, HID0_DCFI|HID0_DLOCK |
||||
andc r3, r3, r5 |
||||
mtspr HID0, r3 /* no invalidate, unlock */ |
||||
li r5, HID0_DCE|HID0_DCFI |
||||
andc r3, r3, r5 /* no enable, no invalidate */ |
||||
mtspr HID0, r3 |
||||
sync |
||||
#ifdef CFG_L2 |
||||
bl l2cache_disable_no_flush /* uses r3 */ |
||||
#endif |
||||
mtlr r4 /* restore link register */ |
||||
blr |
||||
|
||||
/* |
||||
* Is data cache enabled? |
||||
*/ |
||||
_GLOBAL(dcache_status) |
||||
mfspr r3, HID0 |
||||
andi. r3, r3, HID0_DCE |
||||
blr |
||||
|
||||
/* |
||||
* Invalidate L2 cache using L2I and polling L2IP |
||||
*/ |
||||
_GLOBAL(l2cache_invalidate) |
||||
sync |
||||
oris r3, r3, L2CR_L2I@h
|
||||
sync |
||||
mtspr l2cr, r3 |
||||
sync |
||||
invl2: |
||||
mfspr r3, l2cr |
||||
andi. r3, r3, L2CR_L2IP |
||||
bne invl2 |
||||
/* turn off the global invalidate bit */ |
||||
mfspr r3, l2cr |
||||
rlwinm r3, r3, 0, 11, 9 |
||||
sync |
||||
mtspr l2cr, r3 |
||||
sync |
||||
blr |
||||
|
||||
/* |
||||
* Enable L2 cache |
||||
* Calls l2cache_invalidate. LR is saved in r4 |
||||
*/ |
||||
_GLOBAL(l2cache_enable) |
||||
mflr r4 /* save link register */ |
||||
bl l2cache_invalidate /* uses r3 */ |
||||
sync |
||||
lis r3, L2_ENABLE@h
|
||||
ori r3, r3, L2_ENABLE@l
|
||||
mtspr l2cr, r3 |
||||
isync |
||||
mtlr r4 /* restore link register */ |
||||
blr |
||||
|
||||
/* |
||||
* Disable L2 cache |
||||
* Calls flush_data_cache. LR is saved in r4 |
||||
*/ |
||||
_GLOBAL(l2cache_disable) |
||||
mflr r4 /* save link register */ |
||||
bl flush_data_cache /* uses r3 and r5 */ |
||||
sync |
||||
mtlr r4 /* restore link register */ |
||||
l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */ |
||||
lis r3, L2_INIT@h
|
||||
ori r3, r3, L2_INIT@l
|
||||
mtspr l2cr, r3 |
||||
isync |
||||
blr |
@ -0,0 +1,26 @@ |
||||
#
|
||||
# (C) Copyright 2004 Freescale Semiconductor.
|
||||
# Jeff Brown <jeffrey@freescale.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring
|
@ -0,0 +1,669 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor |
||||
* Jeff Brown (jeffrey@freescale.com) |
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <watchdog.h> |
||||
#include <command.h> |
||||
#include <asm/cache.h> |
||||
#include <mpc86xx.h> |
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) |
||||
#include <ft_build.h> |
||||
#endif |
||||
|
||||
|
||||
// SS: For debug only, remove after use
|
||||
|
||||
static __inline__ unsigned long get_dbat3u (void) |
||||
{ |
||||
unsigned long dbat3u; |
||||
asm volatile("mfspr %0, 542" : "=r" (dbat3u) :); |
||||
return dbat3u; |
||||
} |
||||
|
||||
static __inline__ unsigned long get_dbat3l (void) |
||||
{ |
||||
unsigned long dbat3l; |
||||
asm volatile("mfspr %0, 543" : "=r" (dbat3l) :); |
||||
return dbat3l; |
||||
} |
||||
|
||||
static __inline__ unsigned long get_msr (void) |
||||
{ |
||||
unsigned long msr; |
||||
asm volatile("mfmsr %0" : "=r" (msr) :); |
||||
return msr; |
||||
} |
||||
|
||||
extern unsigned long get_board_sys_clk(ulong dummy); |
||||
|
||||
int checkcpu (void) |
||||
{ |
||||
sys_info_t sysinfo; |
||||
uint pvr, svr; |
||||
uint ver; |
||||
uint major, minor; |
||||
uint lcrr; /* local bus clock ratio register */ |
||||
uint clkdiv; /* clock divider portion of lcrr */ |
||||
|
||||
puts("Freescale PowerPC\n"); |
||||
|
||||
pvr = get_pvr(); |
||||
ver = PVR_VER(pvr); |
||||
major = PVR_MAJ(pvr); |
||||
minor = PVR_MIN(pvr); |
||||
|
||||
puts ("CPU:\n"); |
||||
|
||||
printf(" Core: "); |
||||
|
||||
switch (ver) { |
||||
case PVR_VER(PVR_86xx): |
||||
puts("E600"); |
||||
break; |
||||
default: |
||||
puts("Unknown"); |
||||
break; |
||||
} |
||||
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); |
||||
|
||||
svr = get_svr(); |
||||
ver = SVR_VER(svr); |
||||
major = SVR_MAJ(svr); |
||||
minor = SVR_MIN(svr); |
||||
|
||||
puts(" System: "); |
||||
switch (ver) {
|
||||
case SVR_8641: |
||||
puts("8641"); |
||||
break; |
||||
case SVR_8641D: |
||||
puts("8641D"); |
||||
break; |
||||
default: |
||||
puts("Unknown"); |
||||
break; |
||||
} |
||||
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); |
||||
|
||||
get_sys_info(&sysinfo); |
||||
|
||||
puts(" Clocks: "); |
||||
printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); |
||||
printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); |
||||
printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); |
||||
|
||||
#if defined(CFG_LBC_LCRR) |
||||
lcrr = CFG_LBC_LCRR; |
||||
#else |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_lbc_t *lbc= &immap->im_lbc; |
||||
|
||||
lcrr = lbc->lcrr; |
||||
} |
||||
#endif |
||||
clkdiv = lcrr & 0x0f; |
||||
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { |
||||
printf("LBC:%4lu MHz\n", |
||||
sysinfo.freqSystemBus / 1000000 / clkdiv); |
||||
} else { |
||||
printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); |
||||
} |
||||
|
||||
printf(" L2: "); |
||||
if (get_l2cr() & 0x80000000) |
||||
printf("Enabled\n"); |
||||
else |
||||
printf("Disabled\n"); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */ |
||||
|
||||
static inline void |
||||
soft_restart(unsigned long addr) |
||||
{ |
||||
|
||||
#ifndef CONFIG_MPC8641HPCN |
||||
|
||||
/* SRR0 has system reset vector, SRR1 has default MSR value */ |
||||
/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ |
||||
|
||||
__asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); |
||||
__asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); |
||||
__asm__ __volatile__ ("mtspr 27, 4"); |
||||
__asm__ __volatile__ ("rfi"); |
||||
|
||||
#else /* CONFIG_MPC8641HPCN */ |
||||
out8(PIXIS_BASE+PIXIS_RST,0); |
||||
#endif /* !CONFIG_MPC8641HPCN */ |
||||
while(1); /* not reached */ |
||||
} |
||||
|
||||
|
||||
|
||||
#ifdef CONFIG_MPC8641HPCN |
||||
|
||||
int set_px_sysclk(ulong sysclk) |
||||
{ |
||||
u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux,tmp; |
||||
|
||||
/* Per table 27, page 58 of MPC8641HPCN spec*/ |
||||
switch(sysclk) |
||||
{ |
||||
case 33: |
||||
sysclk_s = 0x04; |
||||
sysclk_r = 0x04; |
||||
sysclk_v = 0x07; |
||||
sysclk_aux = 0x00; |
||||
break; |
||||
case 40: |
||||
sysclk_s = 0x01; |
||||
sysclk_r = 0x1F; |
||||
sysclk_v = 0x20; |
||||
sysclk_aux = 0x01; |
||||
break; |
||||
case 50: |
||||
sysclk_s = 0x01; |
||||
sysclk_r = 0x1F; |
||||
sysclk_v = 0x2A; |
||||
sysclk_aux = 0x02; |
||||
break; |
||||
case 66: |
||||
sysclk_s = 0x01; |
||||
sysclk_r = 0x04; |
||||
sysclk_v = 0x04; |
||||
sysclk_aux = 0x03; |
||||
break; |
||||
case 83: |
||||
sysclk_s = 0x01; |
||||
sysclk_r = 0x1F; |
||||
sysclk_v = 0x4B; |
||||
sysclk_aux = 0x04; |
||||
break; |
||||
case 100: |
||||
sysclk_s = 0x01; |
||||
sysclk_r = 0x1F; |
||||
sysclk_v = 0x5C; |
||||
sysclk_aux = 0x05; |
||||
break; |
||||
case 134: |
||||
sysclk_s = 0x06; |
||||
sysclk_r = 0x1F; |
||||
sysclk_v = 0x3B; |
||||
sysclk_aux = 0x06;
|
||||
break; |
||||
case 166: |
||||
sysclk_s = 0x06; |
||||
sysclk_r = 0x1F; |
||||
sysclk_v = 0x4B; |
||||
sysclk_aux = 0x07; |
||||
break; |
||||
default: |
||||
printf("Unsupported SYSCLK frequency.\n"); |
||||
return 0; |
||||
} |
||||
|
||||
vclkh = (sysclk_s << 5) | sysclk_r ; |
||||
vclkl = sysclk_v; |
||||
out8(PIXIS_BASE+PIXIS_VCLKH,vclkh); |
||||
out8(PIXIS_BASE+PIXIS_VCLKL,vclkl); |
||||
|
||||
out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux); |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
int set_px_mpxpll(ulong mpxpll) |
||||
{ |
||||
u8 tmp; |
||||
u8 val; |
||||
switch(mpxpll) |
||||
{ |
||||
case 2: |
||||
case 4: |
||||
case 6: |
||||
case 8: |
||||
case 10: |
||||
case 12: |
||||
case 14: |
||||
case 16: |
||||
val = (u8)mpxpll; |
||||
break; |
||||
default: |
||||
printf("Unsupported MPXPLL ratio.\n"); |
||||
return 0; |
||||
} |
||||
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VSPEED1); |
||||
tmp = (tmp & 0xF0) | (val & 0x0F); |
||||
out8(PIXIS_BASE+PIXIS_VSPEED1,tmp); |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
int set_px_corepll(ulong corepll) |
||||
{ |
||||
u8 tmp; |
||||
u8 val; |
||||
|
||||
switch((int)corepll) |
||||
{ |
||||
case 20: |
||||
val = 0x08; |
||||
break; |
||||
case 25: |
||||
val = 0x0C; |
||||
break; |
||||
case 30: |
||||
val = 0x10; |
||||
break; |
||||
case 35: |
||||
val = 0x1C; |
||||
break; |
||||
case 40: |
||||
val = 0x14; |
||||
break; |
||||
case 45: |
||||
val = 0x0E; |
||||
break; |
||||
default: |
||||
printf("Unsupported COREPLL ratio.\n"); |
||||
return 0; |
||||
} |
||||
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VSPEED0); |
||||
tmp = (tmp & 0xE0) | (val & 0x1F); |
||||
out8(PIXIS_BASE+PIXIS_VSPEED0,tmp); |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
void read_from_px_regs(int set) |
||||
{ |
||||
u8 tmp, mask = 0x1C; |
||||
tmp = in8(PIXIS_BASE+PIXIS_VCFGEN0); |
||||
if (set) |
||||
tmp = tmp | mask; |
||||
else |
||||
tmp = tmp & ~mask; |
||||
out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp);
|
||||
} |
||||
|
||||
void read_from_px_regs_altbank(int set) |
||||
{ |
||||
u8 tmp, mask = 0x04; |
||||
tmp = in8(PIXIS_BASE+PIXIS_VCFGEN1); |
||||
if (set) |
||||
tmp = tmp | mask; |
||||
else |
||||
tmp = tmp & ~mask; |
||||
out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp);
|
||||
} |
||||
|
||||
void set_altbank(void) |
||||
{ |
||||
u8 tmp; |
||||
tmp = in8(PIXIS_BASE+PIXIS_VBOOT); |
||||
tmp ^= 0x40; |
||||
out8(PIXIS_BASE+PIXIS_VBOOT,tmp); |
||||
} |
||||
|
||||
|
||||
void set_px_go(void) |
||||
{ |
||||
u8 tmp; |
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL); |
||||
tmp = tmp & 0x1E; |
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp); |
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL); |
||||
tmp = tmp | 0x01; |
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
|
||||
} |
||||
|
||||
void set_px_go_with_watchdog(void) |
||||
{ |
||||
u8 tmp; |
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL); |
||||
tmp = tmp & 0x1E; |
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp); |
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL); |
||||
tmp = tmp | 0x09; |
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
|
||||
} |
||||
|
||||
/* This function takes the non-integral cpu:mpx pll ratio
|
||||
* and converts it to an integer that can be used to assign |
||||
* FPGA register values. |
||||
* input: strptr i.e. argv[2] |
||||
*/ |
||||
|
||||
ulong strfractoint(uchar *strptr) |
||||
{ |
||||
int i,j,retval,intarr_len=0, decarr_len=0, mulconst, no_dec=0; |
||||
ulong intval =0, decval=0; |
||||
uchar intarr[3], decarr[3]; |
||||
|
||||
/* Assign the integer part to intarr[]
|
||||
* If there is no decimal point i.e. |
||||
* if the ratio is an integral value |
||||
* simply create the intarr. |
||||
*/ |
||||
i=0; |
||||
while(strptr[i] != 46) |
||||
{ |
||||
if(strptr[i] == 0) |
||||
{ |
||||
no_dec = 1; |
||||
break; /* Break from loop once the end of string is reached */ |
||||
} |
||||
|
||||
intarr[i] = strptr[i]; |
||||
i++; |
||||
} |
||||
|
||||
intarr_len = i; /* Assign length of integer part to intarr_len*/ |
||||
intarr[i] = '\0'; /* */ |
||||
|
||||
if(no_dec) |
||||
{ |
||||
mulconst=10; /* Currently needed only for single digit corepll ratios */ |
||||
decval = 0; |
||||
} |
||||
else |
||||
{ |
||||
j=0; |
||||
i++; /* Skipping the decimal point */ |
||||
while ((strptr[i] > 47) && (strptr[i] < 58)) |
||||
{ |
||||
decarr[j] = strptr[i]; |
||||
i++; |
||||
j++; |
||||
} |
||||
|
||||
decarr_len = j; |
||||
decarr[j] = '\0'; |
||||
|
||||
mulconst=1; |
||||
for(i=0; i<decarr_len;i++) |
||||
mulconst = mulconst*10; |
||||
decval = simple_strtoul(decarr,NULL,10);
|
||||
} |
||||
|
||||
intval = simple_strtoul(intarr,NULL,10); |
||||
intval = intval*mulconst; |
||||
|
||||
retval = intval+decval; |
||||
|
||||
return retval; |
||||
|
||||
} |
||||
|
||||
|
||||
#endif //CONFIG_MPC8641HPCN
|
||||
|
||||
|
||||
/* no generic way to do board reset. simply call soft_reset. */ |
||||
void |
||||
do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
char cmd; |
||||
ulong addr, val; |
||||
ulong corepll; |
||||
|
||||
|
||||
|
||||
#ifdef CFG_RESET_ADDRESS |
||||
addr = CFG_RESET_ADDRESS; |
||||
#else |
||||
/*
|
||||
* note: when CFG_MONITOR_BASE points to a RAM address, |
||||
* CFG_MONITOR_BASE - sizeof (ulong) is usually a valid |
||||
* address. Better pick an address known to be invalid on your |
||||
* system and assign it to CFG_RESET_ADDRESS. |
||||
*/ |
||||
addr = CFG_MONITOR_BASE - sizeof (ulong); |
||||
#endif |
||||
|
||||
#ifndef CONFIG_MPC8641HPCN |
||||
|
||||
/* flush and disable I/D cache */ |
||||
__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); |
||||
__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); |
||||
__asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); |
||||
__asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("mtspr 1008, 4"); |
||||
__asm__ __volatile__ ("isync"); |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("mtspr 1008, 5"); |
||||
__asm__ __volatile__ ("isync"); |
||||
__asm__ __volatile__ ("sync"); |
||||
|
||||
soft_restart(addr); |
||||
|
||||
#else /* CONFIG_MPC8641HPCN */ |
||||
|
||||
if(argc > 1) |
||||
{ |
||||
cmd = argv[1][1]; |
||||
switch(cmd) |
||||
{ |
||||
case 'f': /* reset with frequency changed */ |
||||
|
||||
if (argc < 5) |
||||
goto my_usage; |
||||
|
||||
read_from_px_regs(0); |
||||
|
||||
val = set_px_sysclk(simple_strtoul(argv[2],NULL,10)); |
||||
|
||||
corepll = strfractoint(argv[3]); |
||||
val = val + set_px_corepll(corepll); |
||||
val = val + set_px_mpxpll(simple_strtoul(argv[4],NULL,10)); |
||||
if(val == 3) |
||||
{ |
||||
printf("Setting registers VCFGEN0 and VCTL\n"); |
||||
read_from_px_regs(1); |
||||
printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); |
||||
set_px_go(); |
||||
} |
||||
else |
||||
goto my_usage; |
||||
|
||||
while(1); /* Not reached */ |
||||
|
||||
case 'l': |
||||
if(argv[2][1] == 'f') |
||||
{ |
||||
read_from_px_regs(0); |
||||
read_from_px_regs_altbank(0); |
||||
/* reset with frequency changed */ |
||||
val = set_px_sysclk(simple_strtoul(argv[3],NULL,10)); |
||||
|
||||
corepll = strfractoint(argv[4]); |
||||
val = val + set_px_corepll(corepll); |
||||
val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10)); |
||||
if(val == 3) |
||||
{ |
||||
printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); |
||||
set_altbank(); |
||||
read_from_px_regs(1); |
||||
read_from_px_regs_altbank(1); |
||||
printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); |
||||
set_px_go_with_watchdog(); |
||||
|
||||
} |
||||
else |
||||
goto my_usage; |
||||
|
||||
while(1); /* Not reached */ |
||||
} |
||||
else /* Reset from next bank without changing frequencies */ |
||||
{ |
||||
read_from_px_regs(0); |
||||
read_from_px_regs_altbank(0); |
||||
if(argc > 2) |
||||
goto my_usage; |
||||
printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); |
||||
set_altbank(); |
||||
read_from_px_regs_altbank(1); |
||||
printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); |
||||
set_px_go_with_watchdog(); |
||||
while(1); /* Not reached */ |
||||
} |
||||
|
||||
default: |
||||
goto my_usage; |
||||
} |
||||
my_usage: |
||||
printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"); |
||||
printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n"); |
||||
printf("For example: reset cf 40 2.5 10\n"); |
||||
printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); |
||||
return; |
||||
} |
||||
else |
||||
out8(PIXIS_BASE+PIXIS_RST,0); |
||||
|
||||
#endif /* !CONFIG_MPC8641HPCN */ |
||||
|
||||
while(1); /* not reached */ |
||||
} |
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* Get timebase clock frequency |
||||
*/ |
||||
unsigned long get_tbclk(void) |
||||
{ |
||||
sys_info_t sys_info; |
||||
|
||||
get_sys_info(&sys_info); |
||||
return ((sys_info.freqSystemBus + 3L) / 4L); |
||||
|
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
#if defined(CONFIG_WATCHDOG) |
||||
void |
||||
watchdog_reset(void) |
||||
{ |
||||
|
||||
} |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
#if defined(CONFIG_DDR_ECC) |
||||
void dma_init(void) { |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_dma_t *dma = &immap->im_dma; |
||||
|
||||
dma->satr0 = 0x00040000; |
||||
dma->datr0 = 0x00040000; |
||||
asm("sync; isync"); |
||||
return; |
||||
} |
||||
|
||||
uint dma_check(void) { |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_dma_t *dma = &immap->im_dma; |
||||
volatile uint status = dma->sr0; |
||||
|
||||
/* While the channel is busy, spin */ |
||||
while((status & 4) == 4) { |
||||
status = dma->sr0; |
||||
} |
||||
|
||||
if (status != 0) { |
||||
printf ("DMA Error: status = %x\n", status); |
||||
} |
||||
return status; |
||||
} |
||||
|
||||
int dma_xfer(void *dest, uint count, void *src) { |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_dma_t *dma = &immap->im_dma; |
||||
|
||||
dma->dar0 = (uint) dest; |
||||
dma->sar0 = (uint) src; |
||||
dma->bcr0 = count; |
||||
dma->mr0 = 0xf000004; |
||||
asm("sync;isync"); |
||||
dma->mr0 = 0xf000005; |
||||
asm("sync;isync"); |
||||
return dma_check(); |
||||
} |
||||
#endif /* CONFIG_DDR_ECC */ |
||||
|
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE |
||||
void ft_cpu_setup(void *blob, bd_t *bd) |
||||
{ |
||||
u32 *p; |
||||
ulong clock; |
||||
int len; |
||||
|
||||
clock = bd->bi_busfreq; |
||||
p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); |
||||
if (p != NULL) |
||||
*p = cpu_to_be32(clock); |
||||
|
||||
p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); |
||||
if (p != NULL) |
||||
*p = cpu_to_be32(clock); |
||||
|
||||
p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len); |
||||
if (p != NULL) |
||||
*p = cpu_to_be32(clock); |
||||
|
||||
#if defined(CONFIG_MPC86XX_TSEC1) |
||||
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len); |
||||
memcpy(p, bd->bi_enetaddr, 6); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_MPC86XX_TSEC2) |
||||
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len); |
||||
memcpy(p, bd->bi_enet1addr, 6); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_MPC86XX_TSEC3) |
||||
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/address", &len); |
||||
memcpy(p, bd->bi_enet2addr, 6); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_MPC86XX_TSEC4) |
||||
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/address", &len); |
||||
memcpy(p, bd->bi_enet3addr, 6); |
||||
#endif |
||||
|
||||
} |
||||
#endif |
@ -0,0 +1,134 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Jeff Brown (jeffrey@freescale.com) |
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* cpu_init.c - low level cpu init |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc86xx.h> |
||||
|
||||
/*
|
||||
* Breathe some life into the CPU... |
||||
* |
||||
* Set up the memory map |
||||
* initialize a bunch of registers |
||||
*/ |
||||
|
||||
void cpu_init_f (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_lbc_t *memctl = &immap->im_lbc; |
||||
//u8 val;
|
||||
|
||||
/* Pointer is writable since we allocated a register for it */ |
||||
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); |
||||
|
||||
/* Clear initial global data */ |
||||
memset ((void *) gd, 0, sizeof (gd_t)); |
||||
|
||||
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
|
||||
* addresses - these have to be modified later when FLASH size |
||||
* has been determined |
||||
*/ |
||||
|
||||
#if defined(CFG_OR0_REMAP) |
||||
memctl->or0 = CFG_OR0_REMAP; |
||||
#endif |
||||
#if defined(CFG_OR1_REMAP) |
||||
memctl->or1 = CFG_OR1_REMAP; |
||||
#endif |
||||
|
||||
/* now restrict to preliminary range */ |
||||
#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) |
||||
memctl->br0 = CFG_BR0_PRELIM; |
||||
memctl->or0 = CFG_OR0_PRELIM; |
||||
#endif |
||||
|
||||
#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) |
||||
memctl->or1 = CFG_OR1_PRELIM; |
||||
memctl->br1 = CFG_BR1_PRELIM; |
||||
#endif |
||||
|
||||
//#if !defined(CONFIG_MPC86xx)
|
||||
#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) |
||||
memctl->or2 = CFG_OR2_PRELIM; |
||||
memctl->br2 = CFG_BR2_PRELIM; |
||||
#endif |
||||
//#endif
|
||||
|
||||
#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) |
||||
memctl->or3 = CFG_OR3_PRELIM; |
||||
memctl->br3 = CFG_BR3_PRELIM; |
||||
#endif |
||||
|
||||
#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) |
||||
memctl->or4 = CFG_OR4_PRELIM; |
||||
memctl->br4 = CFG_BR4_PRELIM; |
||||
#endif |
||||
|
||||
#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) |
||||
memctl->or5 = CFG_OR5_PRELIM; |
||||
memctl->br5 = CFG_BR5_PRELIM; |
||||
#endif |
||||
|
||||
#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) |
||||
memctl->or6 = CFG_OR6_PRELIM; |
||||
memctl->br6 = CFG_BR6_PRELIM; |
||||
#endif |
||||
|
||||
#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) |
||||
memctl->or7 = CFG_OR7_PRELIM; |
||||
memctl->br7 = CFG_BR7_PRELIM; |
||||
#endif |
||||
|
||||
/* enable the timebase bit in HID0 */ |
||||
set_hid0(get_hid0() | 0x4000000); |
||||
|
||||
/* enable SYNCBE | ABE bits in HID1 */ |
||||
set_hid1(get_hid1() | 0x00000C00); |
||||
|
||||
/* Since the bats have been set up at this point and
|
||||
* the local bus registers have been initialized, we |
||||
* turn on the WDEN bit in PIXIS_VCTL |
||||
*/ |
||||
/* val = in8(PIXIS_BASE+PIXIS_VCTL); */ |
||||
/* Set the WDEN */ |
||||
/* val |= 0x08; */ |
||||
/* out8(PIXIS_BASE+PIXIS_VCTL,val); */ |
||||
} |
||||
|
||||
/*
|
||||
* initialize higher level parts of CPU like timers |
||||
*/ |
||||
int cpu_init_r (void) |
||||
{ |
||||
return (0); |
||||
} |
||||
|
||||
|
||||
|
||||
|
||||
|
@ -0,0 +1,273 @@ |
||||
/*
|
||||
* (C) Copyright 2003,Motorola Inc. |
||||
* Xianghua Xiao <x.xiao@motorola.com> |
||||
* Adapted for Motorola 85xx chip. |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Gleb Natapov <gnatapov@mrv.com> |
||||
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk |
||||
* |
||||
* Modified for MPC86xx by Jeff Brown (jeffrey@freescale.com) |
||||
* |
||||
* Hardware I2C driver for MPC107 PCI bridge. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/io.h> |
||||
|
||||
#ifdef CONFIG_HARD_I2C |
||||
#include <i2c.h> |
||||
|
||||
#define TIMEOUT (CFG_HZ/4) |
||||
|
||||
#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3100)) |
||||
|
||||
#define I2CADR &I2C_Addr[0] |
||||
#define I2CFDR &I2C_Addr[4] |
||||
#define I2CCCR &I2C_Addr[8] |
||||
#define I2CCSR &I2C_Addr[12] |
||||
#define I2CCDR &I2C_Addr[16] |
||||
#define I2CDFSRR &I2C_Addr[20] |
||||
|
||||
#define I2C_READ 1 |
||||
#define I2C_WRITE 0 |
||||
|
||||
void |
||||
i2c_init(int speed, int slaveadd) |
||||
{ |
||||
/* stop I2C controller */ |
||||
writeb(0x0, I2CCCR); |
||||
|
||||
/* set clock */ |
||||
writeb(0x3f, I2CFDR); |
||||
|
||||
/* set default filter */ |
||||
writeb(0x10,I2CDFSRR); |
||||
|
||||
/* write slave address */ |
||||
writeb(slaveadd, I2CADR); |
||||
|
||||
/* clear status register */ |
||||
writeb(0x0, I2CCSR); |
||||
|
||||
/* start I2C controller */ |
||||
writeb(MPC86xx_I2CCR_MEN, I2CCCR); |
||||
} |
||||
|
||||
static __inline__ int |
||||
i2c_wait4bus (void) |
||||
{ |
||||
ulong timeval = get_timer (0); |
||||
|
||||
// debug("I2C: Wait for bus\n");
|
||||
while (readb(I2CCSR) & MPC86xx_I2CSR_MBB) { |
||||
if (get_timer (timeval) > TIMEOUT) { |
||||
return -1; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static __inline__ int |
||||
i2c_wait (int write) |
||||
{ |
||||
u32 csr; |
||||
ulong timeval = get_timer (0); |
||||
|
||||
do { |
||||
csr = readb(I2CCSR); |
||||
|
||||
if (!(csr & MPC86xx_I2CSR_MIF)) |
||||
continue; |
||||
|
||||
writeb(0x0, I2CCSR); |
||||
|
||||
if (csr & MPC86xx_I2CSR_MAL) { |
||||
debug("i2c_wait: MAL\n"); |
||||
return -1; |
||||
} |
||||
|
||||
if (!(csr & MPC86xx_I2CSR_MCF)) { |
||||
debug("i2c_wait: unfinished\n"); |
||||
return -1; |
||||
} |
||||
|
||||
if (write == I2C_WRITE && (csr & MPC86xx_I2CSR_RXAK)) { |
||||
debug("i2c_wait: No RXACK\n"); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} while (get_timer (timeval) < TIMEOUT); |
||||
|
||||
debug("i2c_wait: timed out\n"); |
||||
return -1; |
||||
} |
||||
|
||||
static __inline__ int |
||||
i2c_write_addr (u8 dev, u8 dir, int rsta) |
||||
{ |
||||
// debug("I2C: Write Addr\n");
|
||||
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX | |
||||
(rsta?MPC86xx_I2CCR_RSTA:0), |
||||
I2CCCR); |
||||
|
||||
writeb((dev << 1) | dir, I2CCDR); |
||||
|
||||
if (i2c_wait (I2C_WRITE) < 0) |
||||
return 0; |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
static __inline__ int |
||||
__i2c_write (u8 *data, int length) |
||||
{ |
||||
int i; |
||||
// debug("I2C: __i2c_write\n");
|
||||
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX, |
||||
I2CCCR); |
||||
|
||||
for (i=0; i < length; i++) { |
||||
writeb(data[i], I2CCDR); |
||||
|
||||
if (i2c_wait (I2C_WRITE) < 0) |
||||
break; |
||||
} |
||||
|
||||
return i; |
||||
} |
||||
|
||||
static __inline__ int |
||||
__i2c_read (u8 *data, int length) |
||||
{ |
||||
int i; |
||||
|
||||
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | |
||||
((length == 1) ? MPC86xx_I2CCR_TXAK : 0), |
||||
I2CCCR); |
||||
|
||||
/* dummy read */ |
||||
readb(I2CCDR); |
||||
// debug("length = %d\n", length);
|
||||
|
||||
for (i=0; i < length; i++) { |
||||
if (i2c_wait (I2C_READ) < 0) |
||||
break; |
||||
|
||||
/* Generate ack on last next to last byte */ |
||||
if (i == length - 2) |
||||
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | |
||||
MPC86xx_I2CCR_TXAK, |
||||
I2CCCR); |
||||
|
||||
/* Generate stop on last byte */ |
||||
if (i == length - 1) |
||||
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_TXAK, I2CCCR); |
||||
|
||||
// debug("I2CCR = 0x%08x\n", readb(I2CCCR));
|
||||
data[i] = readb(I2CCDR); |
||||
// debug("data[i] = 0x%08x\n", data[i]);
|
||||
} |
||||
// debug("Returning i = %d\n", i);
|
||||
return i; |
||||
} |
||||
|
||||
int |
||||
i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) |
||||
{ |
||||
int i = 0; |
||||
u8 *a = (u8*)&addr; |
||||
|
||||
if (i2c_wait4bus () < 0) |
||||
goto exit; |
||||
|
||||
if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) |
||||
goto exit; |
||||
|
||||
if (__i2c_write (&a[4 - alen], alen) != alen) |
||||
goto exit; |
||||
|
||||
if (i2c_write_addr (dev, I2C_READ, 1) == 0) |
||||
goto exit; |
||||
|
||||
i = __i2c_read (data, length); |
||||
|
||||
exit: |
||||
writeb(MPC86xx_I2CCR_MEN, I2CCCR); |
||||
|
||||
return !(i == length); |
||||
} |
||||
|
||||
int |
||||
i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) |
||||
{ |
||||
int i = 0; |
||||
u8 *a = (u8*)&addr; |
||||
|
||||
if (i2c_wait4bus () < 0) |
||||
goto exit; |
||||
|
||||
if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) |
||||
goto exit; |
||||
|
||||
if (__i2c_write (&a[4 - alen], alen) != alen) |
||||
goto exit; |
||||
|
||||
i = __i2c_write (data, length); |
||||
|
||||
exit: |
||||
writeb(MPC86xx_I2CCR_MEN, I2CCCR); |
||||
|
||||
return !(i == length); |
||||
} |
||||
|
||||
int i2c_probe (uchar chip) |
||||
{ |
||||
int tmp; |
||||
|
||||
/*
|
||||
* Try to read the first location of the chip. The underlying |
||||
* driver doesn't appear to support sending just the chip address |
||||
* and looking for an <ACK> back. |
||||
*/ |
||||
udelay(10000); |
||||
|
||||
return i2c_read (chip, 0, 1, (char *)&tmp, 1); |
||||
} |
||||
|
||||
uchar i2c_reg_read (uchar i2c_addr, uchar reg) |
||||
{ |
||||
char buf[1]; |
||||
|
||||
i2c_read (i2c_addr, reg, 1, buf, 1); |
||||
|
||||
return (buf[0]); |
||||
} |
||||
|
||||
void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) |
||||
{ |
||||
i2c_write (i2c_addr, reg, 1, &val, 1); |
||||
} |
||||
|
||||
#endif /* CONFIG_HARD_I2C */ |
@ -0,0 +1,225 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2002 (440 port) |
||||
* Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com |
||||
* |
||||
* (C) Copyright 2003 Motorola Inc. (MPC85xx port) |
||||
* Xianghua Xiao (X.Xiao@motorola.com) |
||||
* |
||||
* (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port) |
||||
* Jeff Brown (Jeffrey@freescale.com) |
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc86xx.h> |
||||
#include <command.h> |
||||
#include <asm/processor.h> |
||||
#include <ppc_asm.tmpl> |
||||
|
||||
unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */ |
||||
|
||||
|
||||
unsigned long timestamp; |
||||
|
||||
static __inline__ unsigned long get_msr (void) |
||||
{ |
||||
unsigned long msr; |
||||
|
||||
asm volatile ("mfmsr %0":"=r" (msr):); |
||||
|
||||
return msr; |
||||
} |
||||
|
||||
static __inline__ void set_msr (unsigned long msr) |
||||
{ |
||||
asm volatile ("mtmsr %0"::"r" (msr)); |
||||
} |
||||
|
||||
static __inline__ unsigned long get_dec (void) |
||||
{ |
||||
unsigned long val; |
||||
|
||||
asm volatile ("mfdec %0":"=r" (val):); |
||||
|
||||
return val; |
||||
} |
||||
|
||||
|
||||
static __inline__ void set_dec (unsigned long val) |
||||
{ |
||||
if (val) |
||||
asm volatile ("mtdec %0"::"r" (val)); |
||||
} |
||||
|
||||
/* interrupt is not supported yet */ |
||||
int interrupt_init_cpu (unsigned *decrementer_count) |
||||
{ |
||||
return (0); |
||||
} |
||||
|
||||
|
||||
int interrupt_init (void) |
||||
{ |
||||
int ret; |
||||
|
||||
/* call cpu specific function from $(CPU)/interrupts.c */ |
||||
ret = interrupt_init_cpu (&decrementer_count); |
||||
|
||||
if (ret) |
||||
return ret; |
||||
|
||||
decrementer_count = get_tbclk()/CFG_HZ; |
||||
debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count); |
||||
|
||||
set_dec (decrementer_count); |
||||
|
||||
set_msr (get_msr () | MSR_EE); |
||||
|
||||
debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec()); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
void enable_interrupts (void) |
||||
{ |
||||
set_msr (get_msr () | MSR_EE); |
||||
} |
||||
|
||||
/* returns flag if MSR_EE was set before */ |
||||
int disable_interrupts (void) |
||||
{ |
||||
ulong msr = get_msr (); |
||||
|
||||
set_msr (msr & ~MSR_EE); |
||||
return ((msr & MSR_EE) != 0); |
||||
} |
||||
|
||||
|
||||
void increment_timestamp(void) |
||||
{ |
||||
timestamp++; |
||||
} |
||||
|
||||
/*
|
||||
* timer_interrupt - gets called when the decrementer overflows, |
||||
* with interrupts disabled. |
||||
* Trivial implementation - no need to be really accurate. |
||||
*/ |
||||
void |
||||
timer_interrupt_cpu (struct pt_regs *regs) |
||||
{ |
||||
/* nothing to do here */ |
||||
return; |
||||
} |
||||
|
||||
|
||||
void timer_interrupt (struct pt_regs *regs) |
||||
{ |
||||
/* call cpu specific function from $(CPU)/interrupts.c */ |
||||
timer_interrupt_cpu (regs); |
||||
|
||||
timestamp++; |
||||
|
||||
ppcDcbf(×tamp); |
||||
|
||||
/* Restore Decrementer Count */ |
||||
set_dec (decrementer_count); |
||||
|
||||
#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) |
||||
if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) |
||||
WATCHDOG_RESET (); |
||||
#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ |
||||
|
||||
#ifdef CONFIG_STATUS_LED |
||||
status_led_tick (timestamp); |
||||
#endif /* CONFIG_STATUS_LED */ |
||||
|
||||
#ifdef CONFIG_SHOW_ACTIVITY |
||||
board_show_activity (timestamp); |
||||
#endif /* CONFIG_SHOW_ACTIVITY */ |
||||
|
||||
|
||||
} |
||||
|
||||
void reset_timer (void) |
||||
{ |
||||
timestamp = 0; |
||||
} |
||||
|
||||
ulong get_timer (ulong base) |
||||
{
|
||||
return (timestamp - base); |
||||
} |
||||
|
||||
void set_timer (ulong t) |
||||
{ |
||||
timestamp = t; |
||||
} |
||||
|
||||
/*
|
||||
* Install and free a interrupt handler. Not implemented yet. |
||||
*/ |
||||
|
||||
void |
||||
irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) |
||||
{ |
||||
return; |
||||
} |
||||
|
||||
void |
||||
irq_free_handler(int vec) |
||||
{ |
||||
return; |
||||
} |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* |
||||
* irqinfo - print information about PCI devices,not implemented. |
||||
* |
||||
*/ |
||||
int |
||||
do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
printf ("\nInterrupt-unsupported:\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Handle external interrupts |
||||
*/ |
||||
void |
||||
external_interrupt(struct pt_regs *regs) |
||||
{ |
||||
puts("external_interrupt (oops!)\n"); |
||||
} |
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
@ -0,0 +1,196 @@ |
||||
/*
|
||||
* Copyright 2005 Freescale Semiconductor. |
||||
* Ed Swarthout (ed.swarthout@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* PEX Configuration space access support for MPC85xx PEX Bridge |
||||
*/ |
||||
#include <common.h> |
||||
#include <pci.h> |
||||
|
||||
|
||||
#if defined(CONFIG_PCI) |
||||
|
||||
void |
||||
pci_mpc86xx_init(struct pci_controller *hose) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; |
||||
volatile ccsr_pex_t *pex1 = &immap->im_pex1; |
||||
volatile ccsr_gur_t *gur = &immap->im_gur; |
||||
uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; |
||||
uint pex1_host = (host1_agent == 2) || (host1_agent == 3); |
||||
|
||||
u16 reg16, reg16_1, reg16_2, reg16_3; |
||||
u32 reg32, i; |
||||
|
||||
ulong addr, data; |
||||
|
||||
|
||||
uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); |
||||
uint devdisr = gur->devdisr; |
||||
uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; |
||||
|
||||
if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ |
||||
printf ("PCI-EXPRESS 1: Configured as %s \n", |
||||
pex1_agent ? "Agent" : "Host"); |
||||
printf (" Scanning PCI bus"); |
||||
debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); |
||||
if (pex1->pme_msg_det) { |
||||
pex1->pme_msg_det = 0xffffffff; |
||||
debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det); |
||||
} |
||||
debug ("\n"); |
||||
} |
||||
|
||||
|
||||
hose->first_busno = 0; |
||||
hose->last_busno = 0x7f; |
||||
|
||||
pci_set_region(hose->regions + 0, |
||||
CFG_PCI1_MEM_BASE, |
||||
CFG_PCI1_MEM_PHYS, |
||||
CFG_PCI1_MEM_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
pci_set_region(hose->regions + 1, |
||||
CFG_PCI1_IO_BASE, |
||||
CFG_PCI1_IO_PHYS, |
||||
CFG_PCI1_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
hose->region_count = 2; |
||||
|
||||
pci_setup_indirect(hose, |
||||
(CFG_IMMR+0x8000), |
||||
(CFG_IMMR+0x8004)); |
||||
|
||||
/*
|
||||
* Hose scan. |
||||
*/ |
||||
pci_register_hose(hose); |
||||
|
||||
//#define MPC8548_REV1_PEX12_ERRATA
|
||||
#ifdef MPC8548_REV1_PEX12_ERRATA |
||||
/* can only read/write 4 bytes */ |
||||
pci_read_config_dword (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®32); |
||||
printf("pex_mpc85xx_init: pex cr %2x %8x\n",PCI_VENDOR_ID, reg32); |
||||
|
||||
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®32); |
||||
reg32 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg32); |
||||
#else |
||||
pci_read_config_word (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®16); |
||||
debug("pex_mpc86xx_init: read %2x %4x\n",PCI_VENDOR_ID, reg16); |
||||
pci_read_config_word (PCI_BDF(0,0,0), PCI_DEVICE_ID, ®16); |
||||
debug("pex_mpc86xx_init: read %2x %4x\n",PCI_DEVICE_ID, reg16); |
||||
|
||||
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); |
||||
|
||||
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); |
||||
debug("pex_mpc86xx_init: read %2x %4x\n",PCI_COMMAND, reg16); |
||||
|
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
// pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
|
||||
// pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
|
||||
|
||||
pex1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; |
||||
pex1->powar1 = 0x8004401c; /* 512M MEM space */ |
||||
pex1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; |
||||
pex1->potear1 = 0x00000000; |
||||
|
||||
pex1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; |
||||
pex1->powar2 = 0x80088017; /* 16M IO space */ |
||||
pex1->potar2 = 0x00000000; |
||||
pex1->potear2 = 0x00000000; |
||||
|
||||
|
||||
if (!pex1->piwar1) { |
||||
pex1->pitar1 = 0x00000000; |
||||
pex1->piwbar1 = (0x80000000 >> 12 ) & 0x000fffff; |
||||
pex1->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
|
||||
* Snoop R/W, 2G */ |
||||
} |
||||
|
||||
pex1->pitar2 = 0x00000000; |
||||
pex1->piwbar2 = (0xe2000000 >> 12 ) & 0x000fffff; |
||||
pex1->piwar2 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
|
||||
|
||||
|
||||
|
||||
/* if (pex1_host) { */ |
||||
/* #ifdef MPC8548_REV1_PEX12_ERRATA */ |
||||
/* pci_write_config_dword (PCI_BDF(0,0,0), 0x18, 0x00ff0100); */ |
||||
/* #else */ |
||||
|
||||
|
||||
|
||||
*(u32 *)(0xf8008000)= 0x80000000; |
||||
debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); |
||||
|
||||
|
||||
pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20); |
||||
pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00); |
||||
pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F); |
||||
/* #endif */ |
||||
|
||||
|
||||
*(u32 *)(0xf8008000)= 0x80200000; |
||||
debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); |
||||
|
||||
*(u32 *)(0xf8008000)= 0x80200000; |
||||
debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); |
||||
|
||||
*(u32 *)(0xf8008000)= 0x80200000; |
||||
debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); |
||||
|
||||
|
||||
|
||||
hose->last_busno = pci_hose_scan(hose); |
||||
hose->last_busno = 0x21; |
||||
debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno); |
||||
debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno); |
||||
|
||||
|
||||
printf("....PCI scan & enumeration done\n"); |
||||
|
||||
/* *(u32 *)(0xf8008000)= 0x80000000 | (0x12 << 11); */ |
||||
/* printf("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); */ |
||||
|
||||
/* if (hose->last_busno < 1) { */ |
||||
/* hose->last_busno=1; /\*Hack*\/ */ |
||||
/* } else { */ |
||||
/* hose->last_busno = 0; */ |
||||
/* } */ |
||||
/*}*/ |
||||
/* pci_read_config_dword (PCI_BDF(1,0,0), 0x18, ®32); */ |
||||
/* printf("pex_mpc86xx_init: pex cr %2x %8x\n",0x18, reg32); */ |
||||
|
||||
|
||||
} |
||||
#endif /* CONFIG_PCI */ |
@ -0,0 +1,2 @@ |
||||
.section .resetvec,"ax" |
||||
b _start |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,248 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Jeff Brown (jeffrey@freescale.com) |
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
||||
* |
||||
* (C) Copyright 2000-2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc86xx.h> |
||||
#include <asm/processor.h> |
||||
|
||||
unsigned long get_board_sys_clk(ulong dummy); |
||||
unsigned long get_sysclk_from_px_regs(void); |
||||
|
||||
|
||||
/* --------------------------------------------------------------- */ |
||||
|
||||
void get_sys_info (sys_info_t * sysInfo) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_gur_t *gur = &immap->im_gur; |
||||
uint plat_ratio, e600_ratio; |
||||
|
||||
plat_ratio = (gur->porpllsr) & 0x0000003e; |
||||
plat_ratio >>= 1; |
||||
|
||||
switch(plat_ratio) { |
||||
case 0x0: |
||||
sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ; |
||||
break; |
||||
case 0x02: |
||||
case 0x03: |
||||
case 0x04: |
||||
case 0x05: |
||||
case 0x06: |
||||
case 0x08: |
||||
case 0x09: |
||||
case 0x0a: |
||||
case 0x0c: |
||||
case 0x10: |
||||
sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; |
||||
break; |
||||
default: |
||||
sysInfo->freqSystemBus = 0; |
||||
break; |
||||
} |
||||
|
||||
// printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", sysInfo->freqSystemBus, plat_ratio);
|
||||
e600_ratio = (gur->porpllsr) & 0x003f0000; |
||||
e600_ratio >>= 16; |
||||
switch(e600_ratio) {
|
||||
case 0x10: |
||||
sysInfo->freqProcessor = 2*sysInfo->freqSystemBus; |
||||
break; |
||||
case 0x19:
|
||||
sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2; |
||||
break; |
||||
case 0x20: |
||||
sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; |
||||
break; |
||||
case 0x39: |
||||
sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2; |
||||
break; |
||||
case 0x28: |
||||
sysInfo->freqProcessor = 4*sysInfo->freqSystemBus; |
||||
break; |
||||
case 0x1d: |
||||
sysInfo->freqProcessor = 9*sysInfo->freqSystemBus/2; |
||||
break; |
||||
default: |
||||
/* JB - Emulator workaround until real cop is plugged in */ |
||||
sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; |
||||
//sysInfo->freqProcessor = 3*sysInfo->freqSystemBus;
|
||||
break; |
||||
} |
||||
// printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", sysInfo->freqProcessor, e600_ratio);
|
||||
|
||||
} |
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* Measure CPU clock speed (core clock GCLK1, GCLK2) |
||||
* |
||||
* (Approx. GCLK frequency in Hz) |
||||
*/ |
||||
|
||||
int get_clocks (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
sys_info_t sys_info; |
||||
|
||||
get_sys_info (&sys_info); |
||||
gd->cpu_clk = sys_info.freqProcessor; |
||||
gd->bus_clk = sys_info.freqSystemBus; |
||||
|
||||
if(gd->cpu_clk != 0) return (0); |
||||
else return (1); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
/********************************************
|
||||
* get_bus_freq |
||||
* return system bus freq in Hz |
||||
*********************************************/ |
||||
ulong get_bus_freq (ulong dummy) |
||||
{ |
||||
ulong val; |
||||
|
||||
sys_info_t sys_info; |
||||
|
||||
get_sys_info (&sys_info); |
||||
val = sys_info.freqSystemBus; |
||||
|
||||
return val; |
||||
} |
||||
|
||||
unsigned long get_sysclk_from_px_regs() |
||||
{ |
||||
ulong val; |
||||
u8 vclkh,vclkl; |
||||
|
||||
vclkh = in8(PIXIS_BASE+PIXIS_VCLKH); |
||||
vclkl = in8(PIXIS_BASE+PIXIS_VCLKL); |
||||
|
||||
if((vclkh == 0x84) && (vclkl ==0x07)) |
||||
{ |
||||
val = 33000000; |
||||
} |
||||
if((vclkh == 0x3F) && (vclkl ==0x20)) |
||||
{ |
||||
val = 40000000; |
||||
} |
||||
if((vclkh == 0x3F) && (vclkl ==0x2A)) |
||||
{ |
||||
val = 50000000; |
||||
} |
||||
if((vclkh == 0x24) && (vclkl ==0x04)) |
||||
{ |
||||
val = 66000000; |
||||
} |
||||
if((vclkh == 0x3F) && (vclkl ==0x4B)) |
||||
{ |
||||
val = 83000000; |
||||
} |
||||
if((vclkh == 0x3F) && (vclkl ==0x5C)) |
||||
{ |
||||
val = 100000000; |
||||
} |
||||
if((vclkh == 0xDF) && (vclkl ==0x3B)) |
||||
{ |
||||
val = 134000000; |
||||
} |
||||
if((vclkh == 0xDF) && (vclkl ==0x4B)) |
||||
{ |
||||
val = 166000000; |
||||
} |
||||
|
||||
return val; |
||||
} |
||||
|
||||
/******* From MPC8641HPCN Design Workbook ************
|
||||
* |
||||
* get_board_sys_clk |
||||
* reads the FPGA on board for CONFIG_SYS_CLK_FREQ |
||||
* |
||||
********************************************************/ |
||||
|
||||
unsigned long get_board_sys_clk(ulong dummy) |
||||
{ |
||||
u8 i, go_bit, rd_clks; |
||||
ulong val; |
||||
|
||||
go_bit = in8(PIXIS_BASE+PIXIS_VCTL); |
||||
go_bit &= 0x01; |
||||
|
||||
rd_clks = in8(PIXIS_BASE+PIXIS_VCFGEN0); |
||||
rd_clks &= 0x1C; |
||||
|
||||
/* Only if both go bit and the SCLK bit in VCFGEN0 are set
|
||||
* should we be using the AUX register. Remember, we also set the |
||||
* GO bit to boot from the alternate bank on the on-board flash |
||||
*/ |
||||
|
||||
if(go_bit) |
||||
{ |
||||
if(rd_clks == 0x1c) |
||||
i = in8(PIXIS_BASE+PIXIS_AUX); |
||||
else |
||||
i = in8(PIXIS_BASE+PIXIS_SPD); |
||||
//val = get_sysclk_from_px_regs();
|
||||
} |
||||
else |
||||
i = in8(PIXIS_BASE+PIXIS_SPD); |
||||
|
||||
i &= 0x07; |
||||
|
||||
switch(i) |
||||
{ |
||||
case 0: |
||||
val = 33000000; |
||||
break; |
||||
case 1: |
||||
val = 40000000; |
||||
break; |
||||
case 2: |
||||
val = 50000000; |
||||
break; |
||||
case 3: |
||||
val = 66000000; |
||||
break; |
||||
case 4: |
||||
val = 83000000; |
||||
break; |
||||
case 5: |
||||
val = 100000000; |
||||
break; |
||||
case 6: |
||||
val = 134000000; |
||||
break; |
||||
case 7: |
||||
val = 166000000; |
||||
break; |
||||
} |
||||
|
||||
return val; |
||||
} |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,253 @@ |
||||
/*
|
||||
* linux/arch/ppc/kernel/traps.c |
||||
* |
||||
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
||||
* |
||||
* Modified by Cort Dougan (cort@cs.nmt.edu) |
||||
* and Paul Mackerras (paulus@cs.anu.edu.au) |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* This file handles the architecture-dependent parts of hardware exceptions |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/processor.h> |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
int (*debugger_exception_handler)(struct pt_regs *) = 0; |
||||
#endif |
||||
|
||||
/* Returns 0 if exception not found and fixup otherwise. */ |
||||
extern unsigned long search_exception_table(unsigned long); |
||||
|
||||
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) |
||||
|
||||
/*
|
||||
* Trap & Exception support |
||||
*/ |
||||
|
||||
void |
||||
print_backtrace(unsigned long *sp) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int cnt = 0; |
||||
unsigned long i; |
||||
|
||||
printf("Call backtrace: "); |
||||
while (sp) { |
||||
if ((uint)sp > END_OF_MEM) |
||||
break; |
||||
|
||||
i = sp[1]; |
||||
if (cnt++ % 7 == 0) |
||||
printf("\n"); |
||||
printf("%08lX ", i); |
||||
if (cnt > 32) break; |
||||
sp = (unsigned long *)*sp; |
||||
} |
||||
printf("\n"); |
||||
} |
||||
|
||||
void |
||||
show_regs(struct pt_regs * regs) |
||||
{ |
||||
int i; |
||||
|
||||
printf("NIP: %08lX XER: %08lX LR: %08lX REGS:" |
||||
" %p TRAP: %04lx DAR: %08lX\n", |
||||
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); |
||||
printf("MSR: %08lx EE: %01x PR: %01x FP:" |
||||
" %01x ME: %01x IR/DR: %01x%01x\n", |
||||
regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, |
||||
regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, |
||||
regs->msr&MSR_IR ? 1 : 0, |
||||
regs->msr&MSR_DR ? 1 : 0); |
||||
|
||||
printf("\n"); |
||||
for (i = 0; i < 32; i++) { |
||||
if ((i % 8) == 0) |
||||
{ |
||||
printf("GPR%02d: ", i); |
||||
} |
||||
|
||||
printf("%08lX ", regs->gpr[i]); |
||||
if ((i % 8) == 7) |
||||
{ |
||||
printf("\n"); |
||||
} |
||||
} |
||||
} |
||||
|
||||
|
||||
void |
||||
_exception(int signr, struct pt_regs *regs) |
||||
{ |
||||
show_regs(regs); |
||||
print_backtrace((unsigned long *)regs->gpr[1]); |
||||
panic("Exception in kernel pc %lx signal %d",regs->nip,signr); |
||||
} |
||||
|
||||
void |
||||
MachineCheckException(struct pt_regs *regs) |
||||
{ |
||||
unsigned long fixup; |
||||
|
||||
/* Probing PCI using config cycles cause this exception
|
||||
* when a device is not present. Catch it and return to |
||||
* the PCI exception handler. |
||||
*/ |
||||
if ((fixup = search_exception_table(regs->nip)) != 0) { |
||||
regs->nip = fixup; |
||||
return; |
||||
} |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
if (debugger_exception_handler && (*debugger_exception_handler)(regs)) |
||||
return; |
||||
#endif |
||||
|
||||
printf("Machine check in kernel mode.\n"); |
||||
printf("Caused by (from msr): "); |
||||
printf("regs %p ",regs); |
||||
switch( regs->msr & 0x000F0000) { |
||||
case (0x80000000>>12): |
||||
printf("Machine check signal - probably due to mm fault\n" |
||||
"with mmu off\n"); |
||||
break; |
||||
case (0x80000000>>13): |
||||
printf("Transfer error ack signal\n"); |
||||
break; |
||||
case (0x80000000>>14): |
||||
printf("Data parity signal\n"); |
||||
break; |
||||
case (0x80000000>>15): |
||||
printf("Address parity signal\n"); |
||||
break; |
||||
default: |
||||
printf("Unknown values in msr\n"); |
||||
} |
||||
show_regs(regs); |
||||
print_backtrace((unsigned long *)regs->gpr[1]); |
||||
panic("machine check"); |
||||
} |
||||
|
||||
void |
||||
AlignmentException(struct pt_regs *regs) |
||||
{ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
if (debugger_exception_handler && (*debugger_exception_handler)(regs)) |
||||
return; |
||||
#endif |
||||
show_regs(regs); |
||||
print_backtrace((unsigned long *)regs->gpr[1]); |
||||
panic("Alignment Exception"); |
||||
} |
||||
|
||||
void |
||||
ProgramCheckException(struct pt_regs *regs) |
||||
{ |
||||
unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; |
||||
int i, j; |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
if (debugger_exception_handler && (*debugger_exception_handler)(regs)) |
||||
return; |
||||
#endif |
||||
show_regs(regs); |
||||
|
||||
p = (unsigned char *) ((unsigned long)p & 0xFFFFFFE0); |
||||
p -= 32; |
||||
for (i = 0; i < 256; i+=16) { |
||||
printf("%08x: ", (unsigned int)p+i); |
||||
for (j = 0; j < 16; j++) { |
||||
printf("%02x ", p[i+j]); |
||||
} |
||||
printf("\n"); |
||||
} |
||||
|
||||
print_backtrace((unsigned long *)regs->gpr[1]); |
||||
panic("Program Check Exception"); |
||||
} |
||||
|
||||
void |
||||
SoftEmuException(struct pt_regs *regs) |
||||
{ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
if (debugger_exception_handler && (*debugger_exception_handler)(regs)) |
||||
return; |
||||
#endif |
||||
show_regs(regs); |
||||
print_backtrace((unsigned long *)regs->gpr[1]); |
||||
panic("Software Emulation Exception"); |
||||
} |
||||
|
||||
|
||||
void |
||||
UnknownException(struct pt_regs *regs) |
||||
{ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
if (debugger_exception_handler && (*debugger_exception_handler)(regs)) |
||||
return; |
||||
#endif |
||||
printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", |
||||
regs->nip, regs->msr, regs->trap); |
||||
_exception(0, regs); |
||||
} |
||||
|
||||
/* Probe an address by reading. If not present, return -1, otherwise
|
||||
* return 0. |
||||
*/ |
||||
int |
||||
addr_probe(uint *addr) |
||||
{ |
||||
#if 0 |
||||
int retval; |
||||
|
||||
__asm__ __volatile__( \
|
||||
"1: lwz %0,0(%1)\n" \
|
||||
" eieio\n" \
|
||||
" li %0,0\n" \
|
||||
"2:\n" \
|
||||
".section .fixup,\"ax\"\n" \
|
||||
"3: li %0,-1\n" \
|
||||
" b 2b\n" \
|
||||
".section __ex_table,\"a\"\n" \
|
||||
" .align 2\n" \
|
||||
" .long 1b,3b\n" \
|
||||
".text" \
|
||||
: "=r" (retval) : "r"(addr)); |
||||
|
||||
return (retval); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,629 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* mpc8641hpc3 board configuration file |
||||
* |
||||
* |
||||
* Make sure you change the MAC address and other network params first, |
||||
* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_MPC86xx 1 /* MPC86xx */ |
||||
#define CONFIG_MPC8641 1 /* MPC8641 specific */ |
||||
#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ |
||||
#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ |
||||
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
||||
#undef DEBUG |
||||
|
||||
//#define RUN_DIAG 1
|
||||
#ifdef RUN_DIAG |
||||
#define CFG_DIAG_ADDR 0xff800000 |
||||
#endif |
||||
#define CFG_RESET_ADDRESS 0xfff00100 |
||||
|
||||
//#define CONFIG_PCI
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
/*#define CONFIG_DDR_ECC */ /* only for ECC DDR module */ |
||||
/*#define CONFIG_DDR_DLL */ /* possible DLL fix needed */ |
||||
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ |
||||
|
||||
|
||||
#define CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
||||
|
||||
|
||||
#define CONFIG_ALTIVEC 1 |
||||
/*-----------------------------------------------------------------------
|
||||
* L2CR setup -- make sure this is right for your board! |
||||
*/ |
||||
|
||||
#define CFG_L2 |
||||
#define L2_INIT 0 |
||||
#define L2_ENABLE (L2CR_L2E) |
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ |
||||
//#define CONFIG_SYS_CLK_FREQ 33000000
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
||||
#endif |
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default. |
||||
*/ |
||||
/* JB - XXX - Are these available on 86xx? */ |
||||
#define CONFIG_BTB /* toggle branch predition */ |
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00200000 /* memtest region */ |
||||
#define CFG_MEMTEST_END 0x00400000 |
||||
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*/ |
||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
||||
#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ |
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
||||
|
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
||||
|
||||
#define MPC86xx_DDR_SDRAM_CLK_CNTL |
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
/*
|
||||
* Determine DDR configuration from I2C interface. |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
||||
|
||||
#else |
||||
/*
|
||||
* Manually set up DDR parameters |
||||
*/ |
||||
|
||||
/* DDR I */ |
||||
#if 1 |
||||
#define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ |
||||
|
||||
#define CFG_DDR_CS0_BNDS 0x0000000F |
||||
#define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ |
||||
#define CFG_DDR_EXT_REFRESH 0x00000000 |
||||
#define CFG_DDR_TIMING_0 0x00260802 |
||||
#define CFG_DDR_TIMING_1 0x39357322 |
||||
#define CFG_DDR_TIMING_2 0x14904cc8 |
||||
#define CFG_DDR_MODE_1 0x00480432 |
||||
#define CFG_DDR_MODE_2 0x00000000 |
||||
#define CFG_DDR_INTERVAL 0x06090100 |
||||
#define CFG_DDR_DATA_INIT 0xdeadbeef |
||||
#define CFG_DDR_CLK_CTRL 0x03800000 |
||||
#define CFG_DDR_OCD_CTRL 0x00000000 |
||||
#define CFG_DDR_OCD_STATUS 0x00000000 |
||||
#define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ |
||||
#define CFG_DDR_CONTROL2 0x04400000 |
||||
|
||||
//Not used in fixed_sdram function
|
||||
|
||||
#define CFG_DDR_MODE 0x00000022 |
||||
#define CFG_DDR_CS1_BNDS 0x00000000 |
||||
#define CFG_DDR_CS2_BNDS 0x00000FFF //Not done
|
||||
#define CFG_DDR_CS3_BNDS 0x00000FFF //Not done
|
||||
#define CFG_DDR_CS4_BNDS 0x00000FFF //Not done
|
||||
#define CFG_DDR_CS5_BNDS 0x00000FFF //Not done
|
||||
|
||||
|
||||
|
||||
#endif |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus |
||||
*/ |
||||
//#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
|
||||
//#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
|
||||
|
||||
/* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000
|
||||
* We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff |
||||
* map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. |
||||
* However, when u-boot comes up, the flash_init needs hard start addresses |
||||
* to build its info table. For user convenience, we have the flash addresses |
||||
* as fe800000 and ff800000. That way, when we do flash operations, u-boot |
||||
* knows where the flash is and the user can download u-boot code from promjet to |
||||
* fef00000 <- more intuitive than fe700000. Note that, on switching the boot |
||||
* location, fef00000 becomes fff00000. |
||||
*/ |
||||
#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ |
||||
#define CFG_FLASH_BASE2 0xff800000 |
||||
|
||||
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} |
||||
|
||||
|
||||
/*Sri: This looks like a good place to init all the Local Bus chip selects*/ |
||||
|
||||
#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ |
||||
#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ |
||||
|
||||
#define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ |
||||
#define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ |
||||
|
||||
#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ |
||||
#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ |
||||
|
||||
#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ |
||||
#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ |
||||
|
||||
#define PIXIS_BASE 0xf8100000 /* PIXIS registers*/ |
||||
#define PIXIS_ID 0x0 /* MPC8641HPCN Board ID at offset 0*/ |
||||
#define PIXIS_VER 0x1 /* MPC8641HPCN board version version at offset 1*/ |
||||
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2*/ |
||||
#define PIXIS_RST 0x4 /* PIXIS Reset Control register*/ |
||||
#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ |
||||
#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ |
||||
#define PIXIS_VCTL 0x10 /* VELA Control Register */ |
||||
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ |
||||
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ |
||||
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ |
||||
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
||||
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ |
||||
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ |
||||
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ |
||||
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ |
||||
//#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
/*#define CFG_HPCN_FLASH_CFI_DRIVER */ |
||||
#define CFG_FLASH_CFI |
||||
#define CFG_FLASH_EMPTY_INFO |
||||
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#if !defined(CFG_RAMBOOT) |
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
||||
#endif |
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ |
||||
|
||||
#define CONFIG_L1_INIT_RAM |
||||
#undef CFG_INIT_RAM_LOCK |
||||
#ifndef CFG_INIT_RAM_LOCK |
||||
#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ |
||||
#else |
||||
#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
||||
#endif |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/* Serial Port */ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_FLAT_TREE 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
|
||||
/* maximum size of the flat tree (8K) */ |
||||
#define OF_FLAT_TREE_MAX_SIZE 8192 |
||||
|
||||
#define OF_CPU "PowerPC,8641@0" |
||||
#define OF_SOC "soc8641@f8000000" |
||||
#define OF_TBCLK (bd->bi_busfreq / 8) |
||||
#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" |
||||
|
||||
#define CFG_64BIT_VSPRINTF 1 |
||||
#define CFG_64BIT_STRTOUL 1 |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
||||
|
||||
/* RapidIO MMU */ |
||||
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ |
||||
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE |
||||
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI1_MEM_BASE 0x80000000 |
||||
//#define CFG_PCI1_MEM_BASE 0xd0000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCI1_IO_BASE 0xe2000000 |
||||
//#define CFG_PCI1_IO_BASE 0xe0000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE |
||||
//#define CFG_PCI1_IO_BUS 0x00000000
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ |
||||
|
||||
/* For RTL8139 */ |
||||
#define _IO_BASE 0x00000000 |
||||
|
||||
#define CFG_PCI2_MEM_BASE 0xa0000000 |
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
||||
#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI2_IO_BASE 0xe3000000 |
||||
#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE |
||||
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ |
||||
|
||||
// #define CFG_PCI1_MEM_BASE 0x80000000
|
||||
// #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
// #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
// #define CFG_PCI1_IO_BASE 0xe2000000
|
||||
// #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
// #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
|
||||
|
||||
|
||||
#if defined(CONFIG_PCI) |
||||
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
|
||||
//#define CFG_SCSI_SCAN_BUS_REVERSE
|
||||
|
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#define CONFIG_RTL8139 |
||||
|
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_TULIP |
||||
|
||||
#if !defined(CONFIG_PCI_PNP) |
||||
#define PCI_ENET0_IOADDR 0xe0000000 |
||||
#define PCI_ENET0_MEMADDR 0xe0000000 |
||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
||||
#endif |
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
//#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
|
||||
#define CONFIG_MPC86XX_TSEC1 1 |
||||
#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" |
||||
#define CONFIG_MPC86XX_TSEC2 1 |
||||
#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" |
||||
#define CONFIG_MPC86XX_TSEC3 1 |
||||
#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" |
||||
#define CONFIG_MPC86XX_TSEC4 1 |
||||
#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" |
||||
|
||||
|
||||
#define TSEC1_PHY_ADDR 0 |
||||
#define TSEC2_PHY_ADDR 1 |
||||
#define TSEC3_PHY_ADDR 2 |
||||
#define TSEC4_PHY_ADDR 3 |
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
#define TSEC3_PHYIDX 0 |
||||
#define TSEC4_PHYIDX 0 |
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC1" |
||||
|
||||
#endif /* CONFIG_TSEC_ENET */ |
||||
|
||||
|
||||
/* BAT0 2G Cacheable, non-guarded
|
||||
* 0x0000_0000 2G DDR |
||||
*/ |
||||
//#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE)
|
||||
#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE) |
||||
#define CFG_DBAT0U (0x0 | BATU_BL_512M | BATU_VS | BATU_VP) |
||||
//#define CFG_IBAT0L CFG_DBAT0L
|
||||
//#define CFG_IBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT0L (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT0U CFG_DBAT0U |
||||
|
||||
/* BAT1 1G Cache-inhibited, guarded
|
||||
* 0x8000_0000 512M PCI-Express 1 Memory |
||||
* 0xa000_0000 512M PCI-Express 2 Memory |
||||
** SS - Changed it for operating from 0xd0000000 |
||||
*/ |
||||
#define CFG_DBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT1U CFG_DBAT1U |
||||
|
||||
/* BAT2 512M Cache-inhibited, guarded
|
||||
* 0xc000_0000 512M RapidIO Memory |
||||
*/ |
||||
#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT2U CFG_DBAT2U |
||||
|
||||
/* BAT3 4M Cache-inhibited, guarded
|
||||
* 0xf800_0000 4M CCSR |
||||
*/ |
||||
#define CFG_DBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT3U CFG_DBAT3U |
||||
|
||||
/* BAT4 32M Cache-inhibited, guarded
|
||||
* 0xe200_0000 16M PCI-Express 1 I/O |
||||
* 0xe300_0000 16M PCI-Express 2 I/0 |
||||
** SS - Note that this is at 0xe0000000 |
||||
*/ |
||||
#define CFG_DBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT4U CFG_DBAT4U |
||||
|
||||
/* BAT5 128K Cacheable, non-guarded
|
||||
* 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) |
||||
*/ |
||||
#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
||||
#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT5L CFG_DBAT5L |
||||
#define CFG_IBAT5U CFG_DBAT5U |
||||
|
||||
/* BAT6 32M Cache-inhibited, guarded
|
||||
* 0xfe00_0000 32M FLASH |
||||
*/ |
||||
#define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT6U CFG_DBAT6U |
||||
|
||||
|
||||
#define CFG_DBAT7L 0x00000000 |
||||
#define CFG_DBAT7U 0x00000000 |
||||
#define CFG_IBAT7L 0x00000000 |
||||
#define CFG_IBAT7U 0x00000000 |
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */ |
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#if defined(CFG_RAMBOOT) |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_PCI \
|
||||
| CFG_CMD_I2C) \
|
||||
& \
|
||||
~(CFG_CMD_ENV \
|
||||
| CFG_CMD_IMLS \
|
||||
| CFG_CMD_FLASH \
|
||||
| CFG_CMD_LOADS)) |
||||
#else |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_I2C) \
|
||||
& \
|
||||
~(CFG_CMD_ENV \
|
||||
| CFG_CMD_IMLS \
|
||||
| CFG_CMD_FLASH \
|
||||
| CFG_CMD_LOADS)) |
||||
#endif |
||||
#else |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PCI \
|
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_I2C) |
||||
#else |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_I2C) |
||||
#endif |
||||
#endif |
||||
|
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
||||
|
||||
/* Cache Configuration */ |
||||
#define CFG_DCACHE_SIZE 32768 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
/* The mac addresses for all ethernet interface */ |
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_ETHADDR 00:E0:0C:00:00:01 |
||||
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
||||
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
||||
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD |
||||
#endif |
||||
|
||||
#define CONFIG_HAS_ETH1 1 |
||||
#define CONFIG_HAS_ETH2 1 |
||||
#define CONFIG_HAS_ETH3 1 |
||||
|
||||
#define CONFIG_IPADDR 10.82.193.138 |
||||
|
||||
#define CONFIG_HOSTNAME unknown |
||||
#define CONFIG_ROOTPATH /opt/nfsroot |
||||
#define CONFIG_BOOTFILE uImage |
||||
|
||||
#define CONFIG_SERVERIP 10.82.193.104 |
||||
#define CONFIG_GATEWAYIP 10.82.193.254 |
||||
#define CONFIG_NETMASK 255.255.252.0 |
||||
|
||||
#define CONFIG_LOADADDR 1000000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
||||
//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=400000\0" \
|
||||
"ramdiskfile=your.ramdisk.u-boot\0" \
|
||||
"pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \
|
||||
"pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \
|
||||
"pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \
|
||||
"pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \
|
||||
"pex=run pexstat; run pex1; run pexd\0" \
|
||||
"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
|
||||
"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
|
||||
"maxcpus=2" |
||||
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"bootm $loadaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,119 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Jeffrey Brown (jeffrey@freescale.com) |
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
||||
*/ |
||||
|
||||
#ifndef __MPC86xx_H__ |
||||
#define __MPC86xx_H__ |
||||
|
||||
#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ |
||||
|
||||
/*----------------------------------------------------------------
|
||||
* l2cr values. Look in config_<BOARD>.h for the actual setup |
||||
*/ |
||||
#define l2cr 1017 |
||||
|
||||
#define L2CR_L2E 0x80000000 /* bit 0 - enable */ |
||||
#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ |
||||
#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ |
||||
#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ |
||||
#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */ |
||||
#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */ |
||||
#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ |
||||
#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ |
||||
|
||||
/*----------------------------------------------------------------
|
||||
* BAT settings. Look in config_<BOARD>.h for the actual setup |
||||
*/ |
||||
|
||||
#define BATU_BL_128K 0x00000000 |
||||
#define BATU_BL_256K 0x00000004 |
||||
#define BATU_BL_512K 0x0000000c |
||||
#define BATU_BL_1M 0x0000001c |
||||
#define BATU_BL_2M 0x0000003c |
||||
#define BATU_BL_4M 0x0000007c |
||||
#define BATU_BL_8M 0x000000fc |
||||
#define BATU_BL_16M 0x000001fc |
||||
#define BATU_BL_32M 0x000003fc |
||||
#define BATU_BL_64M 0x000007fc |
||||
#define BATU_BL_128M 0x00000ffc |
||||
#define BATU_BL_256M 0x00001ffc |
||||
#define BATU_BL_512M 0x00003ffc |
||||
#define BATU_BL_1G 0x00007ffc |
||||
#define BATU_BL_2G 0x0000fffc |
||||
#define BATU_BL_4G 0x0001fffc |
||||
|
||||
#define BATU_VS 0x00000002 |
||||
#define BATU_VP 0x00000001 |
||||
#define BATU_INVALID 0x00000000 |
||||
|
||||
#define BATL_WRITETHROUGH 0x00000040 |
||||
#define BATL_CACHEINHIBIT 0x00000020 |
||||
#define BATL_MEMCOHERENCE 0x00000010 |
||||
#define BATL_GUARDEDSTORAGE 0x00000008 |
||||
#define BATL_NO_ACCESS 0x00000000 |
||||
|
||||
#define BATL_PP_MSK 0x00000003 |
||||
#define BATL_PP_00 0x00000000 /* No access */ |
||||
#define BATL_PP_01 0x00000001 /* Read-only */ |
||||
#define BATL_PP_10 0x00000002 /* Read-write */ |
||||
#define BATL_PP_11 0x00000003 |
||||
|
||||
#define BATL_PP_NO_ACCESS BATL_PP_00 |
||||
#define BATL_PP_RO BATL_PP_01 |
||||
#define BATL_PP_RW BATL_PP_10 |
||||
|
||||
#define HID0_XBSEN 0x00000100 |
||||
#define HID0_HIGH_BAT_EN 0x00800000 |
||||
#define HID0_XAEN 0x00020000 |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
|
||||
typedef struct |
||||
{ |
||||
unsigned long freqProcessor; |
||||
unsigned long freqSystemBus; |
||||
} MPC86xx_SYS_INFO; |
||||
|
||||
#define l1icache_enable icache_enable |
||||
|
||||
void l2cache_enable(void); |
||||
void l1dcache_enable(void); |
||||
|
||||
static __inline__ unsigned long get_hid0 (void) |
||||
{ |
||||
unsigned long hid0; |
||||
asm volatile("mfspr %0, 1008" : "=r" (hid0) :); |
||||
return hid0; |
||||
} |
||||
|
||||
static __inline__ unsigned long get_hid1 (void) |
||||
{ |
||||
unsigned long hid1; |
||||
asm volatile("mfspr %0, 1009" : "=r" (hid1) :); |
||||
return hid1; |
||||
} |
||||
|
||||
static __inline__ void set_hid0 (unsigned long hid0) |
||||
{ |
||||
asm volatile("mtspr 1008, %0" : : "r" (hid0)); |
||||
} |
||||
|
||||
static __inline__ void set_hid1 (unsigned long hid1) |
||||
{ |
||||
asm volatile("mtspr 1009, %0" : : "r" (hid1)); |
||||
} |
||||
|
||||
|
||||
static __inline__ unsigned long get_l2cr (void) |
||||
{ |
||||
unsigned long l2cr_val; |
||||
asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :); |
||||
return l2cr_val; |
||||
} |
||||
|
||||
#endif /* _ASMLANGUAGE */ |
||||
#endif /* __MPC86xx_H__ */ |
||||
|
||||
|
Loading…
Reference in new issue