@ -46,7 +46,7 @@ extern void nand_wait_ready(struct mtd_info *mtd);
* is supported now . If you add a chip with bigger oobsize / page
* adjust this accordingly .
*/
# define NAND_MAX_OOBSIZE 57 6
# define NAND_MAX_OOBSIZE 640
# define NAND_MAX_PAGESIZE 8192
/*
@ -82,6 +82,8 @@ extern void nand_wait_ready(struct mtd_info *mtd);
# define NAND_CMD_READID 0x90
# define NAND_CMD_ERASE2 0xd0
# define NAND_CMD_PARAM 0xec
# define NAND_CMD_GET_FEATURES 0xee
# define NAND_CMD_SET_FEATURES 0xef
# define NAND_CMD_RESET 0xff
# define NAND_CMD_LOCK 0x2a
@ -142,7 +144,7 @@ typedef enum {
# define NAND_ECC_READ 0
/* Reset Hardware ECC for write */
# define NAND_ECC_WRITE 1
/* Enable Hardware ECC before syndrom is read back from flash */
/* Enable Hardware ECC before syndrome is read back from flash */
# define NAND_ECC_READSYN 2
/* Bit mask for flags passed to do_nand_read_ecc */
@ -153,9 +155,7 @@ typedef enum {
* Option constants for bizarre disfunctionality and real
* features .
*/
/* Chip can not auto increment pages */
# define NAND_NO_AUTOINCR 0x00000001
/* Buswitdh is 16 bit */
/* Buswidth is 16 bit */
# define NAND_BUSWIDTH_16 0x00000002
/* Device supports partial programming without padding */
# define NAND_NO_PADDING 0x00000004
@ -179,12 +179,6 @@ typedef enum {
* This happens with the Renesas AG - AND chips , possibly others .
*/
# define BBT_AUTO_REFRESH 0x00000080
/*
* Chip does not require ready check on read . true
* for all large page devices , as they do not support
* autoincrement .
*/
# define NAND_NO_READRDY 0x00000100
/* Chip does not allow subpage writes */
# define NAND_NO_SUBPAGE_WRITE 0x00000200
@ -202,34 +196,21 @@ typedef enum {
( NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK )
/* Macros to identify the above */
# define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
# define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
# define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
# define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
# define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
/* Non chip related options */
/*
* Use a flash based bad block table . OOB identifier is saved in OOB area .
* This option is passed to the default bad block table function .
*/
# define NAND_USE_FLASH_BBT 0x00010000
/* This option skips the bbt scan during initialization. */
# define NAND_SKIP_BBTSCAN 0x0002 0000
# define NAND_SKIP_BBTSCAN 0x00010000
/*
* This option is defined if the board driver allocates its own buffers
* ( e . g . because it needs them DMA - coherent ) .
*/
# define NAND_OWN_BUFFERS 0x0004 0000
# define NAND_OWN_BUFFERS 0x0002 0000
/* Chip may not exist, so silence any errors in scan */
# define NAND_SCAN_SILENT_NODEV 0x00080000
/*
* If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch
* the OOB area .
*/
# define NAND_USE_FLASH_BBT_NO_OOB 0x00800000
/* Create an empty BBT with no vendor information if the BBT is available */
# define NAND_CREATE_EMPTY_BBT 0x01000000
# define NAND_SCAN_SILENT_NODEV 0x00040000
/* Options set by nand scan */
/* bbt has already been read */
@ -244,6 +225,21 @@ typedef enum {
/* Keep gcc happy */
struct nand_chip ;
/* ONFI timing mode, used in both asynchronous and synchronous mode */
# define ONFI_TIMING_MODE_0 (1 << 0)
# define ONFI_TIMING_MODE_1 (1 << 1)
# define ONFI_TIMING_MODE_2 (1 << 2)
# define ONFI_TIMING_MODE_3 (1 << 3)
# define ONFI_TIMING_MODE_4 (1 << 4)
# define ONFI_TIMING_MODE_5 (1 << 5)
# define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
/* ONFI feature address */
# define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
/* ONFI subfeature parameters length */
# define ONFI_SUBFEATURE_PARAM_LEN 4
struct nand_onfi_params {
/* rev info and features block */
/* 'O' 'N' 'F' 'I' */
@ -326,27 +322,32 @@ struct nand_hw_control {
} ;
/**
* struct nand_ecc_ctrl - Control structure for ecc
* @ mode : ecc mode
* @ steps : number of ecc steps per page
* @ size : data bytes per ecc step
* @ bytes : ecc bytes per step
* @ total : total number of ecc bytes per page
* @ prepad : padding information for syndrome based ecc generators
* @ postpad : padding information for syndrome based ecc generators
* struct nand_ecc_ctrl - Control structure for ECC
* @ mode : ECC mode
* @ steps : number of ECC steps per page
* @ size : data bytes per ECC step
* @ bytes : ECC bytes per step
* @ strength : max number of correctible bits per ECC step
* @ total : total number of ECC bytes per page
* @ prepad : padding information for syndrome based ECC generators
* @ postpad : padding information for syndrome based ECC generators
* @ layout : ECC layout control struct pointer
* @ priv : pointer to private ecc control data
* @ hwctl : function to control hardware ecc generator . Must only
* @ priv : pointer to private ECC control data
* @ hwctl : function to control hardware ECC generator . Must only
* be provided if an hardware ECC is available
* @ calculate : function for ecc calculation or readback from ecc hardware
* @ correct : function for ecc correction , matching to ecc generator ( sw / hw )
* @ calculate : function for ECC calculation or readback from ECC hardware
* @ correct : function for ECC correction , matching to ECC generator ( sw / hw )
* @ read_page_raw : function to read a raw page without ECC
* @ write_page_raw : function to write a raw page without ECC
* @ read_page : function to read a page according to the ecc generator
* requirements .
* @ read_subpage : function to read parts of the page covered by ECC .
* @ write_page : function to write a page according to the ecc generator
* @ read_page : function to read a page according to the ECC generator
* requirements ; returns maximum number of bitflips corrected in
* any single ECC step , 0 if bitflips uncorrectable , - EIO hw error
* @ read_subpage : function to read parts of the page covered by ECC ;
* returns same as read_page ( )
* @ write_page : function to write a page according to the ECC generator
* requirements .
* @ write_oob_raw : function to write chip OOB data without ECC
* @ read_oob_raw : function to read chip OOB data without ECC
* @ read_oob : function to read chip OOB data
* @ write_oob : function to write chip OOB data
*/
@ -356,6 +357,7 @@ struct nand_ecc_ctrl {
int size ;
int bytes ;
int total ;
int strength ;
int prepad ;
int postpad ;
struct nand_ecclayout * layout ;
@ -366,25 +368,28 @@ struct nand_ecc_ctrl {
int ( * correct ) ( struct mtd_info * mtd , uint8_t * dat , uint8_t * read_ecc ,
uint8_t * calc_ecc ) ;
int ( * read_page_raw ) ( struct mtd_info * mtd , struct nand_chip * chip ,
uint8_t * buf , int page ) ;
void ( * write_page_raw ) ( struct mtd_info * mtd , struct nand_chip * chip ,
const uint8_t * buf ) ;
uint8_t * buf , int oob_required , int page ) ;
int ( * write_page_raw ) ( struct mtd_info * mtd , struct nand_chip * chip ,
const uint8_t * buf , int oob_required ) ;
int ( * read_page ) ( struct mtd_info * mtd , struct nand_chip * chip ,
uint8_t * buf , int page ) ;
uint8_t * buf , int oob_required , int page ) ;
int ( * read_subpage ) ( struct mtd_info * mtd , struct nand_chip * chip ,
uint32_t offs , uint32_t len , uint8_t * buf ) ;
void ( * write_page ) ( struct mtd_info * mtd , struct nand_chip * chip ,
const uint8_t * buf ) ;
int ( * read_oob ) ( struct mtd_info * mtd , struct nand_chip * chip , int page ,
int sndcmd ) ;
int ( * write_page ) ( struct mtd_info * mtd , struct nand_chip * chip ,
const uint8_t * buf , int oob_required ) ;
int ( * write_oob_raw ) ( struct mtd_info * mtd , struct nand_chip * chip ,
int page ) ;
int ( * read_oob_raw ) ( struct mtd_info * mtd , struct nand_chip * chip ,
int page ) ;
int ( * read_oob ) ( struct mtd_info * mtd , struct nand_chip * chip , int page ) ;
int ( * write_oob ) ( struct mtd_info * mtd , struct nand_chip * chip ,
int page ) ;
} ;
/**
* struct nand_buffers - buffer structure for read / write
* @ ecccalc : buffer for calculated ecc
* @ ecccode : buffer for ecc read from flash
* @ ecccalc : buffer for calculated ECC
* @ ecccode : buffer for ECC read from flash
* @ databuf : buffer for data - dynamically sized
*
* Do not change the order of buffers . databuf and oobrbuf must be in
@ -418,7 +423,7 @@ struct nand_buffers {
* mtd - > oobsize , mtd - > writesize and so on .
* @ id_data contains the 8 bytes values of NAND_CMD_READID .
* Return with the bus width .
* @ dev_ready : [ BOARDSPECIFIC ] hardwarespecific function for accesing
* @ dev_ready : [ BOARDSPECIFIC ] hardwarespecific function for access ing
* device ready / busy line . If set to NULL no access to
* ready / busy is available and the ready / busy information
* is read from the chip status register .
@ -426,17 +431,17 @@ struct nand_buffers {
* commands to the chip .
* @ waitfunc : [ REPLACEABLE ] hardwarespecific function for wait on
* ready .
* @ ecc : [ BOARDSPECIFIC ] ecc control c tructure
* @ ecc : [ BOARDSPECIFIC ] ECC control s tructure
* @ buffers : buffer structure for read / write
* @ hwcontrol : platform - specific hardware control structure
* @ ops : oob operation operands
* @ erase_cmd : [ INTERN ] erase command write function , selectable due
* to AND support .
* @ scan_bbt : [ REPLACEABLE ] function to scan bad block table
* @ chip_delay : [ BOARDSPECIFIC ] chip dependent delay for transferring
* data from array to read regs ( tR ) .
* @ state : [ INTERN ] the current state of the NAND device
* @ oob_poi : poison value buffer
* @ oob_poi : " poison value buffer, " used for laying out OOB data
* before writing
* @ page_shift : [ INTERN ] number of address bits in a page ( column
* address bits ) .
* @ phys_erase_shift : [ INTERN ] number of address bits in a physical eraseblock
@ -445,10 +450,14 @@ struct nand_buffers {
* @ options : [ BOARDSPECIFIC ] various chip options . They can partly
* be set to inform nand_scan about special functionality .
* See the defines for further explanation .
* @ bbt_options : [ INTERN ] bad block specific options . All options used
* here must come from bbm . h . By default , these options
* will be copied to the appropriate nand_bbt_descr ' s .
* @ badblockpos : [ INTERN ] position of the bad block marker in the oob
* area .
* @ badblockbits : [ INTERN ] number of bits to left - shift the bad block
* number
* @ badblockbits : [ INTERN ] minimum number of set bits in a good block ' s
* bad block marker position ; i . e . , BBM = = 11110111 b is
* not bad when badblockbits = = 7
* @ cellinfo : [ INTERN ] MLC / multichip data from chip ident
* @ numchips : [ INTERN ] number of physical chips
* @ chipsize : [ INTERN ] the size of one chip for multichip arrays
@ -460,7 +469,9 @@ struct nand_buffers {
* non 0 if ONFI supported .
* @ onfi_params : [ INTERN ] holds the ONFI page parameter when ONFI is
* supported , 0 otherwise .
* @ ecclayout : [ REPLACEABLE ] the default ecc placement scheme
* @ onfi_set_features [ REPLACEABLE ] set the features for ONFI nand
* @ onfi_get_features [ REPLACEABLE ] get the features for ONFI nand
* @ ecclayout : [ REPLACEABLE ] the default ECC placement scheme
* @ bbt : [ INTERN ] bad block table pointer
* @ bbt_td : [ REPLACEABLE ] bad block table descriptor for flash
* lookup .
@ -468,9 +479,9 @@ struct nand_buffers {
* @ badblock_pattern : [ REPLACEABLE ] bad block scan pattern used for initial
* bad block scan .
* @ controller : [ REPLACEABLE ] a pointer to a hardware controller
* structure which is shared among multiple independend
* structure which is shared among multiple independent
* devices .
* @ priv : [ OPTIONAL ] pointer to private chip date
* @ priv : [ OPTIONAL ] pointer to private chip data
* @ errstat : [ OPTIONAL ] hardware specific function to perform
* additional error status checks ( determine if errors are
* correctable ) .
@ -501,10 +512,16 @@ struct nand_chip {
int ( * errstat ) ( struct mtd_info * mtd , struct nand_chip * this , int state ,
int status , int page ) ;
int ( * write_page ) ( struct mtd_info * mtd , struct nand_chip * chip ,
const uint8_t * buf , int page , int cached , int raw ) ;
const uint8_t * buf , int oob_required , int page ,
int cached , int raw ) ;
int ( * onfi_set_features ) ( struct mtd_info * mtd , struct nand_chip * chip ,
int feature_addr , uint8_t * subfeature_para ) ;
int ( * onfi_get_features ) ( struct mtd_info * mtd , struct nand_chip * chip ,
int feature_addr , uint8_t * subfeature_para ) ;
int chip_delay ;
unsigned int options ;
unsigned int bbt_options ;
int page_shift ;
int phys_erase_shift ;
@ -534,8 +551,6 @@ struct nand_chip {
struct nand_buffers * buffers ;
struct nand_hw_control hwcontrol ;
struct mtd_oob_ops ops ;
uint8_t * bbt ;
struct nand_bbt_descr * bbt_td ;
struct nand_bbt_descr * bbt_md ;
@ -557,6 +572,8 @@ struct nand_chip {
# define NAND_MFR_HYNIX 0xad
# define NAND_MFR_MICRON 0x2c
# define NAND_MFR_AMD 0x01
# define NAND_MFR_MACRONIX 0xc2
# define NAND_MFR_EON 0x92
/**
* struct nand_flash_dev - NAND Flash Device ID Structure
@ -615,9 +632,9 @@ extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
* @ partitions : mtd partition list
* @ chip_delay : R / B delay value in us
* @ options : Option flags , e . g . 16 bit buswidth
* @ ecclayout : ecc layout info structure
* @ bbt_options : BBT option flags , e . g . NAND_BBT_USE_FLASH
* @ ecclayout : ECC layout info structure
* @ part_probe_types : NULL - terminated array of probe types
* @ priv : hardware controller specific settings
*/
struct platform_nand_chip {
int nr_chips ;
@ -627,8 +644,8 @@ struct platform_nand_chip {
struct nand_ecclayout * ecclayout ;
int chip_delay ;
unsigned int options ;
unsigned int bbt_options ;
const char * * part_probe_types ;
void * priv ;
} ;
/* Keep gcc happy */
@ -650,6 +667,7 @@ struct platform_nand_ctrl {
int ( * dev_ready ) ( struct mtd_info * mtd ) ;
void ( * select_chip ) ( struct mtd_info * mtd , int chip ) ;
void ( * cmd_ctrl ) ( struct mtd_info * mtd , int dat , unsigned int ctrl ) ;
unsigned char ( * read_byte ) ( struct mtd_info * mtd ) ;
void * priv ;
} ;
@ -679,4 +697,23 @@ void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
void nand_read_buf16 ( struct mtd_info * mtd , uint8_t * buf , int len ) ;
uint8_t nand_read_byte ( struct mtd_info * mtd ) ;
/* return the supported asynchronous timing mode. */
# ifdef CONFIG_SYS_NAND_ONFI_DETECTION
static inline int onfi_get_async_timing_mode ( struct nand_chip * chip )
{
if ( ! chip - > onfi_version )
return ONFI_TIMING_MODE_UNKNOWN ;
return le16_to_cpu ( chip - > onfi_params . async_timing_mode ) ;
}
/* return the supported synchronous timing mode. */
static inline int onfi_get_sync_timing_mode ( struct nand_chip * chip )
{
if ( ! chip - > onfi_version )
return ONFI_TIMING_MODE_UNKNOWN ;
return le16_to_cpu ( chip - > onfi_params . src_sync_timing_mode ) ;
}
# endif
# endif /* __LINUX_MTD_NAND_H */
Sergey Lapin
11 years ago
committed by
Scott Wood