mx25pdk: Add Ethernet support

mx25pdk has a Ethernet port that is connected to its internal FEC controller.

In order to power up the Ethernet PHY (DP83640) it is necessary to communicate
with the MC34704 PMIC via I2C.

Make the FEC ethernet port functional

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

board/freescale/mx25pdk/mx25pdk.c

@@ -26,7 +26,13 @@
 #include <asm/arch/clock.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
+#include <i2c.h>
+#include <pmic.h>
+#include <fsl_pmic.h>
+#include <mc34704.h>
 
+#define FEC_RESET_B		IMX_GPIO_NR(2, 3)
+#define FEC_ENABLE_B		IMX_GPIO_NR(4, 8)
 #define CARD_DETECT		IMX_GPIO_NR(2, 1)
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -37,6 +43,47 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = {
 };
 #endif
 
+static void mx25pdk_fec_init(void)
+{
+	struct iomuxc_mux_ctl *muxctl;
+	struct iomuxc_pad_ctl *padctl;
+	u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
+	u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+
+	/* FEC pin init is generic */
+	mx25_fec_init_pins();
+
+	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+	/*
+	 * Set up FEC_RESET_B and FEC_ENABLE_B
+	 *
+	 * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12
+	 * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17
+	 */
+	writel(gpio_mux_mode, &muxctl->pad_d12);
+	writel(gpio_mux_mode, &muxctl->pad_a17);
+
+	writel(0x0, &padctl->pad_d12);
+	writel(0x0, &padctl->pad_a17);
+
+	/* Assert RESET and ENABLE low */
+	gpio_direction_output(FEC_RESET_B, 0);
+	gpio_direction_output(FEC_ENABLE_B, 0);
+
+	udelay(10);
+
+	/* Deassert RESET and ENABLE */
+	gpio_set_value(FEC_RESET_B, 1);
+	gpio_set_value(FEC_ENABLE_B, 1);
+
+	/* Setup I2C pins so that PMIC can turn on PHY supply */
+	writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk);
+	writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat);
+	writel(0x1E8, &padctl->pad_i2c1_clk);
+	writel(0x1E8, &padctl->pad_i2c1_dat);
+}
+
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
@@ -60,6 +107,20 @@ int board_init(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+	struct pmic *p;
+
+	mx25pdk_fec_init();
+
+	pmic_init();
+	p = get_pmic();
+	/* Turn on Ethernet PHY supply */
+	pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
+
+	return 0;
+}
+
 #ifdef CONFIG_FSL_ESDHC
 int board_mmc_getcd(struct mmc *mmc)
 {

include/configs/mx25pdk.h

@@ -43,6 +43,7 @@
 #define PHYS_SDRAM_1_SIZE	(64 * 1024 * 1024)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_RAM_ADDR	IMX_RAM_BASE
@@ -105,8 +106,29 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define CONFIG_SYS_FSL_ESDHC_NUM	1
 
+/* PMIC Configs */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_PMIC_FSL
+#define CONFIG_PMIC_FSL_MC34704
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x54
+
 #define CONFIG_DOS_PARTITION
 
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE		IMX_I2C_BASE
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* Ethernet Configs */
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
 #define CONFIG_BOOTDELAY	3
 
 #define CONFIG_LOADADDR		0x81000000	/* loadaddr env var */