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board/freescale: Update ddr clk_adjust

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This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
master
Shengzhou Liu 8 years ago committed by York Sun
parent d8e5163ad8
commit e04f9d0c2f
13 changed files with 172 additions and 172 deletions
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  1. 28
      board/freescale/ls1021aqds/ddr.h
  2. 28
      board/freescale/ls1043aqds/ddr.h
  3. 6
      board/freescale/ls1043ardb/ddr.h
  4. 32
      board/freescale/ls2080aqds/ddr.h
  5. 32
      board/freescale/ls2080ardb/ddr.h
  6. 22
      board/freescale/t102xqds/ddr.c
  7. 12
      board/freescale/t102xrdb/ddr.c
  8. 22
      board/freescale/t1040qds/ddr.h
  9. 26
      board/freescale/t104xrdb/ddr.h
  10. 40
      board/freescale/t208xqds/ddr.h
  11. 20
      board/freescale/t208xrdb/ddr.h
  12. 38
      board/freescale/t4qds/ddr.h
  13. 38
      board/freescale/t4rdb/ddr.h

28
board/freescale/ls1021aqds/ddr.h
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@ -31,21 +31,21 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
#ifdef CONFIG_SYS_FSL_DDR4
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,},
{1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
{1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 8, 8, 0x090A0B0B, 0x0C0D0E0C,},
{1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
{1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,},
#elif defined(CONFIG_SYS_FSL_DDR3)
{1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
{2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
{1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
{2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
#else
#error DDR type not defined
#endif

28
board/freescale/ls1043aqds/ddr.h
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@ -34,21 +34,21 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
#ifdef CONFIG_SYS_FSL_DDR4
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,},
{1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
{1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,},
{1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
{1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,},
#elif defined(CONFIG_SYS_FSL_DDR3)
{1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
{2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
{1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
{2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
#else
#error DDR type not defined
#endif

6
board/freescale/ls1043ardb/ddr.h
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@ -34,9 +34,9 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
#ifdef CONFIG_SYS_FSL_DDR4
{1, 1666, 0, 6, 7, 0x07090800, 0x00000000,},
{1, 1900, 0, 6, 7, 0x07090800, 0x00000000,},
{1, 2200, 0, 6, 7, 0x07090800, 0x00000000,},
{1, 1666, 0, 12, 7, 0x07090800, 0x00000000,},
{1, 1900, 0, 12, 7, 0x07090800, 0x00000000,},
{1, 2200, 0, 12, 7, 0x07090800, 0x00000000,},
#endif
{}
};

32
board/freescale/ls2080aqds/ddr.h
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@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2300, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{2, 2300, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
{2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
{2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
{2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
{}
};
@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};

32
board/freescale/ls2080ardb/ddr.h
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@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 5, 9, 0x090A0B0E, 0x0F11110C,},
{2, 1900, 0, 6, 0xA, 0x0B0C0E11, 0x1214140F,},
{2, 2300, 0, 6, 0xB, 0x0C0D0F12, 0x14161610,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 10, 9, 0x090A0B0E, 0x0F11110C,},
{2, 1900, 0, 12, 0xA, 0x0B0C0E11, 0x1214140F,},
{2, 2300, 0, 12, 0xB, 0x0C0D0F12, 0x14161610,},
{}
};
@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
{2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
{2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
{2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
{}
};
@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};

22
board/freescale/t102xqds/ddr.c
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@ -35,18 +35,18 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
#if defined(CONFIG_SYS_FSL_DDR4)
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
#elif defined(CONFIG_SYS_FSL_DDR3)
{2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
#else
#error DDR type not defined
#endif

12
board/freescale/t102xrdb/ddr.c
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@ -34,12 +34,12 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
{2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{}
};

22
board/freescale/t1040qds/ddr.h
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@ -29,18 +29,18 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
#ifdef CONFIG_SYS_FSL_DDR4
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
#elif defined(CONFIG_SYS_FSL_DDR3)
{2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
#else
#error DDR type not defined
#endif

26
board/freescale/t104xrdb/ddr.h
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@ -29,20 +29,20 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2
*/
#ifdef CONFIG_SYS_FSL_DDR4
{2, 1600, 4, 4, 6, 0x07090A0c, 0x0e0f100a},
{2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a},
#elif defined(CONFIG_SYS_FSL_DDR3)
{2, 833, 4, 4, 6, 0x06060607, 0x08080807},
{2, 833, 0, 4, 6, 0x06060607, 0x08080807},
{2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
{2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
{1, 833, 4, 4, 6, 0x06060607, 0x08080807},
{1, 833, 0, 4, 6, 0x06060607, 0x08080807},
{1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
{1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
{2, 833, 4, 8, 6, 0x06060607, 0x08080807},
{2, 833, 0, 8, 6, 0x06060607, 0x08080807},
{2, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09},
{2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09},
{2, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A},
{1, 833, 4, 8, 6, 0x06060607, 0x08080807},
{1, 833, 0, 8, 6, 0x06060607, 0x08080807},
{1, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09},
{1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09},
{1, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A},
{1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A},
#else
#error DDR type not defined
#endif

40
board/freescale/t208xqds/ddr.h
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@ -28,17 +28,17 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
{2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09},
{2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a},
{2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c},
{2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d},
{2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d},
{1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
{1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
{1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
{1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c},
{1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
{2, 1200, 0, 10, 7, 0x0708090a, 0x0b0c0d09},
{2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a},
{2, 1700, 0, 10, 8, 0x090a0b0c, 0x0e10110c},
{2, 1900, 0, 10, 8, 0x090b0c0f, 0x1012130d},
{2, 2140, 0, 10, 8, 0x090b0c0f, 0x1012130d},
{1, 1200, 0, 10, 7, 0x0808090a, 0x0b0c0c0a},
{1, 1500, 0, 10, 6, 0x07070809, 0x0a0b0b09},
{1, 1600, 0, 10, 8, 0x090b0b0d, 0x0d0e0f0b},
{1, 1700, 0, 8, 8, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 10, 8, 0x090a0c0d, 0x0e0f110c},
{1, 2140, 0, 8, 8, 0x090a0b0d, 0x0e0f110b},
{}
};
@ -49,15 +49,15 @@ static const struct board_specific_parameters rdimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
/* TODO: need tuning these parameters if RDIMM is used */
{4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
{4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
{2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
{2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
{1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
{1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
{4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
{4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
{4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
{2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
{2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
{2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
{1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
{1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
{1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
{}
};

20
board/freescale/t208xrdb/ddr.h
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@ -28,16 +28,16 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
{2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
{2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
{2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
{2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
{2, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09},
{1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
{1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
{1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
{1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09},
{2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
{2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
{2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
{2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
{2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
{1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
{1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
{1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
{1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
{}
};

38
board/freescale/t4qds/ddr.h
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@ -31,16 +31,16 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
{2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
{2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
{2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
{2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
{2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
{2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
{2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
{1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
{1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
{1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
{1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{}
};
@ -50,15 +50,15 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
{4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
{4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
{2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
{1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{4, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{4, 1666, 0, 10, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
{4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{2, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
{2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{1, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
{1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{}
};

38
board/freescale/t4rdb/ddr.h
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@ -27,16 +27,16 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a},
{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09},
{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b},
{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a},
{2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
{2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a},
{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a},
{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b},
{2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a},
{2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09},
{2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b},
{2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a},
{2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
{2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
{1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a},
{1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a},
{1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b},
{}
};
@ -46,15 +46,15 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
{4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
{2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
{2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
{1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
{1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
{4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
{4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
{4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
{2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
{2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
{2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
{1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
{1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
{1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
{}
};

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