Add support for the Atheros AR934x WiSoCs. This patchs adds complete system init, including PLL and DRAM init, both of which happen from full C environment, since the AR934x has proper SRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>master
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/* |
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* Copyright (C) 2016 Marek Vasut <marex@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include "skeleton.dtsi" |
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/ { |
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compatible = "qca,ar934x"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "mips,mips74Kc"; |
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reg = <0>; |
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}; |
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}; |
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clocks { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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xtal: xtal { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-output-names = "xtal"; |
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}; |
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}; |
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ahb { |
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compatible = "simple-bus"; |
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ranges; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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apb { |
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compatible = "simple-bus"; |
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ranges; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ehci0: ehci@1b000100 { |
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compatible = "generic-ehci"; |
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reg = <0x1b000100 0x100>; |
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status = "disabled"; |
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}; |
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uart0: uart@18020000 { |
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compatible = "ns16550"; |
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reg = <0x18020000 0x20>; |
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reg-shift = <2>; |
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status = "disabled"; |
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}; |
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gmac0: eth@0x19000000 { |
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compatible = "qca,ag934x-mac"; |
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reg = <0x19000000 0x200>; |
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phy = <&phy0>; |
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phy-mode = "rgmii"; |
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status = "disabled"; |
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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phy0: ethernet-phy@0 { |
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reg = <0>; |
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}; |
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}; |
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}; |
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gmac1: eth@0x1a000000 { |
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compatible = "qca,ag934x-mac"; |
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reg = <0x1a000000 0x200>; |
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phy = <&phy1>; |
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phy-mode = "rgmii"; |
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status = "disabled"; |
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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phy1: ethernet-phy@0 { |
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reg = <0>; |
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}; |
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}; |
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}; |
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}; |
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spi0: spi@1f000000 { |
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compatible = "qca,ar7100-spi"; |
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reg = <0x1f000000 0x10>; |
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status = "disabled"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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}; |
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}; |
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cpu.o
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obj-y += clk.o
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obj-y += ddr.o
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/*
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* Copyright (C) 2016 Marek Vasut <marex@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/addrspace.h> |
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#include <asm/types.h> |
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#include <mach/ar71xx_regs.h> |
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#include <mach/reset.h> |
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#include <wait_bit.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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* The math for calculating PLL: |
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* NFRAC * 2^8 |
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* NINT + ------------- |
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* XTAL [MHz] 2^(18 - 1) |
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* PLL [MHz] = ------------ * ---------------------- |
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* REFDIV 2^OUTDIV |
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* |
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* Unfortunatelly, there is no way to reliably compute the variables. |
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* The vendor U-Boot port contains macros for various combinations of |
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* CPU PLL / DDR PLL / AHB bus speed and there is no obvious pattern |
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* in those numbers. |
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*/ |
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struct ar934x_pll_config { |
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u8 range; |
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u8 refdiv; |
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u8 outdiv; |
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/* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */ |
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u8 nint[2]; |
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}; |
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struct ar934x_clock_config { |
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u16 cpu_freq; |
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u16 ddr_freq; |
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u16 ahb_freq; |
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struct ar934x_pll_config cpu_pll; |
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struct ar934x_pll_config ddr_pll; |
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}; |
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static const struct ar934x_clock_config ar934x_clock_config[] = { |
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{ 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } }, |
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{ 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } }, |
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{ 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } }, |
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{ 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } }, |
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{ 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } }, |
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{ 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } }, |
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{ 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } }, |
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{ 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } }, |
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{ 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } }, |
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{ 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } }, |
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{ 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } }, |
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{ 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } }, |
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{ 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } }, |
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{ 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } }, |
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{ 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } }, |
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{ 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } }, |
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{ 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } }, |
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{ 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } }, |
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{ 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } }, |
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{ 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } }, |
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{ 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } }, |
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{ 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } }, |
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{ 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } }, |
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{ 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } }, |
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{ 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } }, |
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{ 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } }, |
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{ 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } }, |
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{ 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } }, |
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}; |
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static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) |
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{ |
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u32 reg; |
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do { |
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writel(0x10810f00, pll_reg_base + 0x4); |
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writel(srif_val, pll_reg_base + 0x0); |
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writel(0xd0810f00, pll_reg_base + 0x4); |
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writel(0x03000000, pll_reg_base + 0x8); |
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writel(0xd0800f00, pll_reg_base + 0x4); |
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clrbits_be32(pll_reg_base + 0x8, BIT(30)); |
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udelay(5); |
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setbits_be32(pll_reg_base + 0x8, BIT(30)); |
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udelay(5); |
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wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0); |
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clrbits_be32(pll_reg_base + 0x8, BIT(30)); |
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udelay(5); |
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/* Check if CPU SRIF PLL locked. */ |
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reg = readl(pll_reg_base + 0x8); |
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reg = (reg & 0x7ffff8) >> 3; |
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} while (reg >= 0x40000); |
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} |
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void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) |
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{ |
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void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE, |
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AR934X_SRIF_SIZE, MAP_NOCACHE); |
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void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, |
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AR71XX_PLL_SIZE, MAP_NOCACHE); |
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const struct ar934x_pll_config *pll_cfg; |
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int i, pll_nint, pll_refdiv, xtal_40 = 0; |
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u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif; |
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/* Configure SRIF PLL with initial values. */ |
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writel(0x13210f00, srif_regs + AR934X_SRIF_CPU_DPLL2_REG); |
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writel(0x03000000, srif_regs + AR934X_SRIF_CPU_DPLL3_REG); |
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writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG); |
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writel(0x03000000, srif_regs + AR934X_SRIF_DDR_DPLL3_REG); |
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writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */ |
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/* Test for 40MHz XTAL */ |
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reg = get_bootstrap(); |
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if (reg & AR934X_BOOTSTRAP_REF_CLK_40) { |
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xtal_40 = 1; |
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cpu_srif = 0x41c00000; |
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ddr_srif = 0x41680000; |
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} else { |
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xtal_40 = 0; |
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cpu_srif = 0x29c00000; |
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ddr_srif = 0x29680000; |
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} |
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/* Locate CPU/DDR PLL configuration */ |
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for (i = 0; i < ARRAY_SIZE(ar934x_clock_config); i++) { |
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if (cpu_mhz != ar934x_clock_config[i].cpu_freq) |
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continue; |
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if (ddr_mhz != ar934x_clock_config[i].ddr_freq) |
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continue; |
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if (ahb_mhz != ar934x_clock_config[i].ahb_freq) |
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continue; |
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/* Entry found */ |
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pll_cfg = &ar934x_clock_config[i].cpu_pll; |
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pll_nint = pll_cfg->nint[xtal_40]; |
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pll_refdiv = pll_cfg->refdiv; |
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cpu_pll = |
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(pll_nint << AR934X_PLL_CPU_CONFIG_NINT_SHIFT) | |
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(pll_refdiv << AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) | |
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(pll_cfg->range << AR934X_PLL_CPU_CONFIG_RANGE_SHIFT) | |
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(pll_cfg->outdiv << AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT); |
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pll_cfg = &ar934x_clock_config[i].ddr_pll; |
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pll_nint = pll_cfg->nint[xtal_40]; |
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pll_refdiv = pll_cfg->refdiv; |
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ddr_pll = |
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(pll_nint << AR934X_PLL_DDR_CONFIG_NINT_SHIFT) | |
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(pll_refdiv << AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) | |
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(pll_cfg->range << AR934X_PLL_DDR_CONFIG_RANGE_SHIFT) | |
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(pll_cfg->outdiv << AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT); |
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break; |
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} |
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/* PLL configuration not found, hang. */ |
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if (i == ARRAY_SIZE(ar934x_clock_config)) |
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hang(); |
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/* Set PLL Bypass */ |
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setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, |
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AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS); |
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setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, |
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AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); |
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setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, |
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AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS); |
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/* Configure CPU PLL */ |
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writel(cpu_pll | AR934X_PLL_CPU_CONFIG_PLLPWD, |
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pll_regs + AR934X_PLL_CPU_CONFIG_REG); |
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/* Configure DDR PLL */ |
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writel(ddr_pll | AR934X_PLL_DDR_CONFIG_PLLPWD, |
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pll_regs + AR934X_PLL_DDR_CONFIG_REG); |
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/* Configure PLL routing */ |
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writel(AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS | |
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AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | |
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AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS | |
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(0 << AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) | |
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(0 << AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) | |
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(1 << AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) | |
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AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL | |
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AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL | |
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AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL, |
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pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); |
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/* Configure SRIF PLLs, which is completely undocumented :-) */ |
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ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_CPU_DPLL1_REG, cpu_srif); |
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ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_DDR_DPLL1_REG, ddr_srif); |
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/* Unset PLL Bypass */ |
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clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, |
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AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS); |
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clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, |
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AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); |
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clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, |
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AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS); |
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/* Enable PLL dithering */ |
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writel((1 << AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT) | |
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(0xf << AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT), |
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pll_regs + AR934X_PLL_DDR_DIT_FRAC_REG); |
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writel(48 << AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT, |
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pll_regs + AR934X_PLL_CPU_DIT_FRAC_REG); |
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} |
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static u32 ar934x_get_xtal(void) |
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{ |
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u32 val; |
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val = get_bootstrap(); |
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if (val & AR934X_BOOTSTRAP_REF_CLK_40) |
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return 40000000; |
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else |
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return 25000000; |
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} |
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int get_serial_clock(void) |
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{ |
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return ar934x_get_xtal(); |
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} |
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static u32 ar934x_cpupll_to_hz(const u32 regval) |
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{ |
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const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & |
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AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; |
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const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & |
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AR934X_PLL_CPU_CONFIG_REFDIV_MASK; |
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const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & |
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AR934X_PLL_CPU_CONFIG_NINT_MASK; |
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const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & |
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AR934X_PLL_CPU_CONFIG_NFRAC_MASK; |
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const u32 xtal = ar934x_get_xtal(); |
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return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); |
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} |
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static u32 ar934x_ddrpll_to_hz(const u32 regval) |
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{ |
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const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & |
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AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; |
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const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & |
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AR934X_PLL_DDR_CONFIG_REFDIV_MASK; |
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const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & |
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AR934X_PLL_DDR_CONFIG_NINT_MASK; |
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const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & |
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AR934X_PLL_DDR_CONFIG_NFRAC_MASK; |
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const u32 xtal = ar934x_get_xtal(); |
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return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); |
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} |
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static void ar934x_update_clock(void) |
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{ |
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void __iomem *regs; |
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u32 ctrl, cpu, cpupll, ddr, ddrpll; |
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u32 cpudiv, ddrdiv, busdiv; |
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u32 cpuclk, ddrclk, busclk; |
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regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, |
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MAP_NOCACHE); |
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cpu = readl(regs + AR934X_PLL_CPU_CONFIG_REG); |
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ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG); |
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ctrl = readl(regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); |
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cpupll = ar934x_cpupll_to_hz(cpu); |
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ddrpll = ar934x_ddrpll_to_hz(ddr); |
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if (ctrl & AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS) |
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cpuclk = ar934x_get_xtal(); |
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else if (ctrl & AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) |
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cpuclk = cpupll; |
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else |
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cpuclk = ddrpll; |
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if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) |
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ddrclk = ar934x_get_xtal(); |
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else if (ctrl & AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) |
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ddrclk = ddrpll; |
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else |
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ddrclk = cpupll; |
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if (ctrl & AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS) |
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busclk = ar934x_get_xtal(); |
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else if (ctrl & AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) |
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busclk = ddrpll; |
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else |
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busclk = cpupll; |
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cpudiv = (ctrl >> AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & |
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AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; |
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ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & |
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AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; |
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busdiv = (ctrl >> AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & |
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AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; |
||||
|
||||
gd->cpu_clk = cpuclk / (cpudiv + 1); |
||||
gd->mem_clk = ddrclk / (ddrdiv + 1); |
||||
gd->bus_clk = busclk / (busdiv + 1); |
||||
} |
||||
|
||||
ulong get_bus_freq(ulong dummy) |
||||
{ |
||||
ar934x_update_clock(); |
||||
return gd->bus_clk; |
||||
} |
||||
|
||||
ulong get_ddr_freq(ulong dummy) |
||||
{ |
||||
ar934x_update_clock(); |
||||
return gd->mem_clk; |
||||
} |
||||
|
||||
int do_ar934x_showclk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
ar934x_update_clock(); |
||||
printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000); |
||||
printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000); |
||||
printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000); |
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
clocks, CONFIG_SYS_MAXARGS, 1, do_ar934x_showclk, |
||||
"display clocks", |
||||
"" |
||||
); |
@ -0,0 +1,10 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Marek Vasut <marex@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
/* The lowlevel_init() is not needed on AR934x */ |
||||
void lowlevel_init(void) {} |
@ -0,0 +1,163 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Marek Vasut <marex@denx.de> |
||||
* |
||||
* Based on RAM init sequence by Piotr Dymacz <pepe2k@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/addrspace.h> |
||||
#include <asm/types.h> |
||||
#include <mach/ar71xx_regs.h> |
||||
#include <mach/reset.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
enum { |
||||
AR934X_SDRAM = 0, |
||||
AR934X_DDR1, |
||||
AR934X_DDR2, |
||||
}; |
||||
|
||||
struct ar934x_mem_config { |
||||
u32 config1; |
||||
u32 config2; |
||||
u32 mode; |
||||
u32 extmode; |
||||
u32 tap; |
||||
}; |
||||
|
||||
static const struct ar934x_mem_config ar934x_mem_config[] = { |
||||
[AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f }, |
||||
[AR934X_DDR1] = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 }, |
||||
[AR934X_DDR2] = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 }, |
||||
}; |
||||
|
||||
void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) |
||||
{ |
||||
void __iomem *ddr_regs; |
||||
const struct ar934x_mem_config *memcfg; |
||||
int memtype; |
||||
u32 reg, cycle, ctl; |
||||
|
||||
ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, |
||||
MAP_NOCACHE); |
||||
|
||||
reg = get_bootstrap(); |
||||
if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */ |
||||
if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */ |
||||
memtype = AR934X_DDR1; |
||||
cycle = 0xffff; |
||||
} else { /* DDR 2 */ |
||||
memtype = AR934X_DDR2; |
||||
if (gd->arch.rev) { |
||||
ctl = BIT(6); /* Undocumented bit :-( */ |
||||
if (reg & BIT(3)) |
||||
cycle = 0xff; |
||||
else |
||||
cycle = 0xffff; |
||||
} else { |
||||
/* Force DDR2/x16 configuratio on old chips. */ |
||||
ctl = 0; |
||||
cycle = 0xffff; /* DDR2 16bit */ |
||||
} |
||||
|
||||
writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG); |
||||
udelay(100); |
||||
|
||||
writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); |
||||
udelay(10); |
||||
|
||||
writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); |
||||
udelay(10); |
||||
|
||||
writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF); |
||||
udelay(10); |
||||
} |
||||
} else { /* SDRAM */ |
||||
memtype = AR934X_SDRAM; |
||||
cycle = 0xffffffff; |
||||
|
||||
writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF); |
||||
udelay(100); |
||||
|
||||
/* Undocumented register */ |
||||
writel(0x13b, ddr_regs + 0x118); |
||||
udelay(100); |
||||
} |
||||
|
||||
memcfg = &ar934x_mem_config[memtype]; |
||||
|
||||
writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG); |
||||
udelay(100); |
||||
|
||||
writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2); |
||||
udelay(100); |
||||
|
||||
writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); |
||||
udelay(10); |
||||
|
||||
writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE); |
||||
mdelay(1); |
||||
|
||||
writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); |
||||
udelay(10); |
||||
|
||||
if (memtype == AR934X_DDR2) { |
||||
writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR); |
||||
udelay(100); |
||||
|
||||
writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); |
||||
udelay(10); |
||||
} |
||||
|
||||
if (memtype != AR934X_SDRAM) |
||||
writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR); |
||||
|
||||
udelay(100); |
||||
|
||||
writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); |
||||
udelay(10); |
||||
|
||||
writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); |
||||
udelay(10); |
||||
|
||||
writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE); |
||||
udelay(100); |
||||
|
||||
writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); |
||||
udelay(10); |
||||
|
||||
writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH); |
||||
udelay(100); |
||||
|
||||
writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0); |
||||
writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1); |
||||
|
||||
if (memtype != AR934X_SDRAM) { |
||||
if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) { |
||||
writel(memcfg->tap, |
||||
ddr_regs + AR934X_DDR_REG_TAP_CTRL2); |
||||
writel(memcfg->tap, |
||||
ddr_regs + AR934X_DDR_REG_TAP_CTRL3); |
||||
} |
||||
} |
||||
|
||||
writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE); |
||||
udelay(100); |
||||
|
||||
writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST); |
||||
udelay(100); |
||||
|
||||
writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2); |
||||
udelay(100); |
||||
|
||||
writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX); |
||||
udelay(100); |
||||
} |
||||
|
||||
void ddr_tap_tuning(void) |
||||
{ |
||||
} |
Loading…
Reference in new issue