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@ -59,7 +59,7 @@ struct upm_freq { |
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/* UPM pattern for bus clock = 25 MHz */ |
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static const u32 upm_patt_25[] = { |
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00, |
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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@ -92,7 +92,7 @@ static const u32 upm_patt_25[] = { |
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/* UPM pattern for bus clock = 33.3 MHz */ |
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static const u32 upm_patt_33[] = { |
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, |
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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@ -125,7 +125,7 @@ static const u32 upm_patt_33[] = { |
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/* UPM pattern for bus clock = 41.7 MHz */ |
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static const u32 upm_patt_42[] = { |
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, |
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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@ -158,7 +158,7 @@ static const u32 upm_patt_42[] = { |
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/* UPM pattern for bus clock = 50 MHz */ |
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static const u32 upm_patt_50[] = { |
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00, |
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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@ -191,7 +191,7 @@ static const u32 upm_patt_50[] = { |
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/* UPM pattern for bus clock = 66.7 MHz */ |
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static const u32 upm_patt_67[] = { |
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, |
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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@ -224,7 +224,7 @@ static const u32 upm_patt_67[] = { |
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/* UPM pattern for bus clock = 83.3 MHz */ |
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static const u32 upm_patt_83[] = { |
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, |
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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@ -257,7 +257,7 @@ static const u32 upm_patt_83[] = { |
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/* UPM pattern for bus clock = 100 MHz */ |
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static const u32 upm_patt_100[] = { |
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000, |
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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@ -290,7 +290,7 @@ static const u32 upm_patt_100[] = { |
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/* UPM pattern for bus clock = 133.3 MHz */ |
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static const u32 upm_patt_133[] = { |
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000, |
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/* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00, |
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@ -323,7 +323,7 @@ static const u32 upm_patt_133[] = { |
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/* UPM pattern for bus clock = 166.7 MHz */ |
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static const u32 upm_patt_167[] = { |
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300, |
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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