85xx: Ensure timebase is zero on secondary cores

The e500um says the timebase is volatile out of reset. To ensure TB sync works we need to make sure its zero. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
17 years ago · e0ff3d350d
parent 650a9e7abc
commit e0ff3d350d
1 changed files with 5 additions and 0 deletions
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@ -37,6 +37,11 @@ __secondary_start_page:
 	li	r3,0x201
 	mtspr	SPRN_BUCSR,r3

+	/* Ensure TB is 0 */
+	li	r3,0
+	mttbl	r3
+	mttbu	r3
+
 	/* Enable/invalidate the I-Cache */
 	mfspr	r0,SPRN_L1CSR1
 	ori	r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)