Tom Rini
9 years ago
commit
e1417c7b66
@ -0,0 +1,16 @@ |
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/* |
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* Freescale ls1021a QDS board common device tree source |
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* |
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* Copyright 2013-2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/dts-v1/; |
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#include "ls1021a-qds.dtsi" |
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|
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/ { |
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chosen { |
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stdout-path = &uart0; |
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}; |
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}; |
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@ -0,0 +1,16 @@ |
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/* |
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* Freescale ls1021a QDS board common device tree source |
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* |
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* Copyright 2013-2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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#include "ls1021a-qds.dtsi" |
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/ { |
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chosen { |
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stdout-path = &lpuart0; |
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}; |
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}; |
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@ -1,12 +1,11 @@ |
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/* |
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* Freescale ls1021a QDS board device tree source |
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* Freescale ls1021a QDS board common device tree source |
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* |
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* Copyright 2013-2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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#include "ls1021a.dtsi" |
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/ { |
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@ -0,0 +1,433 @@ |
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/*
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* FSL PAMU driver |
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* |
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* Copyright 2012-2016 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <linux/log2.h> |
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#include <malloc.h> |
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#include <asm/fsl_pamu.h> |
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struct paace *ppaact; |
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struct paace *sec; |
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unsigned long fspi; |
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static inline int __ilog2_roundup_64(uint64_t val) |
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{ |
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if ((val & (val - 1)) == 0) |
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return __ilog2_u64(val); |
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else |
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return __ilog2_u64(val) + 1; |
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} |
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static inline int count_lsb_zeroes(unsigned long val) |
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{ |
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return ffs(val) - 1; |
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} |
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static unsigned int map_addrspace_size_to_wse(uint64_t addrspace_size) |
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{ |
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/* window size is 2^(WSE+1) bytes */ |
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return count_lsb_zeroes(addrspace_size >> PAMU_PAGE_SHIFT) + |
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PAMU_PAGE_SHIFT - 1; |
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} |
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static unsigned int map_subwindow_cnt_to_wce(uint32_t subwindow_cnt) |
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{ |
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/* window count is 2^(WCE+1) bytes */ |
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return count_lsb_zeroes(subwindow_cnt) - 1; |
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} |
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static void pamu_setup_default_xfer_to_host_ppaace(struct paace *ppaace) |
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{ |
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set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY); |
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set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR, |
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PAACE_M_COHERENCE_REQ); |
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} |
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static void pamu_setup_default_xfer_to_host_spaace(struct paace *spaace) |
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{ |
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set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY); |
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set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR, |
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PAACE_M_COHERENCE_REQ); |
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} |
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|
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/** Sets up PPAACE entry for specified liodn
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* |
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* @param[in] liodn Logical IO device number |
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* @param[in] win_addr starting address of DSA window |
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* @param[in] win-size size of DSA window |
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* @param[in] omi Operation mapping index -- if ~omi == 0 then omi |
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not defined |
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* @param[in] stashid cache stash id for associated cpu -- if ~stashid == 0 |
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then stashid not defined |
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* @param[in] snoopid snoop id for hardware coherency -- if ~snoopid == 0 |
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then snoopid not defined |
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* @param[in] subwin_cnt number of sub-windows |
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* |
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* @return Returns 0 upon success else error code < 0 returned |
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*/ |
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static int pamu_config_ppaace(uint32_t liodn, uint64_t win_addr, |
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uint64_t win_size, uint32_t omi, |
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uint32_t snoopid, uint32_t stashid, |
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uint32_t subwin_cnt) |
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{ |
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struct paace *ppaace; |
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if ((win_size & (win_size - 1)) || win_size < PAMU_PAGE_SIZE) |
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return -1; |
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if (win_addr & (win_size - 1)) |
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return -2; |
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if (liodn > NUM_PPAACT_ENTRIES) { |
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printf("Entries in PPACT not sufficient\n"); |
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return -3; |
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} |
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ppaace = &ppaact[liodn]; |
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/* window size is 2^(WSE+1) bytes */ |
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set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE, |
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map_addrspace_size_to_wse(win_size)); |
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pamu_setup_default_xfer_to_host_ppaace(ppaace); |
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if (sizeof(phys_addr_t) > 4) |
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ppaace->wbah = (u64)win_addr >> (PAMU_PAGE_SHIFT + 20); |
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else |
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ppaace->wbah = 0; |
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set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL, |
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(win_addr >> PAMU_PAGE_SHIFT)); |
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/* set up operation mapping if it's configured */ |
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if (omi < OME_NUMBER_ENTRIES) { |
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set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED); |
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ppaace->op_encode.index_ot.omi = omi; |
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} else if (~omi != 0) { |
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return -3; |
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} |
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|
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/* configure stash id */ |
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if (~stashid != 0) |
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set_bf(ppaace->impl_attr, PAACE_IA_CID, stashid); |
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/* configure snoop id */ |
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if (~snoopid != 0) |
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ppaace->domain_attr.to_host.snpid = snoopid; |
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if (subwin_cnt) { |
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/* window count is 2^(WCE+1) bytes */ |
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set_bf(ppaace->impl_attr, PAACE_IA_WCE, |
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map_subwindow_cnt_to_wce(subwin_cnt)); |
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set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0x1); |
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ppaace->fspi = fspi; |
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fspi = fspi + DEFAULT_NUM_SUBWINDOWS - 1; |
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} else { |
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set_bf(ppaace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL); |
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} |
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asm volatile("sync" : : : "memory"); |
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/* Mark the ppace entry valid */ |
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ppaace->addr_bitfields |= PAACE_V_VALID; |
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asm volatile("sync" : : : "memory"); |
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return 0; |
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} |
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static int pamu_config_spaace(uint32_t liodn, |
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uint64_t subwin_size, uint64_t subwin_addr, uint64_t size, |
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uint32_t omi, uint32_t snoopid, uint32_t stashid) |
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{ |
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struct paace *paace; |
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/* Align start addr of subwin to subwindoe size */ |
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uint64_t sec_addr = subwin_addr & ~(subwin_size - 1); |
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uint64_t end_addr = subwin_addr + size; |
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int size_shift = __ilog2_u64(subwin_size); |
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uint64_t win_size = 0; |
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uint32_t index, swse; |
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unsigned long fspi_idx; |
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/* Recalculate the size */ |
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size = end_addr - sec_addr; |
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if (!subwin_size) |
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return -1; |
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if (liodn > NUM_PPAACT_ENTRIES) { |
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printf("LIODN No programmed %d > no. of PPAACT entries %d\n", |
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liodn, NUM_PPAACT_ENTRIES); |
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return -1; |
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} |
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while (sec_addr < end_addr) { |
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debug("sec_addr < end_addr is %llx < %llx\n", sec_addr, |
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end_addr); |
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paace = &ppaact[liodn]; |
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if (!paace) |
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return -1; |
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fspi_idx = paace->fspi; |
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/* Calculating the win_size here as if we map in index 0,
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paace entry woudl need to be programmed for SWSE */ |
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win_size = end_addr - sec_addr; |
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win_size = 1 << __ilog2_roundup_64(win_size); |
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if (win_size > subwin_size) |
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win_size = subwin_size; |
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else if (win_size < PAMU_PAGE_SIZE) |
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win_size = PAMU_PAGE_SIZE; |
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debug("win_size is %llx\n", win_size); |
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swse = map_addrspace_size_to_wse(win_size); |
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index = sec_addr >> size_shift; |
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if (index == 0) { |
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set_bf(paace->win_bitfields, PAACE_WIN_SWSE, swse); |
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set_bf(paace->addr_bitfields, PAACE_AF_AP, |
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PAACE_AP_PERMS_ALL); |
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sec_addr += subwin_size; |
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continue; |
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} |
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paace = sec + fspi_idx + index - 1; |
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debug("SPAACT:Writing at location %p, index %d\n", paace, |
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index); |
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pamu_setup_default_xfer_to_host_spaace(paace); |
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set_bf(paace->addr_bitfields, SPAACE_AF_LIODN, liodn); |
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set_bf(paace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL); |
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/* configure snoop id */ |
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if (~snoopid != 0) |
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paace->domain_attr.to_host.snpid = snoopid; |
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if (paace->addr_bitfields & PAACE_V_VALID) { |
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debug("Reached overlap condition\n"); |
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debug("%d < %d\n", get_bf(paace->win_bitfields, |
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PAACE_WIN_SWSE), swse); |
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if (get_bf(paace->win_bitfields, PAACE_WIN_SWSE) < swse) |
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set_bf(paace->win_bitfields, PAACE_WIN_SWSE, |
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swse); |
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} else { |
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set_bf(paace->win_bitfields, PAACE_WIN_SWSE, swse); |
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} |
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paace->addr_bitfields |= PAACE_V_VALID; |
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sec_addr += subwin_size; |
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} |
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return 0; |
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} |
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int pamu_init(void) |
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{ |
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u32 base_addr = CONFIG_SYS_PAMU_ADDR; |
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struct ccsr_pamu *regs; |
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u32 i = 0; |
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u64 ppaact_phys, ppaact_lim, ppaact_size; |
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u64 spaact_phys, spaact_lim, spaact_size; |
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ppaact_size = sizeof(struct paace) * NUM_PPAACT_ENTRIES; |
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spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES; |
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/* Allocate space for Primary PAACT Table */ |
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ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size); |
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if (!ppaact) |
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return -1; |
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memset(ppaact, 0, ppaact_size); |
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/* Allocate space for Secondary PAACT Table */ |
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sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size); |
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if (!sec) |
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return -1; |
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memset(sec, 0, spaact_size); |
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ppaact_phys = virt_to_phys((void *)ppaact); |
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ppaact_lim = ppaact_phys + ppaact_size; |
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spaact_phys = (uint64_t)virt_to_phys((void *)sec); |
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spaact_lim = spaact_phys + spaact_size; |
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/* Configure all PAMU's */ |
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for (i = 0; i < CONFIG_NUM_PAMU; i++) { |
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regs = (struct ccsr_pamu *)base_addr; |
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out_be32(®s->ppbah, ppaact_phys >> 32); |
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out_be32(®s->ppbal, (uint32_t)ppaact_phys); |
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out_be32(®s->pplah, (ppaact_lim) >> 32); |
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out_be32(®s->pplal, (uint32_t)ppaact_lim); |
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if (sec != NULL) { |
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out_be32(®s->spbah, spaact_phys >> 32); |
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out_be32(®s->spbal, (uint32_t)spaact_phys); |
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out_be32(®s->splah, spaact_lim >> 32); |
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out_be32(®s->splal, (uint32_t)spaact_lim); |
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} |
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asm volatile("sync" : : : "memory"); |
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base_addr += PAMU_OFFSET; |
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} |
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return 0; |
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} |
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void pamu_enable(void) |
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{ |
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u32 i = 0; |
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u32 base_addr = CONFIG_SYS_PAMU_ADDR; |
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for (i = 0; i < CONFIG_NUM_PAMU; i++) { |
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setbits_be32((void *)base_addr + PAMU_PCR_OFFSET, |
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PAMU_PCR_PE); |
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asm volatile("sync" : : : "memory"); |
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base_addr += PAMU_OFFSET; |
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} |
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} |
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void pamu_reset(void) |
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{ |
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u32 i = 0; |
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u32 base_addr = CONFIG_SYS_PAMU_ADDR; |
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struct ccsr_pamu *regs; |
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for (i = 0; i < CONFIG_NUM_PAMU; i++) { |
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regs = (struct ccsr_pamu *)base_addr; |
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/* Clear PPAACT Base register */ |
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out_be32(®s->ppbah, 0); |
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out_be32(®s->ppbal, 0); |
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out_be32(®s->pplah, 0); |
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out_be32(®s->pplal, 0); |
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out_be32(®s->spbah, 0); |
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out_be32(®s->spbal, 0); |
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out_be32(®s->splah, 0); |
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out_be32(®s->splal, 0); |
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clrbits_be32((void *)regs + PAMU_PCR_OFFSET, PAMU_PCR_PE); |
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asm volatile("sync" : : : "memory"); |
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base_addr += PAMU_OFFSET; |
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} |
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} |
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void pamu_disable(void) |
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{ |
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u32 i = 0; |
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u32 base_addr = CONFIG_SYS_PAMU_ADDR; |
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for (i = 0; i < CONFIG_NUM_PAMU; i++) { |
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clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); |
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asm volatile("sync" : : : "memory"); |
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base_addr += PAMU_OFFSET; |
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} |
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} |
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static uint64_t find_max(uint64_t arr[], int num) |
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{ |
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int i = 0; |
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int max = 0; |
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for (i = 1 ; i < num; i++) |
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if (arr[max] < arr[i]) |
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max = i; |
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return arr[max]; |
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} |
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static uint64_t find_min(uint64_t arr[], int num) |
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{ |
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int i = 0; |
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int min = 0; |
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for (i = 1 ; i < num; i++) |
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if (arr[min] > arr[i]) |
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min = i; |
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return arr[min]; |
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} |
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static uint32_t get_win_cnt(uint64_t size) |
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{ |
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uint32_t win_cnt = DEFAULT_NUM_SUBWINDOWS; |
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while (win_cnt && (size/win_cnt) < PAMU_PAGE_SIZE) |
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win_cnt >>= 1; |
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return win_cnt; |
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} |
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int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn) |
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{ |
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int i = 0; |
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int ret = 0; |
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uint32_t num_sec_windows = 0; |
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uint32_t num_windows = 0; |
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uint64_t min_addr, max_addr; |
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uint64_t size; |
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uint64_t subwin_size; |
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int sizebit; |
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min_addr = find_min(tbl->start_addr, num_entries); |
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max_addr = find_max(tbl->end_addr, num_entries); |
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size = max_addr - min_addr + 1; |
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if (!size) |
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return -1; |
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sizebit = __ilog2_roundup_64(size); |
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size = 1 << sizebit; |
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debug("min start_addr is %llx\n", min_addr); |
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debug("max end_addr is %llx\n", max_addr); |
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debug("size found is %llx\n", size); |
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if (size < PAMU_PAGE_SIZE) |
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size = PAMU_PAGE_SIZE; |
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|
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while (1) { |
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min_addr = min_addr & ~(size - 1); |
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if (min_addr + size > max_addr) |
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break; |
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size <<= 1; |
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if (!size) |
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return -1; |
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} |
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debug("PAACT :Base addr is %llx\n", min_addr); |
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debug("PAACT : Size is %llx\n", size); |
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num_windows = get_win_cnt(size); |
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/* For a single window, no spaact entries are required
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* sec_sub_window count = 0 */ |
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if (num_windows > 1) |
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num_sec_windows = num_windows; |
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else |
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num_sec_windows = 0; |
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ret = pamu_config_ppaace(liodn, min_addr, |
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size , -1, -1, -1, num_sec_windows); |
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if (ret < 0) |
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return ret; |
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debug("configured ppace\n"); |
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|
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if (num_sec_windows) { |
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subwin_size = size >> count_lsb_zeroes(num_sec_windows); |
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debug("subwin_size is %llx\n", subwin_size); |
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|
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for (i = 0; i < num_entries; i++) { |
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ret = pamu_config_spaace(liodn, |
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subwin_size, tbl->start_addr[i] - min_addr, |
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tbl->size[i], -1, -1, -1); |
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if (ret < 0) |
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return ret; |
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} |
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} |
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return ret; |
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} |
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@ -0,0 +1,55 @@ |
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/*
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* Copyright 2012-2016 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/fsl_pamu.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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|
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void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) |
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{ |
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int i = 0; |
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int j; |
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|
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tbl->start_addr[i] = |
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(uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE); |
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tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED)); |
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tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; |
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|
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i++; |
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#ifdef CONFIG_SYS_FLASH_BASE_PHYS |
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tbl->start_addr[i] = |
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(uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS); |
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tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */ |
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tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; |
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|
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i++; |
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#endif |
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debug("PAMU address\t\t\tsize\n"); |
||||
for (j = 0; j < i ; j++) |
||||
debug("%llx \t\t\t%llx\n", tbl->start_addr[j], tbl->size[j]); |
||||
|
||||
*num_entries = i; |
||||
} |
||||
|
||||
int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s) |
||||
{ |
||||
struct pamu_addr_tbl tbl; |
||||
int num_entries = 0; |
||||
int ret = 0; |
||||
|
||||
construct_pamu_addr_table(&tbl, &num_entries); |
||||
|
||||
ret = config_pamu(&tbl, num_entries, liodn_ns); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
ret = config_pamu(&tbl, num_entries, liodn_s); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
return ret; |
||||
} |
||||
@ -0,0 +1,169 @@ |
||||
/*
|
||||
* Copyright 2012-2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __PAMU_H |
||||
#define __PAMU_H |
||||
|
||||
#define CONFIG_NUM_PAMU 16 |
||||
#define NUM_PPAACT_ENTRIES 512 |
||||
#define NUM_SPAACT_ENTRIES 256 |
||||
|
||||
/* PAMU_OFFSET to the next pamu space in ccsr */ |
||||
#define PAMU_OFFSET 0x1000 |
||||
|
||||
#define PAMU_TABLE_ALIGNMENT 0x00001000 |
||||
|
||||
#define PAMU_PAGE_SHIFT 12 |
||||
#define PAMU_PAGE_SIZE 4096U |
||||
|
||||
#define PAACE_M_COHERENCE_REQ 0x01 |
||||
|
||||
#define PAACE_DA_HOST_CR 0x80 |
||||
#define PAACE_DA_HOST_CR_SHIFT 7 |
||||
|
||||
#define PAACE_AF_PT 0x00000002 |
||||
#define PAACE_AF_PT_SHIFT 1 |
||||
|
||||
#define PAACE_PT_PRIMARY 0x0 |
||||
#define PAACE_PT_SECONDARY 0x1 |
||||
|
||||
#define PPAACE_AF_WBAL 0xfffff000 |
||||
#define PPAACE_AF_WBAL_SHIFT 12 |
||||
|
||||
#define OME_NUMBER_ENTRIES 16 /* based on P4080 2.0 silicon plan */ |
||||
|
||||
#define PAACE_IA_CID 0x00FF0000 |
||||
#define PAACE_IA_CID_SHIFT 16 |
||||
#define PAACE_IA_WCE 0x000000F0 |
||||
#define PAACE_IA_WCE_SHIFT 4 |
||||
#define PAACE_IA_ATM 0x0000000C |
||||
#define PAACE_IA_ATM_SHIFT 2 |
||||
#define PAACE_IA_OTM 0x00000003 |
||||
#define PAACE_IA_OTM_SHIFT 0 |
||||
|
||||
#define PAACE_OTM_NO_XLATE 0x00 |
||||
#define PAACE_OTM_IMMEDIATE 0x01 |
||||
#define PAACE_OTM_INDEXED 0x02 |
||||
#define PAACE_OTM_RESERVED 0x03 |
||||
#define PAACE_ATM_NO_XLATE 0x00 |
||||
#define PAACE_ATM_WINDOW_XLATE 0x01 |
||||
#define PAACE_ATM_PAGE_XLATE 0x02 |
||||
#define PAACE_ATM_WIN_PG_XLATE \ |
||||
(PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE) |
||||
#define PAACE_WIN_TWBAL 0xfffff000 |
||||
#define PAACE_WIN_TWBAL_SHIFT 12 |
||||
#define PAACE_WIN_SWSE 0x00000fc0 |
||||
#define PAACE_WIN_SWSE_SHIFT 6 |
||||
|
||||
#define PAACE_AF_AP 0x00000018 |
||||
#define PAACE_AF_AP_SHIFT 3 |
||||
#define PAACE_AF_DD 0x00000004 |
||||
#define PAACE_AF_DD_SHIFT 2 |
||||
#define PAACE_AF_PT 0x00000002 |
||||
#define PAACE_AF_PT_SHIFT 1 |
||||
#define PAACE_AF_V 0x00000001 |
||||
#define PAACE_AF_V_SHIFT 0 |
||||
#define PPAACE_AF_WSE 0x00000fc0 |
||||
#define PPAACE_AF_WSE_SHIFT 6 |
||||
#define PPAACE_AF_MW 0x00000020 |
||||
#define PPAACE_AF_MW_SHIFT 5 |
||||
|
||||
#define PAACE_AP_PERMS_DENIED 0x0 |
||||
#define PAACE_AP_PERMS_QUERY 0x1 |
||||
#define PAACE_AP_PERMS_UPDATE 0x2 |
||||
#define PAACE_AP_PERMS_ALL 0x3 |
||||
|
||||
#define SPAACE_AF_LIODN 0xffff0000 |
||||
#define SPAACE_AF_LIODN_SHIFT 16 |
||||
#define PAACE_V_VALID 0x1 |
||||
|
||||
#define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << \ |
||||
(m##_SHIFT)) & (m))) |
||||
#define get_bf(v, m) (((v) & (m)) >> (m##_SHIFT)) |
||||
|
||||
#define DEFAULT_NUM_SUBWINDOWS 128 |
||||
#define PAMU_PCR_OFFSET 0xc10 |
||||
#define PAMU_PCR_PE 0x40000000 |
||||
|
||||
struct pamu_addr_tbl { |
||||
phys_addr_t start_addr[10]; |
||||
phys_addr_t end_addr[10]; |
||||
phys_size_t size[10]; |
||||
}; |
||||
|
||||
struct paace { |
||||
/* PAACE Offset 0x00 */ |
||||
uint32_t wbah; /* only valid for Primary PAACE */ |
||||
uint32_t addr_bitfields; /* See P/S PAACE_AF_* */ |
||||
|
||||
/* PAACE Offset 0x08 */ |
||||
/* Interpretation of first 32 bits dependent on DD above */ |
||||
union { |
||||
struct { |
||||
/* Destination ID, see PAACE_DID_* defines */ |
||||
uint8_t did; |
||||
/* Partition ID */ |
||||
uint8_t pid; |
||||
/* Snoop ID */ |
||||
uint8_t snpid; |
||||
/* coherency_required : 1 reserved : 7 */ |
||||
uint8_t coherency_required; /* See PAACE_DA_* */ |
||||
} to_host; |
||||
struct { |
||||
/* Destination ID, see PAACE_DID_* defines */ |
||||
uint8_t did; |
||||
uint8_t reserved1; |
||||
uint16_t reserved2; |
||||
} to_io; |
||||
} domain_attr; |
||||
|
||||
/* Implementation attributes + window count + address & operation
|
||||
* translation modes |
||||
*/ |
||||
uint32_t impl_attr; /* See PAACE_IA_* */ |
||||
|
||||
/* PAACE Offset 0x10 */ |
||||
/* Translated window base address */ |
||||
uint32_t twbah; |
||||
uint32_t win_bitfields; /* See PAACE_WIN_* */ |
||||
|
||||
/* PAACE Offset 0x18 */ |
||||
/* first secondary paace entry */ |
||||
uint32_t fspi; /* only valid for Primary PAACE */ |
||||
union { |
||||
struct { |
||||
uint8_t ioea; |
||||
uint8_t moea; |
||||
uint8_t ioeb; |
||||
uint8_t moeb; |
||||
} immed_ot; |
||||
struct { |
||||
uint16_t reserved; |
||||
uint16_t omi; |
||||
} index_ot; |
||||
} op_encode; |
||||
|
||||
/* PAACE Offset 0x20 */ |
||||
uint32_t reserved1[2]; /* not currently implemented */ |
||||
|
||||
/* PAACE Offset 0x28 */ |
||||
uint32_t reserved2[2]; /* not currently implemented */ |
||||
|
||||
/* PAACE Offset 0x30 */ |
||||
uint32_t reserved3[2]; /* not currently implemented */ |
||||
|
||||
/* PAACE Offset 0x38 */ |
||||
uint32_t reserved4[2]; /* not currently implemented */ |
||||
|
||||
}; |
||||
|
||||
int pamu_init(void); |
||||
void pamu_enable(void); |
||||
void pamu_disable(void); |
||||
int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn); |
||||
int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s); |
||||
|
||||
#endif |
||||
@ -0,0 +1,14 @@ |
||||
#PBL preamble and RCW header |
||||
aa55aa55 01ee0100 |
||||
|
||||
#enable IFC, disable QSPI and DSPI |
||||
#0608000a 00000000 00000000 00000000 |
||||
#60000000 00407900 60040a00 21046000 |
||||
#00000000 00000000 00000000 00038000 |
||||
#00000000 001b7200 00000000 00000000 |
||||
|
||||
#disable IFC, enable QSPI and DSPI |
||||
0608000a 00000000 00000000 00000000 |
||||
60000000 00407900 60040a00 21046000 |
||||
00000000 00000000 00000000 00038000 |
||||
20024800 001b7200 00000000 00000000 |
||||
@ -1,7 +1,11 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1021AQDS=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" |
||||
CONFIG_DM_SERIAL=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_E1000=y |
||||
CONFIG_SYS_NS16550=y |
||||
|
||||
@ -1,7 +1,11 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1021AQDS=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" |
||||
CONFIG_DM_SERIAL=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_E1000=y |
||||
CONFIG_FSL_LPUART=y |
||||
|
||||
@ -1,6 +1,10 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1021AQDS=y |
||||
CONFIG_DM_SERIAL=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_E1000=y |
||||
CONFIG_SYS_NS16550=y |
||||
|
||||
@ -1,7 +1,11 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1021AQDS=y |
||||
CONFIG_DM_SERIAL=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" |
||||
CONFIG_SYS_EXTRA_OPTIONS="LPUART" |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_E1000=y |
||||
CONFIG_FSL_LPUART=y |
||||
|
||||
@ -1,8 +1,11 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1021AQDS=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_E1000=y |
||||
CONFIG_SYS_NS16550=y |
||||
@ -0,0 +1,16 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1021AQDS=y |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" |
||||
CONFIG_DM_SPI=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_SPANSION=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_E1000=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_FSL_DSPI=y |
||||
CONFIG_FSL_QSPI=y |
||||
@ -0,0 +1,129 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#include <asm/io.h> |
||||
#include <fsl_qe.h> /* For struct qe_firmware */ |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN |
||||
/**
|
||||
* fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree |
||||
* |
||||
* The binding for an Fman firmware node is documented in |
||||
* Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains |
||||
* the actual Fman firmware binary data. The operating system is expected to |
||||
* be able to parse the binary data to determine any attributes it needs. |
||||
*/ |
||||
void fdt_fixup_fman_firmware(void *blob) |
||||
{ |
||||
int rc, fmnode, fwnode = -1; |
||||
uint32_t phandle; |
||||
struct qe_firmware *fmanfw; |
||||
const struct qe_header *hdr; |
||||
unsigned int length; |
||||
uint32_t crc; |
||||
const char *p; |
||||
|
||||
/* The first Fman we find will contain the actual firmware. */ |
||||
fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman"); |
||||
if (fmnode < 0) |
||||
/* Exit silently if there are no Fman devices */ |
||||
return; |
||||
|
||||
/* If we already have a firmware node, then also exit silently. */ |
||||
if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0) |
||||
return; |
||||
|
||||
/* If the environment variable is not set, then exit silently */ |
||||
p = getenv("fman_ucode"); |
||||
if (!p) |
||||
return; |
||||
|
||||
fmanfw = (struct qe_firmware *)simple_strtoul(p, NULL, 16); |
||||
if (!fmanfw) |
||||
return; |
||||
|
||||
hdr = &fmanfw->header; |
||||
length = fdt32_to_cpu(hdr->length); |
||||
|
||||
/* Verify the firmware. */ |
||||
if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || |
||||
(hdr->magic[2] != 'F')) { |
||||
printf("Data at %p is not an Fman firmware\n", fmanfw); |
||||
return; |
||||
} |
||||
|
||||
if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) { |
||||
printf("Fman firmware at %p is too large (size=%u)\n", |
||||
fmanfw, length); |
||||
return; |
||||
} |
||||
|
||||
length -= sizeof(u32); /* Subtract the size of the CRC */ |
||||
crc = fdt32_to_cpu(*(u32 *)((void *)fmanfw + length)); |
||||
if (crc != crc32_no_comp(0, (void *)fmanfw, length)) { |
||||
printf("Fman firmware at %p has invalid CRC\n", fmanfw); |
||||
return; |
||||
} |
||||
|
||||
length += sizeof(u32); |
||||
|
||||
/* Increase the size of the fdt to make room for the node. */ |
||||
rc = fdt_increase_size(blob, length); |
||||
if (rc < 0) { |
||||
printf("Unable to make room for Fman firmware: %s\n", |
||||
fdt_strerror(rc)); |
||||
return; |
||||
} |
||||
|
||||
/* Create the firmware node. */ |
||||
fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware"); |
||||
if (fwnode < 0) { |
||||
char s[64]; |
||||
fdt_get_path(blob, fmnode, s, sizeof(s)); |
||||
printf("Could not add firmware node to %s: %s\n", s, |
||||
fdt_strerror(fwnode)); |
||||
return; |
||||
} |
||||
rc = fdt_setprop_string(blob, fwnode, "compatible", |
||||
"fsl,fman-firmware"); |
||||
if (rc < 0) { |
||||
char s[64]; |
||||
fdt_get_path(blob, fwnode, s, sizeof(s)); |
||||
printf("Could not add compatible property to node %s: %s\n", s, |
||||
fdt_strerror(rc)); |
||||
return; |
||||
} |
||||
phandle = fdt_create_phandle(blob, fwnode); |
||||
if (!phandle) { |
||||
char s[64]; |
||||
fdt_get_path(blob, fwnode, s, sizeof(s)); |
||||
printf("Could not add phandle property to node %s: %s\n", s, |
||||
fdt_strerror(rc)); |
||||
return; |
||||
} |
||||
rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, length); |
||||
if (rc < 0) { |
||||
char s[64]; |
||||
fdt_get_path(blob, fwnode, s, sizeof(s)); |
||||
printf("Could not add firmware property to node %s: %s\n", s, |
||||
fdt_strerror(rc)); |
||||
return; |
||||
} |
||||
|
||||
/* Find all other Fman nodes and point them to the firmware node. */ |
||||
while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, |
||||
"fsl,fman")) > 0) { |
||||
rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", |
||||
phandle); |
||||
if (rc < 0) { |
||||
char s[64]; |
||||
fdt_get_path(blob, fmnode, s, sizeof(s)); |
||||
printf("Could not add pointer property to node %s: %s\n", |
||||
s, fdt_strerror(rc)); |
||||
return; |
||||
} |
||||
} |
||||
} |
||||
#endif |
||||
Loading…
Reference in new issue