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@ -23,6 +23,7 @@ |
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int board_early_init_f(void) |
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{ |
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struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; |
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u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; |
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/* Enable flash write */ |
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@ -30,6 +31,18 @@ int board_early_init_f(void) |
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/* Clear all of the interrupt of BCSR */ |
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bcsr[0xe] = 0xff; |
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#ifdef CONFIG_MMC |
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/* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */ |
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bcsr[0xc] |= 0x4c; |
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/* Set proper bits in SICR to allow SD signals through */ |
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clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); |
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clrsetbits_be32(&im->sysconf.sicrh, (SICRH_GPIO2_E | SICRH_SPI), |
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(SICRH_GPIO2_E_SD | SICRH_SPI_SD)); |
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#endif |
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#ifdef CONFIG_FSL_SERDES |
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
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u32 spridr = in_be32(&immr->sysconf.spridr); |
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@ -38,21 +51,21 @@ int board_early_init_f(void) |
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switch (PARTID_NO_E(spridr)) { |
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case SPR_8377: |
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, |
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); |
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); |
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break; |
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case SPR_8378: |
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII, |
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FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V); |
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FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V); |
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break; |
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case SPR_8379: |
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, |
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); |
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); |
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, |
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); |
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); |
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break; |
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default: |
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printf("serdes not configured: unknown CPU part number: " |
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"%04x\n", spridr >> 16); |
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"%04x\n", spridr >> 16); |
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break; |
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} |
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#endif /* CONFIG_FSL_SERDES */ |
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