parent
7ebf7443ad
commit
e221174377
@ -0,0 +1,69 @@ |
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# format of this file is: |
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# |
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# 1. blank lines and lines beginning with '#' are ignored |
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# 2. all other lines must have the form <name>=<value> |
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# 3. if a percent appears anywhere, it is replaced like so: |
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# |
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# %s serial number of the main board (10 digit zero filled) |
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# %S serial number of the main board (plain number) |
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# %% a percentage character |
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# |
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# no whitespace is removed in either <name> or <value> |
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# |
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# if first character in <name> is a dash ('-'), then an existing env var |
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# will not be overwritten (the dash is removed). |
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# |
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# if last character in <name> is a plus ('+'), then <value> will be appended |
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# to any existing env var (the plus is removed). Duplicates of <value> are |
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# removed. |
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# |
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|
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# set the ip address based on the main board serial number |
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ipaddr=192.168.1.%S |
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serverip=192.168.1.254 |
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|
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# stop auto execute after tftp |
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autostart=no |
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|
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# |
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# 16M flash map, 64 x 256K sectors, mapped at address 0x40000000 |
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# |
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# sector 0: boot |
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# sector 1: non volatile environment |
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# sectors 2-4: linux kernel image |
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# sectors 5-7: alternate linux kernel image |
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# sectors 8-63: linux initial ramdisk image |
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# |
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|
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fetchboot=tftp 100000 /hymod/u-boot.bin |
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eraseboot=protect off 1:0 ; erase 1:0 ; protect on 1:0 |
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copyboot=protect off 1:0 ; cp.b 100000 40000000 40000 ; protect on 1:0 |
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cmpboot=cmp.b 100000 40000000 40000 |
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newboot=run fetchboot eraseboot copyboot cmpboot |
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|
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fetchlinux=tftp 100000 /hymod/linux.bin |
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eraselinux=erase 1:2-4 |
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copylinux=cp.b 100000 40080000 $(filesize) |
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cmplinux=cmp.b 100000 40080000 $(filesize) |
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newlinux=run fetchlinux eraselinux copylinux cmplinux |
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|
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fetchaltlinux=tftp 100000 /hymod/altlinux.bin |
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erasealtlinux=erase 1:5-7 |
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copyaltlinux=cp.b 100000 40080000 $(filesize) |
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cmpaltlinux=cmp.b 100000 40080000 $(filesize) |
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newaltlinux=run fetchaltlinux erasealtlinux copyaltlinux cmpaltlinux |
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|
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fetchird=tftp 100000 /hymod/initrd.bin |
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eraseird=erase 1:8-63 |
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copyird=cp.b 100000 40200000 $(filesize) |
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cmpird=cmp.b 100000 40200000 $(filesize) |
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newinitrd=run fetchird eraseird copyird cmpird |
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|
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bootcmd=bootm 40080000 40200000 |
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-bootargs=root=/dev/ram rw |
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# these are for hymod linux |
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bootargs+=preload=unix,i2c-cpm,i2c-dev |
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bootargs+=serialno=%S |
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bootargs+=ramdisk_size=32768 |
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bootargs+=automount nisclient nisdomain=mlb.dmt.csiro.au nissrvadr=138.194.112.4 |
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bootdelay=2 |
@ -0,0 +1,966 @@ |
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/***********************************************************************
|
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* |
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M* Modul: lwmon.c |
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M* |
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M* Content: LWMON specific U-Boot commands. |
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* |
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* (C) Copyright 2001, 2002 |
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* DENX Software Engineering |
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* Wolfgang Denk, wd@denx.de |
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* All rights reserved. |
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* |
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D* Design: wd@denx.de |
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C* Coding: wd@denx.de |
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V* Verification: dzu@denx.de |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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***********************************************************************/ |
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|
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/*---------------------------- Headerfiles ----------------------------*/ |
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#include <common.h> |
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#include <mpc8xx.h> |
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#include <commproc.h> |
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#include <i2c.h> |
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#include <command.h> |
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#include <cmd_bsp.h> |
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#include <malloc.h> |
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#include <post.h> |
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|
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#include <linux/types.h> |
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#include <linux/string.h> /* for strdup */ |
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|
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/*------------------------ Local prototypes ---------------------------*/ |
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static long int dram_size (long int, long int *, long int); |
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|
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|
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/*--------------------- Local macros and constants --------------------*/ |
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#define _NOT_USED_ 0xFFFFFFFF |
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|
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/*
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* 66 MHz SDRAM access using UPM A |
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*/ |
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const uint sdram_table[] = |
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{ |
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#if defined(CFG_MEMORY_75) || defined(CFG_MEMORY_8E) |
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/*
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* Single Read. (Offset 0 in UPM RAM) |
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*/ |
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0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, |
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0x1FF5FC47, /* last */ |
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/*
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* SDRAM Initialization (offset 5 in UPM RAM) |
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* |
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* This is no UPM entry point. The following definition uses |
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* the remaining space to establish an initialization |
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* sequence, which is executed by a RUN command. |
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* |
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*/ |
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0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ |
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/*
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* Burst Read. (Offset 8 in UPM RAM) |
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*/ |
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0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, |
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0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Single Write. (Offset 18 in UPM RAM) |
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*/ |
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0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Burst Write. (Offset 20 in UPM RAM) |
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*/ |
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0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, |
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0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */ |
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_NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Refresh (Offset 30 in UPM RAM) |
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*/ |
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0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, |
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0xFFFFFC84, 0xFFFFFC07, /* last */ |
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_NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Exception. (Offset 3c in UPM RAM) |
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*/ |
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0x7FFFFC07, /* last */ |
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0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF, |
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#endif |
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#ifdef CFG_MEMORY_7E |
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/*
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* Single Read. (Offset 0 in UPM RAM) |
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*/ |
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0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */ |
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_NOT_USED_, |
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/*
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* SDRAM Initialization (offset 5 in UPM RAM) |
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* |
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* This is no UPM entry point. The following definition uses |
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* the remaining space to establish an initialization |
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* sequence, which is executed by a RUN command. |
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* |
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*/ |
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0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ |
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/*
|
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* Burst Read. (Offset 8 in UPM RAM) |
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*/ |
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0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00, |
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0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ |
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_NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Single Write. (Offset 18 in UPM RAM) |
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*/ |
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0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */ |
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_NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Burst Write. (Offset 20 in UPM RAM) |
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*/ |
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0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00, |
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0xE1BAFC04, 0x1FF5FC47, /* last */ |
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_NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Refresh (Offset 30 in UPM RAM) |
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*/ |
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0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, |
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0xFFFFFC84, 0xFFFFFC07, /* last */ |
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_NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Exception. (Offset 3c in UPM RAM) |
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*/ |
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0x7FFFFC07, /* last */ |
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0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF, |
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#endif |
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}; |
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|
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/*
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* Check Board Identity: |
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* |
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*/ |
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|
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/***********************************************************************
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F* Function: int checkboard (void) P*A*Z* |
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* |
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P* Parameters: none |
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P* |
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P* Returnvalue: int - 0 is always returned |
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* |
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Z* Intention: This function is the checkboard() method implementation |
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Z* for the lwmon board. Only a standard message is printed. |
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* |
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D* Design: wd@denx.de |
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C* Coding: wd@denx.de |
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V* Verification: dzu@denx.de |
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***********************************************************************/ |
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int checkboard (void) |
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{ |
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puts ("Board: Litronic Monitor IV\n"); |
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return (0); |
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} |
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|
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/***********************************************************************
|
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F* Function: long int initdram (int board_type) P*A*Z* |
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* |
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P* Parameters: int board_type |
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P* - Usually type of the board - ignored here. |
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P* |
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P* Returnvalue: long int |
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P* - Size of initialized memory |
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* |
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Z* Intention: This function is the initdram() method implementation |
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Z* for the lwmon board. |
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Z* The memory controller is initialized to access the |
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Z* DRAM. |
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* |
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D* Design: wd@denx.de |
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C* Coding: wd@denx.de |
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V* Verification: dzu@denx.de |
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***********************************************************************/ |
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long int initdram (int board_type) |
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{ |
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volatile immap_t *immr = (immap_t *) CFG_IMMR; |
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volatile memctl8xx_t *memctl = &immr->im_memctl; |
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long int size_b0; |
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long int size8, size9; |
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int i; |
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|
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/*
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* Configure UPMA for SDRAM |
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*/ |
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upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); |
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|
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memctl->memc_mptpr = CFG_MPTPR; |
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|
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/* burst length=4, burst type=sequential, CAS latency=2 */ |
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memctl->memc_mar = CFG_MAR; |
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|
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/*
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* Map controller bank 3 to the SDRAM bank at preliminary address. |
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*/ |
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memctl->memc_or3 = CFG_OR3_PRELIM; |
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memctl->memc_br3 = CFG_BR3_PRELIM; |
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|
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/* initialize memory address register */ |
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memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */ |
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|
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/* mode initialization (offset 5) */ |
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udelay (200); /* 0x80006105 */ |
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memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05); |
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|
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/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ |
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udelay (1); /* 0x80006130 */ |
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memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); |
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udelay (1); /* 0x80006130 */ |
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memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); |
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|
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udelay (1); /* 0x80006106 */ |
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memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06); |
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|
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memctl->memc_mamr |= MAMR_PTBE; /* refresh enabled */ |
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|
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udelay (200); |
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|
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/* Need at least 10 DRAM accesses to stabilize */ |
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for (i = 0; i < 10; ++i) { |
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volatile unsigned long *addr = |
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(volatile unsigned long *) SDRAM_BASE3_PRELIM; |
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unsigned long val; |
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|
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val = *(addr + i); |
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*(addr + i) = val; |
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} |
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|
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/*
|
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* Check Bank 0 Memory Size for re-configuration |
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* |
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* try 8 column mode |
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*/ |
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size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); |
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|
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udelay (1000); |
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|
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/*
|
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* try 9 column mode |
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*/ |
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size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); |
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|
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if (size8 < size9) { /* leave configuration at 9 columns */ |
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size_b0 = size9; |
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memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTBE; |
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udelay (500); |
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} else { /* back to 8 columns */ |
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size_b0 = size8; |
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memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE; |
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udelay (500); |
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} |
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|
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/*
|
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* Final mapping: |
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*/ |
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|
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memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | |
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OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING; |
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memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; |
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udelay (1000); |
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|
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return (size_b0); |
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} |
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|
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/***********************************************************************
|
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F* Function: static long int dram_size (long int mamr_value, |
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F* long int *base, |
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F* long int maxsize) P*A*Z* |
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* |
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P* Parameters: long int mamr_value |
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P* - Value for MAMR for the test |
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P* long int *base |
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P* - Base address for the test |
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P* long int maxsize |
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P* - Maximum size to test for |
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P* |
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P* Returnvalue: long int |
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P* - Size of probed memory |
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* |
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Z* Intention: Check memory range for valid RAM. A simple memory test |
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Z* determines the actually available RAM size between |
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Z* addresses `base' and `base + maxsize'. Some (not all) |
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Z* hardware errors are detected: |
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Z* - short between address lines |
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Z* - short between data lines |
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* |
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D* Design: wd@denx.de |
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C* Coding: wd@denx.de |
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V* Verification: dzu@denx.de |
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***********************************************************************/ |
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static long int dram_size (long int mamr_value, long int *base, long int maxsize) |
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{ |
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volatile immap_t *immr = (immap_t *) CFG_IMMR; |
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volatile memctl8xx_t *memctl = &immr->im_memctl; |
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volatile long int *addr; |
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ulong cnt, val; |
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ulong save[32]; /* to make test non-destructive */ |
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unsigned char i = 0; |
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|
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memctl->memc_mamr = mamr_value; |
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|
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for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { |
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addr = base + cnt; /* pointer arith! */ |
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|
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save[i++] = *addr; |
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*addr = ~cnt; |
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} |
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|
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/* write 0 to base address */ |
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addr = base; |
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save[i] = *addr; |
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*addr = 0; |
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|
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/* check at base address */ |
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if ((val = *addr) != 0) { |
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*addr = save[i]; |
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return (0); |
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} |
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|
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for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { |
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addr = base + cnt; /* pointer arith! */ |
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|
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val = *addr; |
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*addr = save[--i]; |
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|
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if (val != (~cnt)) { |
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return (cnt * sizeof (long)); |
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} |
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} |
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return (maxsize); |
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} |
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|
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/* ------------------------------------------------------------------------- */ |
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|
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#ifndef PB_ENET_TENA |
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# define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ |
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#endif |
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|
||||
/***********************************************************************
|
||||
F* Function: int board_pre_init (void) P*A*Z* |
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* |
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P* Parameters: none |
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P* |
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P* Returnvalue: int |
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P* - 0 is always returned. |
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* |
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Z* Intention: This function is the board_pre_init() method implementation |
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Z* for the lwmon board. |
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Z* Disable Ethernet TENA on Port B. |
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* |
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D* Design: wd@denx.de |
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C* Coding: wd@denx.de |
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V* Verification: dzu@denx.de |
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***********************************************************************/ |
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int board_pre_init (void) |
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{ |
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volatile immap_t *immr = (immap_t *) CFG_IMMR; |
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|
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/* Disable Ethernet TENA on Port B
|
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* Necessary because of pull up in COM3 port. |
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* |
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* This is just a preliminary fix, intended to turn off TENA |
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* as soon as possible to avoid noise on the network. Once |
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* I²C is running we will make sure the interface is |
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* correctly initialized. |
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*/ |
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immr->im_cpm.cp_pbpar &= ~PB_ENET_TENA; |
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immr->im_cpm.cp_pbodr &= ~PB_ENET_TENA; |
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immr->im_cpm.cp_pbdat &= ~PB_ENET_TENA; /* set to 0 = disabled */ |
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immr->im_cpm.cp_pbdir |= PB_ENET_TENA; |
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return (0); |
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} |
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|
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/* ------------------------------------------------------------------------- */ |
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|
||||
/***********************************************************************
|
||||
F* Function: void reset_phy (void) P*A*Z* |
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* |
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P* Parameters: none |
||||
P* |
||||
P* Returnvalue: none |
||||
* |
||||
Z* Intention: Reset the PHY. In the lwmon case we do this by the |
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Z* signaling the PIC I/O expander. |
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* |
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D* Design: wd@denx.de |
||||
C* Coding: wd@denx.de |
||||
V* Verification: dzu@denx.de |
||||
***********************************************************************/ |
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void reset_phy (void) |
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{ |
||||
uchar c; |
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|
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#ifdef DEBUG |
||||
printf ("### Switch on Ethernet for SCC2 ###\n"); |
||||
#endif |
||||
c = pic_read (0x61); |
||||
#ifdef DEBUG |
||||
printf ("Old PIC read: reg_61 = 0x%02x\n", c); |
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#endif |
||||
c |= 0x40; /* disable COM3 */ |
||||
c &= ~0x80; /* enable Ethernet */ |
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pic_write (0x61, c); |
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#ifdef DEBUG |
||||
c = pic_read (0x61); |
||||
printf ("New PIC read: reg_61 = 0x%02x\n", c); |
||||
#endif |
||||
udelay (1000); |
||||
} |
||||
|
||||
|
||||
/*------------------------- Keyboard controller -----------------------*/ |
||||
/* command codes */ |
||||
#define KEYBD_CMD_READ_KEYS 0x01 |
||||
#define KEYBD_CMD_READ_VERSION 0x02 |
||||
#define KEYBD_CMD_READ_STATUS 0x03 |
||||
#define KEYBD_CMD_RESET_ERRORS 0x10 |
||||
|
||||
/* status codes */ |
||||
#define KEYBD_STATUS_MASK 0x3F |
||||
#define KEYBD_STATUS_H_RESET 0x20 |
||||
#define KEYBD_STATUS_BROWNOUT 0x10 |
||||
#define KEYBD_STATUS_WD_RESET 0x08 |
||||
#define KEYBD_STATUS_OVERLOAD 0x04 |
||||
#define KEYBD_STATUS_ILLEGAL_WR 0x02 |
||||
#define KEYBD_STATUS_ILLEGAL_RD 0x01 |
||||
|
||||
/* Number of bytes returned from Keyboard Controller */ |
||||
#define KEYBD_VERSIONLEN 2 /* version information */ |
||||
#define KEYBD_DATALEN 9 /* normal key scan data */ |
||||
|
||||
/* maximum number of "magic" key codes that can be assigned */ |
||||
|
||||
static uchar kbd_addr = CFG_I2C_KEYBD_ADDR; |
||||
|
||||
static uchar *key_match (uchar *); |
||||
|
||||
#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */ |
||||
|
||||
/***********************************************************************
|
||||
F* Function: int misc_init_r (void) P*A*Z* |
||||
* |
||||
P* Parameters: none |
||||
P* |
||||
P* Returnvalue: int |
||||
P* - 0 is always returned, even in the case of a keyboard |
||||
P* error. |
||||
* |
||||
Z* Intention: This function is the misc_init_r() method implementation |
||||
Z* for the lwmon board. |
||||
Z* The keyboard controller is initialized and the result |
||||
Z* of a read copied to the environment variable "keybd". |
||||
Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for |
||||
Z* this key, and if found display to the LCD will be enabled. |
||||
Z* The keys in "keybd" are checked against the magic |
||||
Z* keycommands defined in the environment. |
||||
Z* See also key_match(). |
||||
* |
||||
D* Design: wd@denx.de |
||||
C* Coding: wd@denx.de |
||||
V* Verification: dzu@denx.de |
||||
***********************************************************************/ |
||||
int misc_init_r (void) |
||||
{ |
||||
uchar kbd_data[KEYBD_DATALEN]; |
||||
uchar tmp_data[KEYBD_DATALEN]; |
||||
uchar keybd_env[2 * KEYBD_DATALEN + 1]; |
||||
uchar val, errcd; |
||||
uchar *str; |
||||
int i; |
||||
|
||||
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); |
||||
|
||||
/* Read initial keyboard error code */ |
||||
val = KEYBD_CMD_READ_STATUS; |
||||
i2c_write (kbd_addr, 0, 0, &val, 1); |
||||
i2c_read (kbd_addr, 0, 0, &errcd, 1); |
||||
/* clear unused bits */ |
||||
errcd &= KEYBD_STATUS_MASK; |
||||
/* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */ |
||||
errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT); |
||||
if (errcd) { |
||||
printf ("KEYBD: Error %02X\n", errcd); |
||||
} |
||||
/* Reset error code and verify */ |
||||
val = KEYBD_CMD_RESET_ERRORS; |
||||
i2c_write (kbd_addr, 0, 0, &val, 1); |
||||
udelay(1000); /* delay NEEDED by keyboard PIC !!! */ |
||||
|
||||
val = KEYBD_CMD_READ_STATUS; |
||||
i2c_write (kbd_addr, 0, 0, &val, 1); |
||||
i2c_read (kbd_addr, 0, 0, &val, 1); |
||||
|
||||
val &= KEYBD_STATUS_MASK; /* clear unused bits */ |
||||
if (val) { /* permanent error, report it */ |
||||
printf ("*** Keyboard error code %02X ***\n", val); |
||||
sprintf (keybd_env, "%02X", val); |
||||
setenv ("keybd", keybd_env); |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Now we know that we have a working keyboard, so disable |
||||
* all output to the LCD except when a key press is detected. |
||||
*/ |
||||
|
||||
if ((console_assign (stdout, "serial") < 0) || |
||||
(console_assign (stderr, "serial") < 0)) { |
||||
printf ("Can't assign serial port as output device\n"); |
||||
} |
||||
|
||||
/* Read Version */ |
||||
val = KEYBD_CMD_READ_VERSION; |
||||
i2c_write (kbd_addr, 0, 0, &val, 1); |
||||
i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN); |
||||
printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]); |
||||
|
||||
/*
|
||||
* Read current keyboard state. |
||||
* |
||||
* After the error reset it may take some time before the |
||||
* keyboard PIC picks up a valid keyboard scan - the total |
||||
* scan time is approx. 1.6 ms (information by Martin Rajek, |
||||
* 28 Sep 2002). We read a couple of times for the keyboard |
||||
* to stabilize, using a big enough delay. |
||||
* 10 times should be enough. If the data is still changing, |
||||
* we use what we get :-( |
||||
*/ |
||||
|
||||
memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */ |
||||
for (i=0; i<10; ++i) { |
||||
val = KEYBD_CMD_READ_KEYS; |
||||
i2c_write (kbd_addr, 0, 0, &val, 1); |
||||
i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); |
||||
|
||||
if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) { |
||||
/* consistent state, done */ |
||||
break; |
||||
} |
||||
/* remeber last state, delay, and retry */ |
||||
memcpy (tmp_data, kbd_data, KEYBD_DATALEN); |
||||
udelay (5000); |
||||
} |
||||
|
||||
for (i = 0; i < KEYBD_DATALEN; ++i) { |
||||
sprintf (keybd_env + i + i, "%02X", kbd_data[i]); |
||||
} |
||||
setenv ("keybd", keybd_env); |
||||
|
||||
str = strdup (key_match (kbd_data)); /* decode keys */ |
||||
#ifdef KEYBD_SET_DEBUGMODE |
||||
if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */ |
||||
if ((console_assign (stdout, "lcd") < 0) || |
||||
(console_assign (stderr, "lcd") < 0)) { |
||||
printf ("Can't assign LCD display as output device\n"); |
||||
} |
||||
} |
||||
#endif /* KEYBD_SET_DEBUGMODE */ |
||||
#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ |
||||
setenv ("preboot", str); /* set or delete definition */ |
||||
#endif /* CONFIG_PREBOOT */ |
||||
if (str != NULL) { |
||||
free (str); |
||||
} |
||||
return (0); |
||||
} |
||||
|
||||
#ifdef CONFIG_PREBOOT |
||||
|
||||
static uchar kbd_magic_prefix[] = "key_magic"; |
||||
static uchar kbd_command_prefix[] = "key_cmd"; |
||||
|
||||
/***********************************************************************
|
||||
F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z* |
||||
* |
||||
P* Parameters: uchar *kbd_data |
||||
P* - The keys to match against our magic definitions |
||||
P* |
||||
P* Returnvalue: uchar * |
||||
P* - != NULL: Pointer to the corresponding command(s) |
||||
P* NULL: No magic is about to happen |
||||
* |
||||
Z* Intention: Check if pressed key(s) match magic sequence, |
||||
Z* and return the command string associated with that key(s). |
||||
Z* |
||||
Z* If no key press was decoded, NULL is returned. |
||||
Z* |
||||
Z* Note: the first character of the argument will be |
||||
Z* overwritten with the "magic charcter code" of the |
||||
Z* decoded key(s), or '\0'. |
||||
Z* |
||||
Z* Note: the string points to static environment data |
||||
Z* and must be saved before you call any function that |
||||
Z* modifies the environment. |
||||
* |
||||
D* Design: wd@denx.de |
||||
C* Coding: wd@denx.de |
||||
V* Verification: dzu@denx.de |
||||
***********************************************************************/ |
||||
static uchar *key_match (uchar *kbd_data) |
||||
{ |
||||
uchar compare[KEYBD_DATALEN-1]; |
||||
uchar magic[sizeof (kbd_magic_prefix) + 1]; |
||||
uchar extra; |
||||
uchar *str, *nxt, *suffix; |
||||
uchar *kbd_magic_keys; |
||||
int i; |
||||
|
||||
/*
|
||||
* The following string defines the characters that can pe appended |
||||
* to "key_magic" to form the names of environment variables that |
||||
* hold "magic" key codes, i. e. such key codes that can cause |
||||
* pre-boot actions. If the string is empty (""), then only |
||||
* "key_magic" is checked (old behaviour); the string "125" causes |
||||
* checks for "key_magic1", "key_magic2" and "key_magic5", etc. |
||||
*/ |
||||
if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) |
||||
kbd_magic_keys = ""; |
||||
|
||||
/* loop over all magic keys;
|
||||
* use '\0' suffix in case of empty string |
||||
*/ |
||||
for (suffix=kbd_magic_keys; *suffix || suffix==kbd_magic_keys; ++suffix) { |
||||
sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); |
||||
#if 0 |
||||
printf ("### Check magic \"%s\"\n", magic); |
||||
#endif |
||||
/* Don't include modifier byte */ |
||||
memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); |
||||
|
||||
extra = 0; |
||||
|
||||
for (str= getenv(magic); str != NULL; str = (*nxt) ? nxt+1 : nxt) { |
||||
uchar c; |
||||
int k; |
||||
|
||||
c = (uchar) simple_strtoul (str, (char **) (&nxt), 16); |
||||
|
||||
if (str == nxt) { /* invalid character */ |
||||
break; |
||||
} |
||||
|
||||
/*
|
||||
* Check if this key matches the input. |
||||
* Set matches to zero, so they match only once |
||||
* and we can find duplicates or extra keys |
||||
*/ |
||||
for (k = 0; k < sizeof(compare); ++k) { |
||||
if (compare[k] == '\0') /* only non-zero entries */ |
||||
continue; |
||||
if (c == compare[k]) { /* found matching key */ |
||||
compare[k] = '\0'; |
||||
break; |
||||
} |
||||
} |
||||
if (k == sizeof(compare)) { |
||||
extra = 1; /* unmatched key */ |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* A full match leaves no keys in the `compare' array, |
||||
* and has no extra keys |
||||
*/ |
||||
|
||||
for (i = 0; i < sizeof(compare); ++i) { |
||||
if (compare[i]) |
||||
break; |
||||
} |
||||
|
||||
if ((i == sizeof(compare)) && (extra == 0)) { |
||||
uchar cmd_name[sizeof (kbd_command_prefix) + 1]; |
||||
char *cmd; |
||||
|
||||
sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); |
||||
|
||||
cmd = getenv (cmd_name); |
||||
#if 0 |
||||
printf ("### Set PREBOOT to $(%s): \"%s\"\n", |
||||
cmd_name, cmd ? cmd : "<<NULL>>"); |
||||
#endif |
||||
*kbd_data = *suffix; |
||||
return (cmd); |
||||
} |
||||
} |
||||
#if 0 |
||||
printf ("### Delete PREBOOT\n"); |
||||
#endif |
||||
*kbd_data = '\0'; |
||||
return (NULL); |
||||
} |
||||
#endif /* CONFIG_PREBOOT */ |
||||
|
||||
/*---------------Board Special Commands: PIC read/write ---------------*/ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_BSP) |
||||
/***********************************************************************
|
||||
F* Function: int do_pic (cmd_tbl_t *cmdtp, int flag, |
||||
F* int argc, char *argv[]) P*A*Z* |
||||
* |
||||
P* Parameters: cmd_tbl_t *cmdtp |
||||
P* - Pointer to our command table entry |
||||
P* int flag |
||||
P* - If the CMD_FLAG_REPEAT bit is set, then this call is |
||||
P* a repetition |
||||
P* int argc |
||||
P* - Argument count |
||||
P* char *argv[] |
||||
P* - Array of the actual arguments |
||||
P* |
||||
P* Returnvalue: int |
||||
P* - 0 The command was handled successfully |
||||
P* 1 An error occurred |
||||
* |
||||
Z* Intention: Implement the "pic [read|write]" commands. |
||||
Z* The read subcommand takes one argument, the register, |
||||
Z* whereas the write command takes two, the register and |
||||
Z* the new value. |
||||
* |
||||
D* Design: wd@denx.de |
||||
C* Coding: wd@denx.de |
||||
V* Verification: dzu@denx.de |
||||
***********************************************************************/ |
||||
int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
uchar reg, val; |
||||
|
||||
switch (argc) { |
||||
case 3: /* PIC read reg */ |
||||
if (strcmp (argv[1], "read") != 0) |
||||
break; |
||||
|
||||
reg = simple_strtoul (argv[2], NULL, 16); |
||||
|
||||
printf ("PIC read: reg %02x: %02x\n\n", reg, pic_read (reg)); |
||||
|
||||
return 0; |
||||
case 4: /* PIC write reg val */ |
||||
if (strcmp (argv[1], "write") != 0) |
||||
break; |
||||
|
||||
reg = simple_strtoul (argv[2], NULL, 16); |
||||
val = simple_strtoul (argv[3], NULL, 16); |
||||
|
||||
printf ("PIC write: reg %02x val 0x%02x: %02x => ", |
||||
reg, val, pic_read (reg)); |
||||
pic_write (reg, val); |
||||
printf ("%02x\n\n", pic_read (reg)); |
||||
return 0; |
||||
default: |
||||
break; |
||||
} |
||||
printf ("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
|
||||
/***********************************************************************
|
||||
F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag, |
||||
F* int argc, char *argv[]) P*A*Z* |
||||
* |
||||
P* Parameters: cmd_tbl_t *cmdtp |
||||
P* - Pointer to our command table entry |
||||
P* int flag |
||||
P* - If the CMD_FLAG_REPEAT bit is set, then this call is |
||||
P* a repetition |
||||
P* int argc |
||||
P* - Argument count |
||||
P* char *argv[] |
||||
P* - Array of the actual arguments |
||||
P* |
||||
P* Returnvalue: int |
||||
P* - 0 is always returned. |
||||
* |
||||
Z* Intention: Implement the "kbd" command. |
||||
Z* The keyboard status is read. The result is printed on |
||||
Z* the console and written into the "keybd" environment |
||||
Z* variable. |
||||
* |
||||
D* Design: wd@denx.de |
||||
C* Coding: wd@denx.de |
||||
V* Verification: dzu@denx.de |
||||
***********************************************************************/ |
||||
int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
uchar kbd_data[KEYBD_DATALEN]; |
||||
uchar keybd_env[2 * KEYBD_DATALEN + 1]; |
||||
uchar val; |
||||
int i; |
||||
|
||||
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); |
||||
|
||||
/* Read keys */ |
||||
val = KEYBD_CMD_READ_KEYS; |
||||
i2c_write (kbd_addr, 0, 0, &val, 1); |
||||
i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); |
||||
|
||||
puts ("Keys:"); |
||||
for (i = 0; i < KEYBD_DATALEN; ++i) { |
||||
sprintf (keybd_env + i + i, "%02X", kbd_data[i]); |
||||
printf (" %02x", kbd_data[i]); |
||||
} |
||||
putc ('\n'); |
||||
setenv ("keybd", keybd_env); |
||||
return 0; |
||||
} |
||||
|
||||
/* Read and set LSB switch */ |
||||
#define CFG_PC_TXD1_ENA 0x0008 |
||||
|
||||
/***********************************************************************
|
||||
F* Function: int do_lsb (cmd_tbl_t *cmdtp, int flag, |
||||
F* int argc, char *argv[]) P*A*Z* |
||||
* |
||||
P* Parameters: cmd_tbl_t *cmdtp |
||||
P* - Pointer to our command table entry |
||||
P* int flag |
||||
P* - If the CMD_FLAG_REPEAT bit is set, then this call is |
||||
P* a repetition |
||||
P* int argc |
||||
P* - Argument count |
||||
P* char *argv[] |
||||
P* - Array of the actual arguments |
||||
P* |
||||
P* Returnvalue: int |
||||
P* - 0 The command was handled successfully |
||||
P* 1 An error occurred |
||||
* |
||||
Z* Intention: Implement the "lsb [on|off]" commands. |
||||
Z* The lsb is switched according to the first parameter by |
||||
Z* by signaling the PIC I/O expander. |
||||
Z* Called with no arguments, the current setting is |
||||
Z* printed. |
||||
* |
||||
D* Design: wd@denx.de |
||||
C* Coding: wd@denx.de |
||||
V* Verification: dzu@denx.de |
||||
***********************************************************************/ |
||||
int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
uchar val; |
||||
immap_t *immr = (immap_t *) CFG_IMMR; |
||||
|
||||
switch (argc) { |
||||
case 1: /* lsb - print setting */ |
||||
val = pic_read (0x60); |
||||
printf ("LSB is o%s\n", (val & 0x20) ? "n" : "ff"); |
||||
return 0; |
||||
case 2: /* lsb on or lsb off - set switch */ |
||||
val = pic_read (0x60); |
||||
|
||||
if (strcmp (argv[1], "on") == 0) { |
||||
val |= 0x20; |
||||
immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA); |
||||
immr->im_ioport.iop_pcdat |= CFG_PC_TXD1_ENA; |
||||
immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA; |
||||
} else if (strcmp (argv[1], "off") == 0) { |
||||
val &= ~0x20; |
||||
immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA); |
||||
immr->im_ioport.iop_pcdat &= ~(CFG_PC_TXD1_ENA); |
||||
immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA; |
||||
} else { |
||||
break; |
||||
} |
||||
pic_write (0x60, val); |
||||
return 0; |
||||
default: |
||||
break; |
||||
} |
||||
printf ("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
|
||||
#endif /* CFG_CMD_BSP */ |
||||
|
||||
/*----------------------------- Utilities -----------------------------*/ |
||||
/***********************************************************************
|
||||
F* Function: uchar pic_read (uchar reg) P*A*Z* |
||||
* |
||||
P* Parameters: uchar reg |
||||
P* - Register to read |
||||
P* |
||||
P* Returnvalue: uchar |
||||
P* - Value read from register |
||||
* |
||||
Z* Intention: Read a register from the PIC I/O expander. |
||||
* |
||||
D* Design: wd@denx.de |
||||
C* Coding: wd@denx.de |
||||
V* Verification: dzu@denx.de |
||||
***********************************************************************/ |
||||
uchar pic_read (uchar reg) |
||||
{ |
||||
return (i2c_reg_read (CFG_I2C_PICIO_ADDR, reg)); |
||||
} |
||||
|
||||
/***********************************************************************
|
||||
F* Function: void pic_write (uchar reg, uchar val) P*A*Z* |
||||
* |
||||
P* Parameters: uchar reg |
||||
P* - Register to read |
||||
P* uchar val |
||||
P* - Value to write |
||||
P* |
||||
P* Returnvalue: none |
||||
* |
||||
Z* Intention: Write to a register on the PIC I/O expander. |
||||
* |
||||
D* Design: wd@denx.de |
||||
C* Coding: wd@denx.de |
||||
V* Verification: dzu@denx.de |
||||
***********************************************************************/ |
||||
void pic_write (uchar reg, uchar val) |
||||
{ |
||||
i2c_reg_write (CFG_I2C_PICIO_ADDR, reg, val); |
||||
} |
||||
|
||||
/*---------------------- Board Control Functions ----------------------*/ |
||||
/***********************************************************************
|
||||
F* Function: void board_poweroff (void) P*A*Z* |
||||
* |
||||
P* Parameters: none |
||||
P* |
||||
P* Returnvalue: none |
||||
* |
||||
Z* Intention: Turn off the battery power and loop endless, so this |
||||
Z* should better be the last function you call... |
||||
* |
||||
D* Design: wd@denx.de |
||||
C* Coding: wd@denx.de |
||||
V* Verification: dzu@denx.de |
||||
***********************************************************************/ |
||||
void board_poweroff (void) |
||||
{ |
||||
/* Turn battery off */ |
||||
((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~(1 << (31 - 13)); |
||||
|
||||
while (1); |
||||
} |
@ -0,0 +1,301 @@ |
||||
U-Boot for a Musenki M-3/M-1 board |
||||
--------------------------- |
||||
|
||||
Musenki M-1 and M-3 have two banks of flash of 4MB or 8MB each. |
||||
|
||||
In board's notation, bank 0 is the one at the address of 0xFF800000 |
||||
and bank 1 is the one at the address of 0xFF000000. |
||||
|
||||
On power-up the processor jumps to the address of 0xFFF00100, the last |
||||
megabyte of the bank 0 of flash. |
||||
|
||||
Thus, U-Boot is configured to reside in flash starting at the address of |
||||
0xFFF00000. The environment space is located in flash separately from |
||||
U-Boot, at the address of 0xFF800000. |
||||
|
||||
There is a Davicom 9102A on-board, but I don't have it working yet. |
||||
|
||||
U-Boot test results |
||||
-------------------- |
||||
|
||||
x.x Operation on all available serial consoles |
||||
|
||||
x.x.x CONFIG_CONS_INDEX 1 |
||||
|
||||
|
||||
U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) |
||||
|
||||
CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache |
||||
Board: MUSENKI Local Bus at 100 MHz |
||||
DRAM: 32 MB |
||||
FLASH: 4 MB |
||||
In: serial |
||||
Out: serial |
||||
Err: serial |
||||
Hit any key to stop autoboot: 0 |
||||
=> help |
||||
autoscr - run script from memory |
||||
base - print or set address offset |
||||
bdinfo - print Board Info structure |
||||
bootm - boot application image from memory |
||||
bootp - boot image via network using BootP/TFTP protocol |
||||
bootd - boot default, i.e., run 'bootcmd' |
||||
cmp - memory compare |
||||
coninfo - print console devices and informations |
||||
cp - memory copy |
||||
crc32 - checksum calculation |
||||
dcache - enable or disable data cache |
||||
echo - echo args to console |
||||
erase - erase FLASH memory |
||||
flinfo - print FLASH memory information |
||||
go - start application at address 'addr' |
||||
help - print online help |
||||
icache - enable or disable instruction cache |
||||
iminfo - print header information for application image |
||||
loadb - load binary file over serial line (kermit mode) |
||||
loads - load S-Record file over serial line |
||||
loop - infinite loop on address range |
||||
md - memory display |
||||
mm - memory modify (auto-incrementing) |
||||
mtest - simple RAM test |
||||
mw - memory write (fill) |
||||
nm - memory modify (constant address) |
||||
printenv- print environment variables |
||||
protect - enable or disable FLASH write protection |
||||
rarpboot- boot image via network using RARP/TFTP protocol |
||||
reset - Perform RESET of the CPU |
||||
run - run commands in an environment variable |
||||
saveenv - save environment variables to persistent storage |
||||
setenv - set environment variables |
||||
tftpboot- boot image via network using TFTP protocol |
||||
and env variables ipaddr and serverip |
||||
version - print monitor version |
||||
? - alias for 'help' |
||||
|
||||
|
||||
|
||||
x.x.x CONFIG_CONS_INDEX 2 |
||||
|
||||
**** NOT TESTED **** |
||||
|
||||
x.x Flash Driver Operation |
||||
|
||||
|
||||
Boot 1.1.1 (Nov 20 2001 - 15:55:32) |
||||
|
||||
CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache |
||||
Board: MUSENKI Local Bus at 100 MHz |
||||
DRAM: 32 MB |
||||
FLASH: 4 MB |
||||
*** Warning - bad CRC, using default environment |
||||
|
||||
In: serial |
||||
Out: serial |
||||
Err: serial |
||||
Hit any key to stop autoboot: 0 |
||||
=> |
||||
=> md ff800000 |
||||
ff800000: 46989bf8 626f6f74 636d643d 626f6f74 F...bootcmd=boot |
||||
ff800010: 6d204646 38323030 30300062 6f6f7464 m FF820000.bootd |
||||
ff800020: 656c6179 3d350062 61756472 6174653d elay=5.baudrate= |
||||
ff800030: 39363030 00636c6f 636b735f 696e5f6d 9600.clocks_in_m |
||||
ff800040: 687a3d31 00737464 696e3d73 65726961 hz=1.stdin=seria |
||||
ff800050: 6c007374 646f7574 3d736572 69616c00 l.stdout=serial. |
||||
ff800060: 73746465 72723d73 65726961 6c006970 stderr=serial.ip |
||||
ff800070: 61646472 3d313932 2e313638 2e302e34 addr=192.168.0.4 |
||||
ff800080: 32007365 72766572 69703d31 39322e31 2.serverip=192.1 |
||||
ff800090: 36382e30 2e380000 00000000 00000000 68.0.8.......... |
||||
ff8000a0: 00000000 00000000 00000000 00000000 ................ |
||||
ff8000b0: 00000000 00000000 00000000 00000000 ................ |
||||
ff8000c0: 00000000 00000000 00000000 00000000 ................ |
||||
ff8000d0: 00000000 00000000 00000000 00000000 ................ |
||||
ff8000e0: 00000000 00000000 00000000 00000000 ................ |
||||
ff8000f0: 00000000 00000000 00000000 00000000 ................ |
||||
=> protect off ff800000 ff81ffff |
||||
Un-Protected 1 sectors |
||||
=> erase ff800000 ff81ffff |
||||
Erase Flash from 0xff800000 to 0xff81ffff |
||||
done |
||||
Erased 1 sectors |
||||
=> md ff800000 |
||||
ff800000: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff800010: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff800020: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff800030: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff800040: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff800050: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff800060: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff800070: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff800080: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff800090: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff8000a0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff8000b0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff8000c0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff8000d0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff8000e0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff8000f0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
|
||||
x.x.x Information |
||||
|
||||
|
||||
U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) |
||||
|
||||
CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache |
||||
Board: MUSENKI Local Bus at 100 MHz |
||||
DRAM: 32 MB |
||||
FLASH: 4 MB |
||||
*** Warning - bad CRC, using default environment |
||||
|
||||
In: serial |
||||
Out: serial |
||||
Err: serial |
||||
Hit any key to stop autoboot: 0 |
||||
=> flinfo |
||||
|
||||
Bank # 1: Intel 28F320J3A (32Mbit = 128K x 32) |
||||
Size: 4 MB in 32 Sectors |
||||
Sector Start Addresses: |
||||
FF800000 (RO) FF820000 FF840000 FF860000 FF880000 |
||||
FF8A0000 FF8C0000 FF8E0000 FF900000 FF920000 |
||||
FF940000 FF960000 FF980000 FF9A0000 FF9C0000 |
||||
FF9E0000 FFA00000 FFA20000 FFA40000 FFA60000 |
||||
FFA80000 FFAA0000 FFAC0000 FFAE0000 FFB00000 |
||||
FFB20000 FFB40000 FFB60000 FFB80000 FFBA0000 |
||||
FFBC0000 FFBE0000 |
||||
|
||||
Bank # 2: missing or unknown FLASH type |
||||
=> |
||||
|
||||
|
||||
|
||||
x.x.x Flash Programming |
||||
|
||||
|
||||
U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) |
||||
|
||||
CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache |
||||
Board: MUSENKI Local Bus at 100 MHz |
||||
DRAM: 32 MB |
||||
FLASH: 4 MB |
||||
|
||||
In: serial |
||||
Out: serial |
||||
Err: serial |
||||
Hit any key to stop autoboot: 0 |
||||
=> |
||||
=> |
||||
=> |
||||
=> protect off ff800000 ff81ffff |
||||
Un-Protected 1 sectors |
||||
=> cp 0 ff800000 20 |
||||
Copy to Flash... done |
||||
=> md ff800000 |
||||
ff800000: 37ce33ec 33cc334c 33c031cc 33cc35cc 7.3.3.3L3.1.3.5. |
||||
ff800010: 33ec13ce 30ccb3ec b3c833c4 31c836cc 3...0.....3.1.6. |
||||
ff800020: 33cc3b9d 31ec33ee 13ecf3cc 338833ec 3.;.1.3.....3.3. |
||||
ff800030: 234c33ec 32cc22cc 33883bdc 534433cc #L3.2.".3.;.SD3. |
||||
ff800040: 33cc30c8 31cc32ec 338c33cc 330c33dc 3.0.1.2.3.3.3.3. |
||||
ff800050: 33cc13dc 334c534c b1c433d8 128c13cc 3...3LSL..3..... |
||||
ff800060: 37ec36cd 33dc33cc bbc9f7e8 bbcc77cc 7.6.3.3.......w. |
||||
ff800070: 314c0adc 139c30ed 33cc334c 33c833ec 1L....0.3.3L3.3. |
||||
ff800080: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff800090: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff8000a0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff8000b0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff8000c0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff8000d0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff8000e0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
ff8000f0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
|
||||
|
||||
x.x.x Storage of environment variables in flash |
||||
|
||||
|
||||
U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) |
||||
|
||||
CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache |
||||
Board: MUSENKI Local Bus at 100 MHz |
||||
DRAM: 32 MB |
||||
FLASH: 4 MB |
||||
In: serial |
||||
Out: serial |
||||
Err: serial |
||||
Hit any key to stop autoboot: 0 |
||||
=> printenv |
||||
bootcmd=bootm FF820000 |
||||
bootdelay=5 |
||||
baudrate=9600 |
||||
clocks_in_mhz=1 |
||||
stdin=serial |
||||
stdout=serial |
||||
stderr=serial |
||||
|
||||
Environment size: 106/16380 bytes |
||||
=> setenv myvar 1234 |
||||
=> saveenv |
||||
Un-Protected 1 sectors |
||||
Erasing Flash... |
||||
done |
||||
Erased 1 sectors |
||||
Saving Environment to Flash... |
||||
Protected 1 sectors |
||||
=> reset |
||||
|
||||
|
||||
U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) |
||||
|
||||
CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache |
||||
Board: MUSENKI Local Bus at 100 MHz |
||||
DRAM: 32 MB |
||||
FLASH: 4 MB |
||||
In: serial |
||||
Out: serial |
||||
Err: serial |
||||
Hit any key to stop autoboot: 0 |
||||
=> printenv |
||||
bootcmd=bootm FF820000 |
||||
bootdelay=5 |
||||
baudrate=9600 |
||||
clocks_in_mhz=1 |
||||
myvar=1234 |
||||
stdin=serial |
||||
stdout=serial |
||||
stderr=serial |
||||
|
||||
Environment size: 117/16380 bytes |
||||
|
||||
x.x Image Download and run over serial port |
||||
|
||||
|
||||
U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) |
||||
|
||||
CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache |
||||
Board: MUSENKI Local Bus at 100 MHz |
||||
DRAM: 32 MB |
||||
FLASH: 4 MB |
||||
In: serial |
||||
Out: serial |
||||
Err: serial |
||||
Hit any key to stop autoboot: 0 |
||||
=> loads |
||||
## Ready for S-Record download ... |
||||
|
||||
## First Load Addr = 0x00040000 |
||||
## Last Load Addr = 0x00050177 |
||||
## Total Size = 0x00010178 = 65912 Bytes |
||||
## Start Addr = 0x00040004 |
||||
=> go 40004 |
||||
## Starting application at 0x00040004 ... |
||||
Hello World |
||||
argc = 1 |
||||
argv[0] = "40004" |
||||
argv[1] = "<NULL>" |
||||
Hit any key to exit ... |
||||
|
||||
## Application terminated, rc = 0x0 |
||||
|
||||
|
||||
x.x Image download and run over ethernet interface |
||||
|
||||
untested (not working yet, actually) |
||||
|
@ -0,0 +1,132 @@ |
||||
/* |
||||
* (C) Copyright 2001 |
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* |
||||
* u-boot.lds - linker script for U-Boot on the Galileo Eval Board. |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/74xx_7xx/start.o (.text) |
||||
|
||||
/* store the environment in a seperate sector in the boot flash */ |
||||
/* . = env_offset; */ |
||||
/* common/environment.o(.text) */ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,42 @@ |
||||
#
|
||||
# (C) Copyright 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# PM826 boards
|
||||
#
|
||||
|
||||
# This should be equal to the CFG_FLASH_BASE or
|
||||
# CFG_BOOTROM_BASE define in config_PM826.h
|
||||
# for the "final" configuration, with U-Boot
|
||||
# in flash, or the address in RAM where
|
||||
# U-Boot is loaded at for debugging.
|
||||
#
|
||||
|
||||
ifeq ($(CONFIG_BOOT_ROM),y) |
||||
TEXT_BASE := 0x60000000
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
|
||||
else |
||||
TEXT_BASE := 0x40000000
|
||||
endif |
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
|
@ -0,0 +1,30 @@ |
||||
Hi, |
||||
|
||||
so this is the port to the Embedded Planet RPX Super Board. |
||||
|
||||
ATTENTION |
||||
This code is only tested on the AY-Version, which is an early release with some |
||||
hardware bugs. The main problem is that this board uses the default Hard Reset |
||||
Configuration Word and not the 4 bytes located at start of FLASH because at |
||||
0xFE000000 is no FLASH. The FLASH consists out of 4 chips each 16bits wide. Be |
||||
carefull, the bytes are swapped. So DQ0-7 is the high byte, DQ8-15 ist the low |
||||
byte. |
||||
|
||||
The icache can only manually be enabled after reset. |
||||
The FLASH and main SDRAM is working with icache enabled. |
||||
The local SDRAM can only be used as data memory when icache is enabled. |
||||
If U-Boot runs in local SDRAM, TFTP does not work. |
||||
The functions in mii_phy.c are all working. Call mii_phy_discover() out of |
||||
eth_init() and solve the linker error. |
||||
I2C, RTC/NVRAM and PCMCIA are not working yet. |
||||
|
||||
TODO |
||||
The 32MB local SDRAM is working but not shown in the startup messages of |
||||
U-Boot. If you locate U-Boot or any other program to this area it won't run. |
||||
Turning the ichache off does not solve this problem. |
||||
|
||||
As I won't buy another RPX Super there might be some little work to do for you |
||||
getting this U-Boot port running on the final board. |
||||
|
||||
|
||||
frank.morauf@salzbrenner.com |
@ -0,0 +1,34 @@ |
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Siemens SCM boards
|
||||
#
|
||||
|
||||
# This should be equal to the CFG_FLASH_BASE define in config_SCM.h
|
||||
# for the "final" configuration, with U-Boot in flash, or the address
|
||||
# in RAM where U-Boot is loaded at for debugging.
|
||||
#
|
||||
TEXT_BASE = 0x40000000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
|
@ -0,0 +1,34 @@ |
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# TQM8260 boards
|
||||
#
|
||||
|
||||
# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h
|
||||
# for the "final" configuration, with U-Boot in flash, or the address
|
||||
# in RAM where U-Boot is loaded at for debugging.
|
||||
#
|
||||
TEXT_BASE = 0x40000000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
|
@ -0,0 +1,351 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
/*
|
||||
* Generic FPGA support |
||||
*/ |
||||
#include <common.h> /* core U-Boot definitions */ |
||||
#include <xilinx.h> /* xilinx specific definitions */ |
||||
#include <altera.h> /* altera specific definitions */ |
||||
|
||||
#if defined(CONFIG_FPGA) |
||||
|
||||
#if 0 |
||||
#define FPGA_DEBUG /* define FPGA_DEBUG to get debug messages */ |
||||
#endif |
||||
|
||||
/* Local definitions */ |
||||
#ifndef CONFIG_MAX_FPGA_DEVICES |
||||
#define CONFIG_MAX_FPGA_DEVICES 5 |
||||
#endif |
||||
|
||||
/* Enable/Disable debug console messages */ |
||||
#ifdef FPGA_DEBUG |
||||
#define PRINTF(fmt,args...) printf (fmt ,##args) |
||||
#else |
||||
#define PRINTF(fmt,args...) |
||||
#endif |
||||
|
||||
/* Local static data */ |
||||
static ulong relocation_offset = 0; |
||||
static int next_desc = FPGA_INVALID_DEVICE; |
||||
static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; |
||||
|
||||
/* Local static functions */ |
||||
static const fpga_desc * const fpga_get_desc( int devnum ); |
||||
static const fpga_desc * const fpga_validate( int devnum, void *buf, |
||||
size_t bsize, char *fn ); |
||||
static int fpga_dev_info( int devnum ); |
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/* fpga_no_sup
|
||||
* 'no support' message function |
||||
*/ |
||||
static void fpga_no_sup( char *fn, char *msg ) |
||||
{ |
||||
if ( fn && msg ) { |
||||
printf( "%s: No support for %s. CONFIG_FPGA defined as 0x%x.\n", |
||||
fn, msg, CONFIG_FPGA ); |
||||
} else if ( msg ) { |
||||
printf( "No support for %s. CONFIG_FPGA defined as 0x%x.\n", |
||||
msg, CONFIG_FPGA ); |
||||
} else { |
||||
printf( "No FPGA suport! CONFIG_FPGA defined as 0x%x.\n", |
||||
CONFIG_FPGA ); |
||||
} |
||||
} |
||||
|
||||
|
||||
/* fpga_get_desc
|
||||
* map a device number to a descriptor |
||||
*/ |
||||
static const fpga_desc * const fpga_get_desc( int devnum ) |
||||
{ |
||||
fpga_desc *desc = (fpga_desc * )NULL; |
||||
|
||||
if (( devnum >= 0 ) && (devnum < next_desc )) { |
||||
desc = &desc_table[devnum]; |
||||
PRINTF( "%s: found fpga descriptor #%d @ 0x%p\n", |
||||
__FUNCTION__, devnum, desc ); |
||||
} |
||||
|
||||
return desc; |
||||
} |
||||
|
||||
|
||||
/* fpga_validate
|
||||
* generic parameter checking code |
||||
*/ |
||||
static const fpga_desc * const fpga_validate( int devnum, void *buf, |
||||
size_t bsize, char *fn ) |
||||
{ |
||||
const fpga_desc * const desc = fpga_get_desc( devnum ); |
||||
|
||||
if ( !desc ) { |
||||
printf( "%s: Invalid device number %d\n", fn, devnum ); |
||||
} |
||||
|
||||
if ( !buf ) { |
||||
printf( "%s: Null buffer.\n", fn ); |
||||
return (fpga_desc * const)NULL; |
||||
} |
||||
if ( !bsize ) { |
||||
printf( "%s: Null buffer size.\n", fn ); |
||||
return (fpga_desc * const)NULL; |
||||
} |
||||
|
||||
return desc; |
||||
} |
||||
|
||||
|
||||
/* fpga_dev_info
|
||||
* generic multiplexing code |
||||
*/ |
||||
static int fpga_dev_info( int devnum ) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume failure */ |
||||
const fpga_desc * const desc = fpga_get_desc( devnum ); |
||||
|
||||
if ( desc ) { |
||||
PRINTF( "%s: Device Descriptor @ 0x%p\n", |
||||
__FUNCTION__, desc->devdesc ); |
||||
|
||||
switch ( desc->devtype ) { |
||||
case fpga_xilinx: |
||||
#if CONFIG_FPGA & CFG_FPGA_XILINX |
||||
printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc ); |
||||
ret_val = xilinx_info( desc->devdesc ); |
||||
#else |
||||
fpga_no_sup( __FUNCTION__, "Xilinx devices" ); |
||||
#endif |
||||
break; |
||||
case fpga_altera: |
||||
#if CONFIG_FPGA & CFG_FPGA_ALTERA |
||||
printf( "Altera Device\nDescriptor @ 0x%p\n", desc ); |
||||
ret_val = altera_info( desc->devdesc ); |
||||
#else |
||||
fpga_no_sup( __FUNCTION__, "Altera devices" ); |
||||
#endif |
||||
break; |
||||
default: |
||||
printf( "%s: Invalid or unsupported device type %d\n", |
||||
__FUNCTION__, desc->devtype ); |
||||
} |
||||
} else { |
||||
printf( "%s: Invalid device number %d\n", |
||||
__FUNCTION__, devnum ); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
|
||||
/* fpga_reloc
|
||||
* generic multiplexing code |
||||
*/ |
||||
int fpga_reloc( fpga_type devtype, void *desc, ulong reloc_off ) |
||||
{ |
||||
int ret_val = FPGA_FAIL; |
||||
|
||||
PRINTF( "%s: Relocating Device of type %d @ 0x%p with offset %lx\n", |
||||
__FUNCTION__, devtype, desc, reloc_off ); |
||||
|
||||
switch ( devtype ) { |
||||
case fpga_xilinx: |
||||
#if CONFIG_FPGA & CFG_FPGA_XILINX |
||||
ret_val = xilinx_reloc( desc, reloc_off ); |
||||
#else |
||||
fpga_no_sup( __FUNCTION__, "Xilinx devices" ); |
||||
#endif |
||||
break; |
||||
case fpga_altera: |
||||
#if CONFIG_FPGA & CFG_FPGA_ALTERA |
||||
ret_val = altera_reloc( desc, reloc_off ); |
||||
#else |
||||
fpga_no_sup( __FUNCTION__, "Altera devices" ); |
||||
#endif |
||||
break; |
||||
default: |
||||
printf( "%s: Invalid or unsupported device type %d\n", |
||||
__FUNCTION__, devtype ); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
/* fgpa_init is usually called from misc_init_r() and MUST be called
|
||||
* before any of the other fpga functions are used. |
||||
*/ |
||||
void fpga_init( ulong reloc_off ) |
||||
{ |
||||
relocation_offset = reloc_off; |
||||
next_desc = 0; |
||||
memset( desc_table, 0, sizeof(desc_table)); |
||||
|
||||
PRINTF( "%s: CONFIG_FPGA = 0x%x\n", __FUNCTION__, CONFIG_FPGA ); |
||||
#if 0 |
||||
PRINTF( "%s: CFG_FPGA_XILINX = 0x%x\n", __FUNCTION__, CFG_FPGA_XILINX ); |
||||
PRINTF( "%s: CFG_FPGA_ALTERA = 0x%x\n", __FUNCTION__, CFG_FPGA_ALTERA ); |
||||
#endif |
||||
} |
||||
|
||||
/* fpga_count
|
||||
* Basic interface function to get the current number of devices available. |
||||
*/ |
||||
const int fpga_count( void ) |
||||
{ |
||||
return next_desc; |
||||
} |
||||
|
||||
/* fpga_add
|
||||
* Attempts to relocate the device/board specific interface code |
||||
* to the proper RAM locations and adds the device descriptor to |
||||
* the device table. |
||||
*/ |
||||
int fpga_add( fpga_type devtype, void *desc ) |
||||
{ |
||||
int devnum = FPGA_INVALID_DEVICE; |
||||
|
||||
if ( next_desc < 0 ) { |
||||
printf( "%s: FPGA support not initialized!\n", __FUNCTION__ ); |
||||
} else if (( devtype > fpga_min_type ) && ( devtype < fpga_undefined )) { |
||||
if ( desc ) { |
||||
if ( next_desc < CONFIG_MAX_FPGA_DEVICES ) { |
||||
if ( fpga_reloc( devtype, desc, relocation_offset ) |
||||
== FPGA_SUCCESS ) { |
||||
devnum = next_desc; |
||||
desc_table[next_desc].devtype = devtype; |
||||
desc_table[next_desc++].devdesc = desc; |
||||
} else { |
||||
printf( "%s: Unable to relocate device interface table!\n", |
||||
__FUNCTION__ ); |
||||
} |
||||
} else { |
||||
printf( "%s: Exceeded Max FPGA device count\n", __FUNCTION__ ); |
||||
} |
||||
} else { |
||||
printf( "%s: NULL device descriptor\n", __FUNCTION__ ); |
||||
} |
||||
} else { |
||||
printf( "%s: Unsupported FPGA type %d\n", __FUNCTION__, devtype ); |
||||
} |
||||
|
||||
return devnum; |
||||
} |
||||
|
||||
/*
|
||||
* Generic multiplexing code |
||||
*/ |
||||
int fpga_load( int devnum, void *buf, size_t bsize ) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume failure */ |
||||
const fpga_desc * const desc = fpga_validate( devnum, buf, bsize, __FUNCTION__ ); |
||||
|
||||
if ( desc ) { |
||||
switch ( desc->devtype ) { |
||||
case fpga_xilinx: |
||||
#if CONFIG_FPGA & CFG_FPGA_XILINX |
||||
ret_val = xilinx_load( desc->devdesc, buf, bsize ); |
||||
#else |
||||
fpga_no_sup( __FUNCTION__, "Xilinx devices" ); |
||||
#endif |
||||
break; |
||||
case fpga_altera: |
||||
#if CONFIG_FPGA & CFG_FPGA_ALTERA |
||||
ret_val = altera_load( desc->devdesc, buf, bsize ); |
||||
#else |
||||
fpga_no_sup( __FUNCTION__, "Altera devices" ); |
||||
#endif |
||||
break; |
||||
default: |
||||
printf( "%s: Invalid or unsupported device type %d\n", |
||||
__FUNCTION__, desc->devtype ); |
||||
} |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
/* fpga_dump
|
||||
* generic multiplexing code |
||||
*/ |
||||
int fpga_dump( int devnum, void *buf, size_t bsize ) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume failure */ |
||||
const fpga_desc * const desc = fpga_validate( devnum, buf, bsize, __FUNCTION__ ); |
||||
|
||||
if ( desc ) { |
||||
switch ( desc->devtype ) { |
||||
case fpga_xilinx: |
||||
#if CONFIG_FPGA & CFG_FPGA_XILINX |
||||
ret_val = xilinx_dump( desc->devdesc, buf, bsize ); |
||||
#else |
||||
fpga_no_sup( __FUNCTION__, "Xilinx devices" ); |
||||
#endif |
||||
break; |
||||
case fpga_altera: |
||||
#if CONFIG_FPGA & CFG_FPGA_ALTERA |
||||
ret_val = altera_dump( desc->devdesc, buf, bsize ); |
||||
#else |
||||
fpga_no_sup( __FUNCTION__, "Altera devices" ); |
||||
#endif |
||||
break; |
||||
default: |
||||
printf( "%s: Invalid or unsupported device type %d\n", |
||||
__FUNCTION__, desc->devtype ); |
||||
} |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
|
||||
/* fpga_info
|
||||
* front end to fpga_dev_info. If devnum is invalid, report on all |
||||
* available devices. |
||||
*/ |
||||
int fpga_info( int devnum ) |
||||
{ |
||||
if ( devnum == FPGA_INVALID_DEVICE ) { |
||||
if ( next_desc > 0 ) { |
||||
int dev; |
||||
|
||||
for ( dev = 0; dev < next_desc; dev++ ) { |
||||
fpga_dev_info( dev ); |
||||
} |
||||
return FPGA_SUCCESS; |
||||
} else { |
||||
printf( "%s: No FPGA devices available.\n", __FUNCTION__ ); |
||||
return FPGA_FAIL; |
||||
} |
||||
} |
||||
else return fpga_dev_info( devnum ); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
#endif /* CONFIG_FPGA */ |
@ -0,0 +1,470 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> /* core U-Boot definitions */ |
||||
#include <spartan2.h> /* Spartan-II device family */ |
||||
|
||||
#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN2)) |
||||
|
||||
/* Define FPGA_DEBUG to get debug printf's */ |
||||
#ifdef FPGA_DEBUG |
||||
#define PRINTF(fmt,args...) printf (fmt ,##args) |
||||
#else |
||||
#define PRINTF(fmt,args...) |
||||
#endif |
||||
|
||||
#undef CFG_FPGA_CHECK_BUSY |
||||
#define CFG_FPGA_PROG_FEEDBACK |
||||
|
||||
/* Note: The assumption is that we cannot possibly run fast enough to
|
||||
* overrun the device (the Slave Parallel mode can free run at 50MHz). |
||||
* If there is a need to operate slower, define CONFIG_FPGA_DELAY in |
||||
* the board config file to slow things down. |
||||
*/ |
||||
#ifndef CONFIG_FPGA_DELAY |
||||
#define CONFIG_FPGA_DELAY() |
||||
#endif |
||||
|
||||
#ifndef CFG_FPGA_WAIT |
||||
#define CFG_FPGA_WAIT 10 |
||||
#endif |
||||
|
||||
static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); |
||||
static int Spartan2_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); |
||||
/* static int Spartan2_sp_info( Xilinx_desc *desc ); */ |
||||
static int Spartan2_sp_reloc( Xilinx_desc *desc, ulong reloc_offset ); |
||||
|
||||
static int Spartan2_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); |
||||
static int Spartan2_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); |
||||
/* static int Spartan2_ss_info( Xilinx_desc *desc ); */ |
||||
static int Spartan2_ss_reloc( Xilinx_desc *desc, ulong reloc_offset ); |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
/* Spartan-II Generic Implementation */ |
||||
int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
int ret_val = FPGA_FAIL; |
||||
|
||||
switch (desc->iface) { |
||||
case slave_serial: |
||||
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); |
||||
ret_val = Spartan2_ss_load (desc, buf, bsize); |
||||
break; |
||||
|
||||
case slave_parallel: |
||||
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); |
||||
ret_val = Spartan2_sp_load (desc, buf, bsize); |
||||
break; |
||||
|
||||
default: |
||||
printf ("%s: Unsupported interface type, %d\n", |
||||
__FUNCTION__, desc->iface); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
int Spartan2_dump (Xilinx_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
int ret_val = FPGA_FAIL; |
||||
|
||||
switch (desc->iface) { |
||||
case slave_serial: |
||||
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); |
||||
ret_val = Spartan2_ss_dump (desc, buf, bsize); |
||||
break; |
||||
|
||||
case slave_parallel: |
||||
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); |
||||
ret_val = Spartan2_sp_dump (desc, buf, bsize); |
||||
break; |
||||
|
||||
default: |
||||
printf ("%s: Unsupported interface type, %d\n", |
||||
__FUNCTION__, desc->iface); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
int Spartan2_info( Xilinx_desc *desc ) |
||||
{ |
||||
return FPGA_SUCCESS; |
||||
} |
||||
|
||||
|
||||
int Spartan2_reloc (Xilinx_desc * desc, ulong reloc_offset) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume a failure */ |
||||
|
||||
if (desc->family != Xilinx_Spartan2) { |
||||
printf ("%s: Unsupported family type, %d\n", |
||||
__FUNCTION__, desc->family); |
||||
return FPGA_FAIL; |
||||
} else |
||||
switch (desc->iface) { |
||||
case slave_serial: |
||||
ret_val = Spartan2_ss_reloc (desc, reloc_offset); |
||||
break; |
||||
|
||||
case slave_parallel: |
||||
ret_val = Spartan2_sp_reloc (desc, reloc_offset); |
||||
break; |
||||
|
||||
default: |
||||
printf ("%s: Unsupported interface type, %d\n", |
||||
__FUNCTION__, desc->iface); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
/* Spartan-II Slave Parallel Generic Implementation */ |
||||
|
||||
static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume the worst */ |
||||
Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; |
||||
|
||||
PRINTF ("%s: start with interface functions @ 0x%p\n", |
||||
__FUNCTION__, fn); |
||||
|
||||
if (fn) { |
||||
size_t bytecount = 0; |
||||
unsigned char *data = (unsigned char *) buf; |
||||
int cookie = desc->cookie; /* make a local copy */ |
||||
unsigned long ts; /* timestamp */ |
||||
|
||||
PRINTF ("%s: Function Table:\n" |
||||
"ptr:\t0x%p\n" |
||||
"struct: 0x%p\n" |
||||
"pre: 0x%p\n" |
||||
"pgm:\t0x%p\n" |
||||
"init:\t0x%p\n" |
||||
"err:\t0x%p\n" |
||||
"clk:\t0x%p\n" |
||||
"cs:\t0x%p\n" |
||||
"wr:\t0x%p\n" |
||||
"read data:\t0x%p\n" |
||||
"write data:\t0x%p\n" |
||||
"busy:\t0x%p\n" |
||||
"abort:\t0x%p\n", |
||||
"post:\t0x%p\n\n", |
||||
__FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err, |
||||
fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy, |
||||
fn->abort, fn->post); |
||||
|
||||
/*
|
||||
* This code is designed to emulate the "Express Style" |
||||
* Continuous Data Loading in Slave Parallel Mode for |
||||
* the Spartan-II Family. |
||||
*/ |
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
printf ("Loading FPGA Device %d...\n", cookie); |
||||
#endif |
||||
/*
|
||||
* Run the pre configuration function if there is one. |
||||
*/ |
||||
if (*fn->pre) { |
||||
(*fn->pre) (cookie); |
||||
} |
||||
|
||||
/* Establish the initial state */ |
||||
(*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */ |
||||
|
||||
/* Get ready for the burn */ |
||||
CONFIG_FPGA_DELAY (); |
||||
(*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */ |
||||
|
||||
ts = get_timer (0); /* get current time */ |
||||
/* Now wait for INIT and BUSY to go high */ |
||||
do { |
||||
CONFIG_FPGA_DELAY (); |
||||
if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ |
||||
puts ("** Timeout waiting for INIT to clear.\n"); |
||||
(*fn->abort) (cookie); /* abort the burn */ |
||||
return FPGA_FAIL; |
||||
} |
||||
} while ((*fn->init) (cookie) && (*fn->busy) (cookie)); |
||||
|
||||
(*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */ |
||||
(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ |
||||
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ |
||||
|
||||
/* Load the data */ |
||||
while (bytecount < bsize) { |
||||
/* XXX - do we check for an Ctrl-C press in here ??? */ |
||||
/* XXX - Check the error bit? */ |
||||
|
||||
(*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */ |
||||
CONFIG_FPGA_DELAY (); |
||||
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ |
||||
CONFIG_FPGA_DELAY (); |
||||
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ |
||||
|
||||
#ifdef CFG_FPGA_CHECK_BUSY |
||||
ts = get_timer (0); /* get current time */ |
||||
while ((*fn->busy) (cookie)) { |
||||
/* XXX - we should have a check in here somewhere to
|
||||
* make sure we aren't busy forever... */ |
||||
|
||||
CONFIG_FPGA_DELAY (); |
||||
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ |
||||
CONFIG_FPGA_DELAY (); |
||||
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ |
||||
|
||||
if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ |
||||
puts ("** Timeout waiting for BUSY to clear.\n"); |
||||
(*fn->abort) (cookie); /* abort the burn */ |
||||
return FPGA_FAIL; |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
if (bytecount % (bsize / 40) == 0) |
||||
putc ('.'); /* let them know we are alive */ |
||||
#endif |
||||
} |
||||
|
||||
CONFIG_FPGA_DELAY (); |
||||
(*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */ |
||||
(*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */ |
||||
|
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
putc ('\n'); /* terminate the dotted line */ |
||||
#endif |
||||
|
||||
/* now check for done signal */ |
||||
ts = get_timer (0); /* get current time */ |
||||
ret_val = FPGA_SUCCESS; |
||||
while ((*fn->done) (cookie) == FPGA_FAIL) { |
||||
/* XXX - we should have a check in here somewhere to
|
||||
* make sure we aren't busy forever... */ |
||||
|
||||
CONFIG_FPGA_DELAY (); |
||||
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ |
||||
CONFIG_FPGA_DELAY (); |
||||
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ |
||||
|
||||
if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ |
||||
puts ("** Timeout waiting for DONE to clear.\n"); |
||||
(*fn->abort) (cookie); /* abort the burn */ |
||||
ret_val = FPGA_FAIL; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
if (ret_val == FPGA_SUCCESS) { |
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
puts ("Done.\n"); |
||||
#endif |
||||
} |
||||
/*
|
||||
* Run the post configuration function if there is one. |
||||
*/ |
||||
if (*fn->post) { |
||||
(*fn->post) (cookie); |
||||
} |
||||
|
||||
else { |
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
puts ("Fail.\n"); |
||||
#endif |
||||
} |
||||
|
||||
} else { |
||||
printf ("%s: NULL Interface function table!\n", __FUNCTION__); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume the worst */ |
||||
Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; |
||||
|
||||
if (fn) { |
||||
unsigned char *data = (unsigned char *) buf; |
||||
size_t bytecount = 0; |
||||
int cookie = desc->cookie; /* make a local copy */ |
||||
|
||||
printf ("Starting Dump of FPGA Device %d...\n", cookie); |
||||
|
||||
(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ |
||||
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ |
||||
|
||||
/* dump the data */ |
||||
while (bytecount < bsize) { |
||||
/* XXX - do we check for an Ctrl-C press in here ??? */ |
||||
|
||||
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ |
||||
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ |
||||
(*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */ |
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
if (bytecount % (bsize / 40) == 0) |
||||
putc ('.'); /* let them know we are alive */ |
||||
#endif |
||||
} |
||||
|
||||
(*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */ |
||||
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ |
||||
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ |
||||
|
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
putc ('\n'); /* terminate the dotted line */ |
||||
#endif |
||||
puts ("Done.\n"); |
||||
|
||||
/* XXX - checksum the data? */ |
||||
} else { |
||||
printf ("%s: NULL Interface function table!\n", __FUNCTION__); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
|
||||
static int Spartan2_sp_reloc (Xilinx_desc * desc, ulong reloc_offset) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume the worst */ |
||||
Xilinx_Spartan2_Slave_Parallel_fns *fn_r, *fn = |
||||
(Xilinx_Spartan2_Slave_Parallel_fns *) (desc->iface_fns); |
||||
|
||||
if (fn) { |
||||
ulong addr; |
||||
|
||||
/* Get the relocated table address */ |
||||
addr = (ulong) fn + reloc_offset; |
||||
fn_r = (Xilinx_Spartan2_Slave_Parallel_fns *) addr; |
||||
|
||||
if (!fn_r->relocated) { |
||||
|
||||
if (memcmp (fn_r, fn, |
||||
sizeof (Xilinx_Spartan2_Slave_Parallel_fns)) |
||||
== 0) { |
||||
/* good copy of the table, fix the descriptor pointer */ |
||||
desc->iface_fns = fn_r; |
||||
} else { |
||||
PRINTF ("%s: Invalid function table at 0x%p\n", |
||||
__FUNCTION__, fn_r); |
||||
return FPGA_FAIL; |
||||
} |
||||
|
||||
PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, |
||||
desc); |
||||
|
||||
addr = (ulong) (fn->pre) + reloc_offset; |
||||
fn_r->pre = (Xilinx_pre_fn) addr; |
||||
|
||||
addr = (ulong) (fn->pgm) + reloc_offset; |
||||
fn_r->pgm = (Xilinx_pgm_fn) addr; |
||||
|
||||
addr = (ulong) (fn->init) + reloc_offset; |
||||
fn_r->init = (Xilinx_init_fn) addr; |
||||
|
||||
addr = (ulong) (fn->done) + reloc_offset; |
||||
fn_r->done = (Xilinx_done_fn) addr; |
||||
|
||||
addr = (ulong) (fn->clk) + reloc_offset; |
||||
fn_r->clk = (Xilinx_clk_fn) addr; |
||||
|
||||
addr = (ulong) (fn->err) + reloc_offset; |
||||
fn_r->err = (Xilinx_err_fn) addr; |
||||
|
||||
addr = (ulong) (fn->cs) + reloc_offset; |
||||
fn_r->cs = (Xilinx_cs_fn) addr; |
||||
|
||||
addr = (ulong) (fn->wr) + reloc_offset; |
||||
fn_r->wr = (Xilinx_wr_fn) addr; |
||||
|
||||
addr = (ulong) (fn->rdata) + reloc_offset; |
||||
fn_r->rdata = (Xilinx_rdata_fn) addr; |
||||
|
||||
addr = (ulong) (fn->wdata) + reloc_offset; |
||||
fn_r->wdata = (Xilinx_wdata_fn) addr; |
||||
|
||||
addr = (ulong) (fn->busy) + reloc_offset; |
||||
fn_r->busy = (Xilinx_busy_fn) addr; |
||||
|
||||
addr = (ulong) (fn->abort) + reloc_offset; |
||||
fn_r->abort = (Xilinx_abort_fn) addr; |
||||
|
||||
addr = (ulong) (fn->post) + reloc_offset; |
||||
fn_r->post = (Xilinx_post_fn) addr; |
||||
|
||||
fn_r->relocated = TRUE; |
||||
|
||||
} else { |
||||
/* this table has already been moved */ |
||||
/* XXX - should check to see if the descriptor is correct */ |
||||
desc->iface_fns = fn_r; |
||||
} |
||||
|
||||
ret_val = FPGA_SUCCESS; |
||||
} else { |
||||
printf ("%s: NULL Interface function table!\n", __FUNCTION__); |
||||
} |
||||
|
||||
return ret_val; |
||||
|
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
printf ("%s: Slave Serial Loading is still unsupported\n", |
||||
__FUNCTION__); |
||||
return FPGA_FAIL; |
||||
} |
||||
|
||||
static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
printf ("%s: Slave Serial Dumping is still unsupported\n", |
||||
__FUNCTION__); |
||||
return FPGA_FAIL; |
||||
} |
||||
|
||||
static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume the worst */ |
||||
Xilinx_Spartan2_Slave_Serial_fns *fn = |
||||
(Xilinx_Spartan2_Slave_Serial_fns *) (desc->iface_fns); |
||||
|
||||
if (fn) { |
||||
printf ("%s: Slave Serial Loading is still unsupported\n", |
||||
__FUNCTION__); |
||||
} else { |
||||
printf ("%s: NULL Interface function table!\n", __FUNCTION__); |
||||
} |
||||
|
||||
return ret_val; |
||||
|
||||
} |
||||
|
||||
#endif |
@ -0,0 +1,156 @@ |
||||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#########################################################################
|
||||
|
||||
#
|
||||
# When cross-compiling on NetBSD, we have to define __PPC__ or else we
|
||||
# will pick up a va_list declaration that is incompatible with the
|
||||
# actual argument lists emitted by the compiler.
|
||||
#
|
||||
# [Tested on NetBSD/i386 1.5 + cross-powerpc-netbsd-1.3]
|
||||
|
||||
ifeq ($(ARCH),ppc) |
||||
ifeq ($(CROSS_COMPILE),powerpc-netbsd-) |
||||
PLATFORM_CPPFLAGS+= -D__PPC__
|
||||
endif |
||||
ifeq ($(CROSS_COMPILE),powerpc-openbsd-) |
||||
PLATFORM_CPPFLAGS+= -D__PPC__
|
||||
endif |
||||
endif |
||||
|
||||
ifeq ($(ARCH),arm) |
||||
ifeq ($(CROSS_COMPILE),powerpc-netbsd-) |
||||
PLATFORM_CPPFLAGS+= -D__ARM__
|
||||
endif |
||||
ifeq ($(CROSS_COMPILE),powerpc-openbsd-) |
||||
PLATFORM_CPPFLAGS+= -D__ARM__
|
||||
endif |
||||
endif |
||||
|
||||
ifdef ARCH |
||||
sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules
|
||||
endif |
||||
ifdef CPU |
||||
sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules
|
||||
endif |
||||
ifdef VENDOR |
||||
BOARDDIR = $(VENDOR)/$(BOARD)
|
||||
else |
||||
BOARDDIR = $(BOARD)
|
||||
endif |
||||
ifdef BOARD |
||||
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk # include board specific rules
|
||||
endif |
||||
|
||||
#########################################################################
|
||||
|
||||
CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
|
||||
else if [ -x /bin/bash ]; then echo /bin/bash; \
|
||||
else echo sh; fi ; fi)
|
||||
|
||||
ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) |
||||
HOSTCC = cc
|
||||
else |
||||
HOSTCC = gcc
|
||||
endif |
||||
HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
|
||||
HOSTSTRIP = strip
|
||||
|
||||
#########################################################################
|
||||
|
||||
#
|
||||
# Include the make variables (CC, etc...)
|
||||
#
|
||||
AS = $(CROSS_COMPILE)as
|
||||
LD = $(CROSS_COMPILE)ld
|
||||
CC = $(CROSS_COMPILE)gcc
|
||||
CPP = $(CC) -E
|
||||
AR = $(CROSS_COMPILE)ar
|
||||
NM = $(CROSS_COMPILE)nm
|
||||
STRIP = $(CROSS_COMPILE)strip
|
||||
OBJCOPY = $(CROSS_COMPILE)objcopy
|
||||
OBJDUMP = $(CROSS_COMPILE)objdump
|
||||
RANLIB = $(CROSS_COMPILE)RANLIB
|
||||
|
||||
RELFLAGS= $(PLATFORM_RELFLAGS)
|
||||
DBGFLAGS= -g #-DDEBUG
|
||||
OPTFLAGS= -Os #-fomit-frame-pointer
|
||||
#LDSCRIPT := board/$(BOARDDIR)/u-boot.lds.debug
|
||||
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
|
||||
OBJCFLAGS := --gap-fill=0xff
|
||||
|
||||
CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
|
||||
-D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \
|
||||
-I$(TOPDIR)/include \
|
||||
-fno-builtin \
|
||||
-pipe $(PLATFORM_CPPFLAGS)
|
||||
|
||||
ifdef BUILD_TAG |
||||
CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \
|
||||
-DBUILD_TAG='"$(BUILD_TAG)"'
|
||||
else |
||||
CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
|
||||
endif |
||||
|
||||
AFLAGS_DEBUG := -Wa,-gstabs
|
||||
AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
|
||||
|
||||
LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
|
||||
|
||||
# Location of a usable BFD library, where we define "usable" as
|
||||
# "built for ${HOST}, supports ${TARGET}". Sensible values are
|
||||
# - When cross-compiling: the root of the cross-environment
|
||||
# - Linux/ppc (native): /usr
|
||||
# - NetBSD/ppc (native): you lose ... (must extract these from the
|
||||
# binutils build directory, plus the native and U-Boot include
|
||||
# files don't like each other)
|
||||
#
|
||||
# So far, this is used only by tools/gdb/Makefile.
|
||||
|
||||
ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) |
||||
BFD_ROOT_DIR = /usr/local/tools
|
||||
else |
||||
#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386
|
||||
#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386
|
||||
#BFD_ROOT_DIR = /usr # native
|
||||
BFD_ROOT_DIR = /opt/powerpc
|
||||
endif |
||||
|
||||
#########################################################################
|
||||
|
||||
export CONFIG_SHELL HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \ |
||||
AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP \
|
||||
MAKE
|
||||
export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS |
||||
|
||||
#########################################################################
|
||||
|
||||
%.s: %.S |
||||
$(CPP) $(AFLAGS) -o $@ $(CURDIR)/$<
|
||||
%.o: %.S |
||||
$(CC) $(AFLAGS) -c -o $@ $(CURDIR)/$<
|
||||
%.o: %.c |
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
#########################################################################
|
@ -0,0 +1,160 @@ |
||||
/*********************************************************************
|
||||
* mpc8240epic.h - EPIC module of the MPC8240 micro-controller |
||||
* |
||||
* Copyrigh 1999 Motorola Inc. |
||||
* |
||||
* Modification History: |
||||
* ===================== |
||||
* 01a,04Feb99,My Created. |
||||
* 15Nov200, robt -modified to use in U-Boot |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __INCEPICh |
||||
#define __INCEPICh |
||||
|
||||
#define ULONG unsigned long |
||||
#define MAXVEC 20 |
||||
#define MAXIRQ 5 /* IRQs */ |
||||
#define EPIC_DIRECT_IRQ 0 /* Direct interrupt type */ |
||||
|
||||
/* EPIC register addresses */ |
||||
|
||||
#define EPIC_EUMBBAR 0x40000 /* EUMBBAR of EPIC */ |
||||
#define EPIC_FEATURES_REG (EPIC_EUMBBAR + 0x01000)/* Feature reporting */ |
||||
#define EPIC_GLOBAL_REG (EPIC_EUMBBAR + 0x01020)/* Global config. */ |
||||
#define EPIC_INT_CONF_REG (EPIC_EUMBBAR + 0x01030)/* Interrupt config. */ |
||||
#define EPIC_VENDOR_ID_REG (EPIC_EUMBBAR + 0x01080)/* Vendor id */ |
||||
#define EPIC_PROC_INIT_REG (EPIC_EUMBBAR + 0x01090)/* Processor init. */ |
||||
#define EPIC_SPUR_VEC_REG (EPIC_EUMBBAR + 0x010e0)/* Spurious vector */ |
||||
#define EPIC_TM_FREQ_REG (EPIC_EUMBBAR + 0x010f0)/* Timer Frequency */ |
||||
|
||||
#define EPIC_TM0_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01100)/* Gbl TM0 Cur. Count*/ |
||||
#define EPIC_TM0_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01110)/* Gbl TM0 Base Count*/ |
||||
#define EPIC_TM0_VEC_REG (EPIC_EUMBBAR + 0x01120)/* Gbl TM0 Vector Pri*/ |
||||
#define EPIC_TM0_DES_REG (EPIC_EUMBBAR + 0x01130)/* Gbl TM0 Dest. */ |
||||
|
||||
#define EPIC_TM1_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01140)/* Gbl TM1 Cur. Count*/ |
||||
#define EPIC_TM1_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01150)/* Gbl TM1 Base Count*/ |
||||
#define EPIC_TM1_VEC_REG (EPIC_EUMBBAR + 0x01160)/* Gbl TM1 Vector Pri*/ |
||||
#define EPIC_TM1_DES_REG (EPIC_EUMBBAR + 0x01170)/* Gbl TM1 Dest. */ |
||||
|
||||
#define EPIC_TM2_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01180)/* Gbl TM2 Cur. Count*/ |
||||
#define EPIC_TM2_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01190)/* Gbl TM2 Base Count*/ |
||||
#define EPIC_TM2_VEC_REG (EPIC_EUMBBAR + 0x011a0)/* Gbl TM2 Vector Pri*/ |
||||
#define EPIC_TM2_DES_REG (EPIC_EUMBBAR + 0x011b0)/* Gbl TM2 Dest */ |
||||
|
||||
#define EPIC_TM3_CUR_COUNT_REG (EPIC_EUMBBAR + 0x011c0)/* Gbl TM3 Cur. Count*/ |
||||
#define EPIC_TM3_BASE_COUNT_REG (EPIC_EUMBBAR + 0x011d0)/* Gbl TM3 Base Count*/ |
||||
#define EPIC_TM3_VEC_REG (EPIC_EUMBBAR + 0x011e0)/* Gbl TM3 Vector Pri*/ |
||||
#define EPIC_TM3_DES_REG (EPIC_EUMBBAR + 0x011f0)/* Gbl TM3 Dest. */ |
||||
|
||||
#define EPIC_EX_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Ext. Int. Sr0 Des */ |
||||
#define EPIC_EX_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Ext. Int. Sr0 Vect*/ |
||||
#define EPIC_EX_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Ext. Int. Sr1 Des */ |
||||
#define EPIC_EX_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Ext. Int. Sr1 Vect*/ |
||||
#define EPIC_EX_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Ext. Int. Sr2 Des */ |
||||
#define EPIC_EX_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Ext. Int. Sr2 Vect*/ |
||||
#define EPIC_EX_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Ext. Int. Sr3 Des */ |
||||
#define EPIC_EX_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Ext. Int. Sr3 Vect*/ |
||||
#define EPIC_EX_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Ext. Int. Sr4 Des */ |
||||
#define EPIC_EX_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Ext. Int. Sr4 Vect*/ |
||||
|
||||
#define EPIC_SR_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Sr. Int. Sr0 Des */ |
||||
#define EPIC_SR_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Sr. Int. Sr0 Vect */ |
||||
#define EPIC_SR_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Sr. Int. Sr1 Des */ |
||||
#define EPIC_SR_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Sr. Int. Sr1 Vect.*/ |
||||
#define EPIC_SR_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Sr. Int. Sr2 Des */ |
||||
#define EPIC_SR_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Sr. Int. Sr2 Vect.*/ |
||||
#define EPIC_SR_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Sr. Int. Sr3 Des */ |
||||
#define EPIC_SR_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Sr. Int. Sr3 Vect.*/ |
||||
#define EPIC_SR_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Sr. Int. Sr4 Des */ |
||||
#define EPIC_SR_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Sr. Int. Sr4 Vect.*/ |
||||
|
||||
#define EPIC_SR_INT5_VEC_REG (EPIC_EUMBBAR + 0x102a0)/* Sr. Int. Sr5 Des */ |
||||
#define EPIC_SR_INT5_DES_REG (EPIC_EUMBBAR + 0x102b0)/* Sr. Int. Sr5 Vect.*/ |
||||
#define EPIC_SR_INT6_VEC_REG (EPIC_EUMBBAR + 0x102c0)/* Sr. Int. Sr6 Des */ |
||||
#define EPIC_SR_INT6_DES_REG (EPIC_EUMBBAR + 0x102d0)/* Sr. Int. Sr6 Vect.*/ |
||||
#define EPIC_SR_INT7_VEC_REG (EPIC_EUMBBAR + 0x102e0)/* Sr. Int. Sr7 Des */ |
||||
#define EPIC_SR_INT7_DES_REG (EPIC_EUMBBAR + 0x102f0)/* Sr. Int. Sr7 Vect.*/ |
||||
#define EPIC_SR_INT8_VEC_REG (EPIC_EUMBBAR + 0x10300)/* Sr. Int. Sr8 Des */ |
||||
#define EPIC_SR_INT8_DES_REG (EPIC_EUMBBAR + 0x10310)/* Sr. Int. Sr8 Vect.*/ |
||||
#define EPIC_SR_INT9_VEC_REG (EPIC_EUMBBAR + 0x10320)/* Sr. Int. Sr9 Des */ |
||||
#define EPIC_SR_INT9_DES_REG (EPIC_EUMBBAR + 0x10330)/* Sr. Int. Sr9 Vect.*/ |
||||
|
||||
#define EPIC_SR_INT10_VEC_REG (EPIC_EUMBBAR + 0x10340)/* Sr. Int. Sr10 Des */ |
||||
#define EPIC_SR_INT10_DES_REG (EPIC_EUMBBAR + 0x10350)/* Sr. Int. Sr10 Vect*/ |
||||
#define EPIC_SR_INT11_VEC_REG (EPIC_EUMBBAR + 0x10360)/* Sr. Int. Sr11 Des */ |
||||
#define EPIC_SR_INT11_DES_REG (EPIC_EUMBBAR + 0x10370)/* Sr. Int. Sr11 Vect*/ |
||||
#define EPIC_SR_INT12_VEC_REG (EPIC_EUMBBAR + 0x10380)/* Sr. Int. Sr12 Des */ |
||||
#define EPIC_SR_INT12_DES_REG (EPIC_EUMBBAR + 0x10390)/* Sr. Int. Sr12 Vect*/ |
||||
#define EPIC_SR_INT13_VEC_REG (EPIC_EUMBBAR + 0x103a0)/* Sr. Int. Sr13 Des */ |
||||
#define EPIC_SR_INT13_DES_REG (EPIC_EUMBBAR + 0x103b0)/* Sr. Int. Sr13 Vect*/ |
||||
#define EPIC_SR_INT14_VEC_REG (EPIC_EUMBBAR + 0x103c0)/* Sr. Int. Sr14 Des */ |
||||
#define EPIC_SR_INT14_DES_REG (EPIC_EUMBBAR + 0x103d0)/* Sr. Int. Sr14 Vect*/ |
||||
#define EPIC_SR_INT15_VEC_REG (EPIC_EUMBBAR + 0x103e0)/* Sr. Int. Sr15 Des */ |
||||
#define EPIC_SR_INT15_DES_REG (EPIC_EUMBBAR + 0x103f0)/* Sr. Int. Sr15 Vect*/ |
||||
|
||||
#define EPIC_I2C_INT_VEC_REG (EPIC_EUMBBAR + 0x11020)/* I2C Int. Vect Pri.*/ |
||||
#define EPIC_I2C_INT_DES_REG (EPIC_EUMBBAR + 0x11030)/* I2C Int. Dest */ |
||||
#define EPIC_DMA0_INT_VEC_REG (EPIC_EUMBBAR + 0x11040)/* DMA0 Int. Vect Pri*/ |
||||
#define EPIC_DMA0_INT_DES_REG (EPIC_EUMBBAR + 0x11050)/* DMA0 Int. Dest */ |
||||
#define EPIC_DMA1_INT_VEC_REG (EPIC_EUMBBAR + 0x11060)/* DMA1 Int. Vect Pri*/ |
||||
#define EPIC_DMA1_INT_DES_REG (EPIC_EUMBBAR + 0x11070)/* DMA1 Int. Dest */ |
||||
#define EPIC_MSG_INT_VEC_REG (EPIC_EUMBBAR + 0x110c0)/* Msg Int. Vect Pri*/ |
||||
#define EPIC_MSG_INT_DES_REG (EPIC_EUMBBAR + 0x110d0)/* Msg Int. Dest */ |
||||
|
||||
#define EPIC_PROC_CTASK_PRI_REG (EPIC_EUMBBAR + 0x20080)/* Proc. current task*/ |
||||
#define EPIC_PROC_INT_ACK_REG (EPIC_EUMBBAR + 0x200a0)/* Int. acknowledge */ |
||||
#define EPIC_PROC_EOI_REG (EPIC_EUMBBAR + 0x200b0)/* End of interrupt */ |
||||
|
||||
/* Error code */ |
||||
|
||||
#define OK 0 |
||||
#define ERROR -1 |
||||
|
||||
/* function prototypes */ |
||||
|
||||
void epicVendorId( unsigned int *step, |
||||
unsigned int *devId, |
||||
unsigned int *venId |
||||
); |
||||
void epicFeatures( unsigned int *noIRQs, |
||||
unsigned int *noCPUs, |
||||
unsigned int *VerId ); |
||||
extern void epicInit( unsigned int IRQType, unsigned int clkRatio); |
||||
ULONG sysEUMBBARRead ( ULONG regNum ); |
||||
void sysEUMBBARWrite ( ULONG regNum, ULONG regVal); |
||||
extern void epicTmFrequencySet( unsigned int frq ); |
||||
extern unsigned int epicTmFrequencyGet(void); |
||||
extern unsigned int epicTmBaseSet( ULONG srcAddr, |
||||
unsigned int cnt, |
||||
unsigned int inhibit ); |
||||
extern unsigned int epicTmBaseGet ( ULONG srcAddr, unsigned int *val ); |
||||
extern unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val ); |
||||
extern unsigned int epicTmInhibit( unsigned int timer ); |
||||
extern unsigned int epicTmEnable( ULONG srcAdr ); |
||||
extern void CoreExtIntEnable(void); /* Enable 603e external interrupts */ |
||||
extern void CoreExtIntDisable(void); /* Disable 603e external interrupts */ |
||||
extern unsigned char epicIntTaskGet(void); |
||||
extern void epicIntTaskSet( unsigned char val ); |
||||
extern unsigned int epicIntAck(void); |
||||
extern void epicSprSet( unsigned int eumbbar, unsigned char ); |
||||
extern void epicConfigGet( unsigned int *clkRatio, |
||||
unsigned int *serEnable ); |
||||
extern void SrcVecTableInit(void); |
||||
extern unsigned int epicModeGet(void); |
||||
extern void epicIntEnable(int Vect); |
||||
extern void epicIntDisable(int Vect); |
||||
extern int epicIntSourceConfig(int Vect, int Polarity, int Sense, int Prio); |
||||
extern unsigned int epicIntAck(void); |
||||
extern void epicEOI(void); |
||||
extern int epicCurTaskPrioSet(int Vect); |
||||
|
||||
struct SrcVecTable |
||||
{ |
||||
ULONG srcAddr; |
||||
char srcName[40]; |
||||
}; |
||||
|
||||
#endif /* EPIC_H */ |
@ -0,0 +1,415 @@ |
||||
|
||||
This file contains basic information on the port of U-Boot to TQM8260. |
||||
All the changes fit in the common U-Boot infrastructure, providing a |
||||
new TQM8260-specific entry in makefiles. To build U-Boot for TQM8260, |
||||
type "make TQM8260_config", edit the "include/config_TQM8260.h" file |
||||
if necessary, then type "make". |
||||
|
||||
|
||||
Common file modifications: |
||||
-------------------------- |
||||
|
||||
The following common files have been modified by this project: |
||||
(starting from the ppcboot-0.9.3/ directory) |
||||
|
||||
MAKEALL - TQM8260 entry added |
||||
Makefile - TQM8260_config entry added |
||||
cpu/mpc8260/Makefile - soft_i2c.o module added |
||||
cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious |
||||
bug fixed (fcr -> scr) |
||||
cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added |
||||
include/flash.h - added definitions for the AM29LV640D Flash chip |
||||
|
||||
|
||||
New files: |
||||
---------- |
||||
|
||||
The following new files have been added by this project: |
||||
(starting from the ppcboot-0.9.3/ directory) |
||||
|
||||
board/tqm8260/ - board-specific directory |
||||
board/tqm8260/Makefile - board-specific makefile |
||||
board/tqm8260/config.mk - config file |
||||
board/tqm8260/flash.c - flash driver (for AM29LV640D) |
||||
board/tqm8260/ppcboot.lds - linker script |
||||
board/tqm8260/tqm8260.c - ioport and memory initialization |
||||
cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver |
||||
include/config_TQM8260.h - main configuration file |
||||
|
||||
|
||||
New configuration options: |
||||
-------------------------- |
||||
|
||||
CONFIG_TQM8260 |
||||
|
||||
Main board-specific option (should be defined for TQM8260). |
||||
|
||||
CONFIG_82xx_CONS_SMC1 |
||||
|
||||
If defined, SMC1 will be used as the console |
||||
|
||||
CONFIG_82xx_CONS_SMC2 |
||||
|
||||
If defined, SMC2 will be used as the console |
||||
|
||||
CFG_INIT_LOCAL_SDRAM |
||||
|
||||
If defined, the SDRAM on the local bus will be initialized and |
||||
mapped at BR2. |
||||
|
||||
|
||||
Acceptance criteria tests: |
||||
-------------------------- |
||||
|
||||
The following tests have been conducted to validate the port of U-Boot |
||||
to TQM8260: |
||||
|
||||
1. Operation on serial console: |
||||
|
||||
With the CONFIG_82xx_CONS_SMC1 option defined in the main configuration file, |
||||
the U-Boot output appeared on the serial terminal connected to COM1 as |
||||
follows: |
||||
|
||||
------------------------------------------------------------------------------ |
||||
=> help |
||||
go - start application at address 'addr' |
||||
run - run commands in an environment variable |
||||
bootm - boot application image from memory |
||||
bootp - boot image via network using BootP/TFTP protocol |
||||
tftpboot- boot image via network using TFTP protocol |
||||
and env variables ipaddr and serverip |
||||
rarpboot- boot image via network using RARP/TFTP protocol |
||||
bootd - boot default, i.e., run 'bootcmd' |
||||
loads - load S-Record file over serial line |
||||
loadb - load binary file over serial line (kermit mode) |
||||
md - memory display |
||||
mm - memory modify (auto-incrementing) |
||||
nm - memory modify (constant address) |
||||
mw - memory write (fill) |
||||
cp - memory copy |
||||
cmp - memory compare |
||||
crc32 - checksum calculation |
||||
base - print or set address offset |
||||
printenv- print environment variables |
||||
setenv - set environment variables |
||||
saveenv - save environment variables to persistent storage |
||||
protect - enable or disable FLASH write protection |
||||
erase - erase FLASH memory |
||||
flinfo - print FLASH memory information |
||||
bdinfo - print Board Info structure |
||||
iminfo - print header information for application image |
||||
coninfo - print console devices and informations |
||||
eeprom - EEPROM sub-system |
||||
loop - infinite loop on address range |
||||
mtest - simple RAM test |
||||
icache - enable or disable instruction cache |
||||
dcache - enable or disable data cache |
||||
reset - Perform RESET of the CPU |
||||
echo - echo args to console |
||||
version - print monitor version |
||||
help - print online help |
||||
? - alias for 'help' |
||||
=> |
||||
------------------------------------------------------------------------------ |
||||
|
||||
|
||||
2. Flash driver operation |
||||
|
||||
The following sequence was performed to test the "flinfo" command: |
||||
|
||||
------------------------------------------------------------------------------ |
||||
=> flinfo |
||||
|
||||
Bank # 1: AMD 29LV640D (64 M, uniform sector) |
||||
Size: 32 MB in 128 Sectors |
||||
Sector Start Addresses: |
||||
40000000 40040000 (RO) 40080000 400C0000 40100000 |
||||
40140000 40180000 401C0000 40200000 40240000 |
||||
40280000 402C0000 40300000 40340000 40380000 |
||||
403C0000 40400000 40440000 40480000 404C0000 |
||||
40500000 40540000 40580000 405C0000 40600000 |
||||
40640000 40680000 406C0000 40700000 40740000 |
||||
40780000 407C0000 40800000 40840000 40880000 |
||||
408C0000 40900000 40940000 40980000 409C0000 |
||||
40A00000 40A40000 40A80000 40AC0000 40B00000 |
||||
40B40000 40B80000 40BC0000 40C00000 40C40000 |
||||
40C80000 40CC0000 40D00000 40D40000 40D80000 |
||||
40DC0000 40E00000 40E40000 40E80000 40EC0000 |
||||
40F00000 40F40000 40F80000 40FC0000 41000000 |
||||
41040000 41080000 410C0000 41100000 41140000 |
||||
41180000 411C0000 41200000 41240000 41280000 |
||||
412C0000 41300000 41340000 41380000 413C0000 |
||||
41400000 41440000 41480000 414C0000 41500000 |
||||
41540000 41580000 415C0000 41600000 41640000 |
||||
41680000 416C0000 41700000 41740000 41780000 |
||||
417C0000 41800000 41840000 41880000 418C0000 |
||||
41900000 41940000 41980000 419C0000 41A00000 |
||||
41A40000 41A80000 41AC0000 41B00000 41B40000 |
||||
41B80000 41BC0000 41C00000 41C40000 41C80000 |
||||
41CC0000 41D00000 41D40000 41D80000 41DC0000 |
||||
41E00000 41E40000 41E80000 41EC0000 41F00000 |
||||
41F40000 41F80000 41FC0000 |
||||
=> |
||||
------------------------------------------------------------------------------ |
||||
|
||||
|
||||
The following sequence was performed to test the erase command: |
||||
|
||||
------------------------------------------------------------------------------ |
||||
=> cp 0 40080000 10 |
||||
Copy to Flash... done |
||||
=> erase 40080000 400bffff |
||||
Erase Flash from 0x40080000 to 0x400bffff |
||||
.. done |
||||
Erased 1 sectors |
||||
=> md 40080000 |
||||
40080000: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080010: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080020: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080030: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080040: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080050: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080060: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080070: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080080: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080090: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800a0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800b0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800c0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800d0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800e0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800f0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
=> cp 0 40080000 10 |
||||
Copy to Flash... done |
||||
=> erase 1:2 |
||||
Erase Flash Sectors 2-2 in Bank # 1 |
||||
.. done |
||||
=> md 40080000 |
||||
40080000: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080010: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080020: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080030: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080040: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080050: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080060: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080070: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080080: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080090: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800a0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800b0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800c0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800d0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800e0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800f0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
=> cp 0 40080000 10 |
||||
Copy to Flash... done |
||||
=> cp 0 400c0000 10 |
||||
Copy to Flash... done |
||||
=> erase 1:2-3 |
||||
Erase Flash Sectors 2-3 in Bank # 1 |
||||
... done |
||||
=> md 40080000 |
||||
40080000: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080010: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080020: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080030: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080040: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080050: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080060: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080070: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080080: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080090: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800a0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800b0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800c0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800d0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800e0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800f0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
=> md 400c0000 |
||||
400c0000: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c0010: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c0020: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c0030: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c0040: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c0050: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c0060: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c0070: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c0080: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c0090: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c00a0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c00b0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c00c0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c00d0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c00e0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400c00f0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
=> |
||||
------------------------------------------------------------------------------ |
||||
|
||||
|
||||
The following sequence was performed to test the Flash programming commands: |
||||
|
||||
------------------------------------------------------------------------------ |
||||
=> erase 40080000 400bffff |
||||
Erase Flash from 0x40080000 to 0x400bffff |
||||
.. done |
||||
Erased 1 sectors |
||||
=> cp 0 40080000 10 |
||||
Copy to Flash... done |
||||
=> md 0 |
||||
00000000: 00000000 00000104 61100200 01000000 ........a....... |
||||
00000010: 00000000 00000000 81140000 82000100 ................ |
||||
00000020: 01080000 00004000 22800000 00000600 ......@."....... |
||||
00000030: 00200800 00000000 10000100 00008000 . .............. |
||||
00000040: 00812000 00000200 00020000 80000000 .. ............. |
||||
00000050: 00028001 00001000 00040400 00000200 ................ |
||||
00000060: 20480000 00000000 20090000 00142000 H...... ..... . |
||||
00000070: 00000000 00004000 24210000 10000000 ......@.$!...... |
||||
00000080: 02440002 10000000 00200008 00000000 .D....... ...... |
||||
00000090: 02440900 00000000 30a40000 00004400 .D......0.....D. |
||||
000000a0: 04420800 00000000 00000040 00020000 .B.........@.... |
||||
000000b0: 05020000 00100000 00060000 00000000 ................ |
||||
000000c0: 00400000 00000000 00080000 00040000 .@.............. |
||||
000000d0: 10400000 00800004 00000000 00000200 .@.............. |
||||
000000e0: 80890000 00010004 00080000 00000020 ............... |
||||
000000f0: 08000000 10000000 00010000 00000000 ................ |
||||
=> md 40080000 |
||||
40080000: 00000000 00000104 61100200 01000000 ........a....... |
||||
40080010: 00000000 00000000 81140000 82000100 ................ |
||||
40080020: 01080000 00004000 22800000 00000600 ......@."....... |
||||
40080030: 00200800 00000000 10000100 00008000 . .............. |
||||
40080040: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080050: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080060: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080070: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080080: ffffffff ffffffff ffffffff ffffffff ................ |
||||
40080090: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800a0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800b0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800c0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800d0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800e0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
400800f0: ffffffff ffffffff ffffffff ffffffff ................ |
||||
=> |
||||
------------------------------------------------------------------------------ |
||||
|
||||
|
||||
The following sequence was performed to test storage of the environment |
||||
variables in Flash: |
||||
|
||||
------------------------------------------------------------------------------ |
||||
=> setenv foo bar |
||||
=> saveenv |
||||
Un-Protected 1 sectors |
||||
Erasing Flash... |
||||
.. done |
||||
Erased 1 sectors |
||||
Saving Environment to Flash... |
||||
Protected 1 sectors |
||||
=> reset |
||||
... |
||||
=> printenv |
||||
bootdelay=CONFIG_BOOTDELAY |
||||
baudrate=9600 |
||||
ipaddr=192.168.4.7 |
||||
serverip=192.168.4.1 |
||||
ethaddr=66:55:44:33:22:11 |
||||
foo=bar |
||||
stdin=serial |
||||
stdout=serial |
||||
stderr=serial |
||||
|
||||
Environment size: 170/262140 bytes |
||||
=> |
||||
------------------------------------------------------------------------------ |
||||
|
||||
|
||||
The following sequence was performed to test image download and run over |
||||
Ethernet interface (both interfaces were tested): |
||||
|
||||
------------------------------------------------------------------------------ |
||||
=> tftpboot 40000 hello_world.bin |
||||
ARP broadcast 1 |
||||
TFTP from server 192.168.2.2; our IP address is 192.168.2.7 |
||||
Filename 'hello_world.bin'. |
||||
Load address: 0x40000 |
||||
Loading: ############# |
||||
done |
||||
Bytes transferred = 65912 (10178 hex) |
||||
=> go 40004 |
||||
## Starting application at 0x00040004 ... |
||||
Hello World |
||||
argc = 1 |
||||
argv[0] = "40004" |
||||
argv[1] = "<NULL>" |
||||
Hit any key to exit ... |
||||
|
||||
## Application terminated, rc = 0x0 |
||||
=> |
||||
------------------------------------------------------------------------------ |
||||
|
||||
|
||||
The following sequence was performed to test eeprom read/write commands: |
||||
|
||||
------------------------------------------------------------------------------ |
||||
=> md 40000 |
||||
00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. |
||||
00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... |
||||
00040020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x |
||||
00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. |
||||
00040040: 7c0803a6 4e800021 813f004c 7f84e378 |...N..!.?.L...x |
||||
00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! |
||||
00040060: 7c1be000 4181003c 80bd0000 813f004c |...A..<.....?.L |
||||
00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... |
||||
00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. |
||||
00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... |
||||
000400a0: 813f004c 807e8010 80090010 7c0803a6 .?.L.~......|... |
||||
000400b0: 4e800021 813f004c 80090004 7c0803a6 N..!.?.L....|... |
||||
000400c0: 4e800021 2c030000 4182ffec 813f004c N..!,...A....?.L |
||||
000400d0: 80090000 7c0803a6 4e800021 813f004c ....|...N..!.?.L |
||||
000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! |
||||
000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. |
||||
=> eeprom write 40000 0 40 |
||||
|
||||
EEPROM write: addr 00040000 off 0000 count 64 ... done |
||||
=> mw 50000 0 1000 |
||||
=> eeprom read 50000 0 40 |
||||
|
||||
EEPROM read: addr 00050000 off 0000 count 64 ... done |
||||
=> md 50000 |
||||
00050000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. |
||||
00050010: 90010024 48000005 7fc802a6 801effe8 ...$H........... |
||||
00050020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x |
||||
00050030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. |
||||
00050040: 00000000 00000000 00000000 00000000 ................ |
||||
00050050: 00000000 00000000 00000000 00000000 ................ |
||||
00050060: 00000000 00000000 00000000 00000000 ................ |
||||
00050070: 00000000 00000000 00000000 00000000 ................ |
||||
00050080: 00000000 00000000 00000000 00000000 ................ |
||||
00050090: 00000000 00000000 00000000 00000000 ................ |
||||
000500a0: 00000000 00000000 00000000 00000000 ................ |
||||
000500b0: 00000000 00000000 00000000 00000000 ................ |
||||
000500c0: 00000000 00000000 00000000 00000000 ................ |
||||
000500d0: 00000000 00000000 00000000 00000000 ................ |
||||
000500e0: 00000000 00000000 00000000 00000000 ................ |
||||
000500f0: 00000000 00000000 00000000 00000000 ................ |
||||
=> |
||||
------------------------------------------------------------------------------ |
||||
|
||||
|
||||
Patch per Mon, 06 Aug 2001 17:57:27: |
||||
|
||||
- upgraded Flash support (added support for the following chips: |
||||
AM29LV800T/B, AM29LV160T/B, AM29DL322T/B, AM29DL323T/B) |
||||
- BCR tweakage for the 8260 bus mode |
||||
- SIUMCR tweakage enabling the MI interrupt (IRQ7) |
||||
|
||||
To simplify switching between the bus modes, a new configuration |
||||
option (CONFIG_BUSMODE_60x) has been added to the "config_TQM8260.h" |
||||
file. If it is defined, BCR will be configured for the 60x mode, |
||||
otherwise - for the 8260 mode. |
||||
|
||||
Concerning the SIUMCR modification: it's hard to predict whether it |
||||
will induce any problems on the other (60x mode) board. However, the |
||||
problems (if they appear) should be easy to notice - if the board |
||||
does not boot, it's most likely caused by the DPPC configuration in |
||||
SIUMCR. |
@ -0,0 +1,89 @@ |
||||
BEDBUG Support for U-Boot |
||||
-------------------------- |
||||
|
||||
These changes implement the bedbug (emBEDded deBUGger) debugger in U-Boot. |
||||
A specific implementation is made for the IBM405 processor but other flavors |
||||
can be easily implemented. |
||||
|
||||
##################### |
||||
### Modifications ### |
||||
##################### |
||||
|
||||
./common/Makefile |
||||
Included cmd_bedbug.c and bedbug.c in the Makefile. |
||||
|
||||
./common/command.c |
||||
Added bedbug commands to command table. |
||||
|
||||
./common/board.c |
||||
Added call to initialize debugger on startup. |
||||
|
||||
./cpu/ppc4xx/Makefile |
||||
Added bedbug_405.c to the Makefile. |
||||
|
||||
./cpu/ppc4xx/start.S |
||||
Added code to handle the debug exception (0x2000) on the 405. |
||||
Also added code to handle critical exceptions since the debug |
||||
is treated as critical on the 405. |
||||
|
||||
./cpu/ppc4xx/traps.c |
||||
Added more detailed output for the program exception to tell |
||||
if it is an illegal instruction, privileged instruction or |
||||
a trap. Also added debug trap handler. |
||||
|
||||
./include/cmd_confdefs.h |
||||
Added definition of CFG_CMD_BEDBUG. |
||||
|
||||
./include/config_WALNUT405.h |
||||
Added CFG_CMD_BEDBUG to the CONFIG_COMMANDS for the WALNUT. |
||||
|
||||
./include/ppc_asm.tmpl |
||||
Added code to handle critical exceptions |
||||
|
||||
################# |
||||
### New Stuff ### |
||||
################# |
||||
|
||||
./include/bedbug/ppc.h |
||||
./include/bedbug/regs.h |
||||
./include/bedbug/bedbug.h |
||||
./include/bedbug/elf.h [obsoleted by new include/elf.h] |
||||
./include/bedbug/tables.h |
||||
./include/cmd_bedbug.h |
||||
./common/cmd_bedbug.c |
||||
./common/bedbug.c |
||||
Bedbug library includes code for assembling and disassembling |
||||
PowerPC instructions to/from memory as well as handling |
||||
hardware breakpoints and stepping through code. These |
||||
routines are common to all PowerPC processors. |
||||
|
||||
./cpu/ppc4xx/bedbug_405.c |
||||
IBM PPC405 specific debugger routines. |
||||
|
||||
|
||||
|
||||
Bedbug support for the MPC860 |
||||
----------------------------- |
||||
|
||||
Changes: |
||||
|
||||
common/cmd_bedbug.c |
||||
Added call to initialize 860 debugger. |
||||
|
||||
cpu/mpc8xx/Makefile |
||||
Added new file "bedbug_860.c" to the makefile |
||||
|
||||
cpu/mpc8xx/start.S |
||||
Added handler for InstructionBreakpoint (0xfd00) |
||||
|
||||
cpu/mpc8xx/traps.c |
||||
Added new routine DebugException() |
||||
|
||||
include/config_MBX.h |
||||
Added CFG_CMD_BEDBUG to CONFIG_COMMANDS define |
||||
|
||||
|
||||
New Files: |
||||
|
||||
cpu/mpc8xx/bedbug_860.c |
||||
CPU-specific routines for 860 debug registers. |
@ -0,0 +1,54 @@ |
||||
This file contains status information for the port of U-Boot to the |
||||
Galileo Evaluation Board. |
||||
|
||||
Author: Josh Huber <huber@mclx.com> |
||||
Mission Critical Linux, Inc. |
||||
|
||||
The support for the Galileo Evaluation board is fairly minimal now. |
||||
It's sufficient to boot Linux, but doesn't provide too much more than |
||||
what's required to do this. |
||||
|
||||
Both DUART channels are supported (to use the second one, you have to |
||||
modify the board -- see the schematics for where to solder on the |
||||
devices module). The ethernet ports are supported, and the MPSC is |
||||
supported as a console driver. (keep in mind that the kernel has no |
||||
support for this yet) |
||||
|
||||
There are still occaisonal lockups with the MPSC console driver due to |
||||
(we think!) overrun problems. If you're looking for something stable |
||||
to use for Linux development, consider sticking with the DUART console |
||||
for now. |
||||
|
||||
Automatic memory sizing mostly works. We've had problems with some |
||||
combinations of memory. Please send us email if you're having trouble |
||||
with respect to the memory detection. |
||||
|
||||
Right now, only the 512k boot flash is supported. Support for the |
||||
16MB flash on the devices module is forthcoming. Right now the flash |
||||
is stored at the 256k boundry in flash, wasting a whole sector (64k!) |
||||
for environment data. This isn't really a big deal since we're not |
||||
using the 512k for anything else. (Just U-Boot and the environment) |
||||
|
||||
Finally, here is a sample output session: |
||||
|
||||
U-Boot 1.0.0-pre1 (Jun 6 2001 - 12:45:11) |
||||
|
||||
Initializing... |
||||
CPU: MPC7400 (altivec enabled) v2.9 |
||||
Board: EVB64260 |
||||
DRAM: 256 MB |
||||
FLASH: 512 kB |
||||
In: serial |
||||
Out: serial |
||||
Err: serial |
||||
|
||||
=> |
||||
|
||||
The default configuration should be correct for the evaluation board, |
||||
as it's shipped from Galileo. Keep in mind that the default baudrate |
||||
is set to 38400, 8N1. |
||||
|
||||
Good luck, and make sure to send any bugreports to us (or the |
||||
u-boot-users list). |
||||
|
||||
Josh |
@ -0,0 +1,22 @@ |
||||
This file contains status information for the port of U-Boot to the |
||||
Motorola mpc74xx series of CPUs. |
||||
|
||||
Author: Josh Huber <huber@mclx.com> |
||||
Mission Critical Linux, Inc. |
||||
|
||||
Currently the support for these CPUs is pretty minimal, but enough to |
||||
get things going. (much like the support for the Galileo Eval Board) |
||||
|
||||
There is a framework in place to enable the L2 cache, and to program |
||||
the BATs. Currently, there are still problems with the code which |
||||
sets up the L2 cache, so it's not enabled. (IMHO, it shouldn't be |
||||
anyway). Additionally, there is support for enabling the MMU, which |
||||
we also don't do. The BATs are programmed just for the benefit of |
||||
jumping into Linux in a sane configuration. |
||||
|
||||
Most of the code was based on other cpus supported by U-Boot. |
||||
|
||||
If you find any errors in the CPU setup code, please send us a note. |
||||
|
||||
Thanks, |
||||
Josh |
@ -0,0 +1,80 @@ |
||||
/* |
||||
* (C) Copyright 2001 |
||||
* Denis Peter, MPL AG Switzerland |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
USB Support for PIP405 and MIP405 (UHCI) |
||||
======================================== |
||||
|
||||
The USB support is implemented on the base of the UHCI Host |
||||
controller. |
||||
|
||||
Currently supported are USB Hubs, USB Keyboards and USB Floppys. |
||||
Tested with a TEAC Floppy TEAC FD-05PUB and Chicony KU-8933 Keyboard. |
||||
|
||||
How it works: |
||||
------------- |
||||
|
||||
The USB (at least the USB UHCI) needs a frame list (4k), transfer |
||||
descripor and queue headers which are all located in the main memory. |
||||
The UHCI allocates every milisecond the PCI bus and reads the current |
||||
frame pointer. This may cause to crash the OS during boot. So the USB |
||||
_MUST_ be stopped during OS boot. This is the reason, why the USB is |
||||
NOT automatically started during start-up. If someone needs the USB |
||||
he has to start it and should therefore be aware that he had to stop |
||||
it before booting the OS. |
||||
|
||||
For USB keyboards this can be done by a script which is automatically |
||||
started after the U-Boot is up and running. To boot an OS with a an |
||||
USB keyboard another script is necessary, which first disables the |
||||
USB and then executes the boot command. If the boot command fails, |
||||
the script can reenable the USB kbd. |
||||
|
||||
Common USB Commands: |
||||
- usb start: |
||||
- usb reset: (re)starts the USB. All USB devices will be |
||||
initialized and a device tree is build for them. |
||||
- usb tree: shows all USB devices in a tree like display |
||||
- usb info [dev]: shows all USB infos of the device dev, or of all |
||||
the devices |
||||
- usb stop [f]: stops the USB. If f==1 the USB will also stop if |
||||
an USB keyboard is assigned as stdin. The stdin |
||||
is then switched to serial input. |
||||
Storage USB Commands: |
||||
- usb scan: scans the USB for storage devices.The USB must be |
||||
running for this command (usb start) |
||||
- usb device [dev]: show or set current USB staorage device |
||||
- usb part [dev]: print partition table of one or all USB storage |
||||
devices |
||||
- usb read addr blk# cnt: |
||||
read `cnt' blocks starting at block `blk#'to |
||||
memory address `addr' |
||||
- usbboot addr dev:part: |
||||
boot from USB device |
||||
|
||||
Config Switches: |
||||
---------------- |
||||
CFG_CMD_USB enables basic USB support and the usb command |
||||
CONFIG_USB_UHCI defines the lowlevel part.A lowlevel part must be defined if |
||||
using CFG_CMD_USB |
||||
CONFIG_USB_KEYBOARD enables the USB Keyboard |
||||
CONFIG_USB_STORAGE enables the USB storage devices |
@ -0,0 +1,289 @@ |
||||
#ifndef _ASM_HYMOD_H_ |
||||
#define _ASM_HYMOD_H_ |
||||
|
||||
#include <linux/config.h> |
||||
#ifdef CONFIG_8260 |
||||
#include <asm/iopin_8260.h> |
||||
#endif |
||||
|
||||
/*
|
||||
* hymod configuration data - passed by boot code via the board information |
||||
* structure (only U-Boot has support for this at the moment) |
||||
* |
||||
* there are three types of data passed up from the boot monitor. the first |
||||
* (type hymod_eeprom_t) is the eeprom data that was read off both the main |
||||
* (or mother) board and the mezzanine board (if any). this data defines how |
||||
* many Xilinx fpgas are on each board, and their types (among other things). |
||||
* the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where |
||||
* in the physical address space the various Xilinx fpga access regions have |
||||
* been mapped by the boot rom. the third type of data (type xlx_iopins_t, |
||||
* one per Xilinx fpga) defines which io port pins are connected to the various |
||||
* signals required to program a Xilinx fpga. |
||||
* |
||||
* A ram/flash "bank" refers to memory controlled by the same chip select. |
||||
* |
||||
* the eeprom contents are defined as in technical note #2 - basically, |
||||
* a header, zero or more records in no particular order, and a 32 bit crc |
||||
* a record is 1 or more type bytes, a length byte and "length" bytes. |
||||
*/ |
||||
|
||||
#define HYMOD_EEPROM_ID 0xAA /* eeprom id byte */ |
||||
#define HYMOD_EEPROM_VER 1 /* eeprom contents version */ |
||||
#define HYMOD_EEPROM_SIZE 256 /* number of bytes in the eeprom */ |
||||
|
||||
/* eeprom header */ |
||||
typedef |
||||
struct { |
||||
unsigned char id; /* eeprom id byte */ |
||||
unsigned char ver; /* eeprom contents version number */ |
||||
unsigned long len; /* total # of bytes btw hdr and crc */ |
||||
} |
||||
hymod_eehdr_t; |
||||
|
||||
/* maximum number of bytes available for eeprom data records */ |
||||
#define HYMOD_EEPROM_MAXLEN (HYMOD_EEPROM_SIZE \ |
||||
- sizeof (hymod_eehdr_t) \
|
||||
- sizeof (unsigned long)) |
||||
|
||||
/* eeprom data record */ |
||||
typedef |
||||
union { |
||||
struct { |
||||
unsigned char topbit:1; |
||||
unsigned char type:7; |
||||
unsigned char len; |
||||
unsigned char data[1]; /* variable length */ |
||||
} small; |
||||
struct { |
||||
unsigned short topbit:1; |
||||
unsigned short nxtbit:1; |
||||
unsigned short type:14; |
||||
unsigned short len; |
||||
unsigned char data[1]; /* variable length */ |
||||
} medium; |
||||
struct { |
||||
unsigned long topbit:1; |
||||
unsigned long nxtbit:1; |
||||
unsigned long type:30; |
||||
unsigned long len; |
||||
unsigned char data[1]; /* variable length */ |
||||
} large; |
||||
} |
||||
hymod_eerec_t; |
||||
|
||||
#define HYMOD_EEOFF_MAIN 0x00 /* i2c addr offset for main eeprom */ |
||||
#define HYMOD_EEOFF_MEZZ 0x04 /* i2c addr offset for mezz eepomr */ |
||||
|
||||
/* eeprom record types */ |
||||
#define HYMOD_EEREC_SERNO 1 /* serial number */ |
||||
#define HYMOD_EEREC_DATE 2 /* date */ |
||||
#define HYMOD_EEREC_BATCH 3 /* batch id */ |
||||
#define HYMOD_EEREC_TYPE 4 /* board type */ |
||||
#define HYMOD_EEREC_REV 5 /* revision number */ |
||||
#define HYMOD_EEREC_SDRAM 6 /* sdram sizes */ |
||||
#define HYMOD_EEREC_FLASH 7 /* flash sizes */ |
||||
#define HYMOD_EEREC_ZBT 8 /* zbt ram sizes */ |
||||
#define HYMOD_EEREC_XLXTYP 9 /* Xilinx fpga types */ |
||||
#define HYMOD_EEREC_XLXSPD 10 /* Xilinx fpga speeds */ |
||||
#define HYMOD_EEREC_XLXTMP 11 /* Xilinx fpga temperatures */ |
||||
#define HYMOD_EEREC_XLXGRD 12 /* Xilinx fpga grades */ |
||||
#define HYMOD_EEREC_CPUTYP 13 /* Motorola CPU type */ |
||||
#define HYMOD_EEREC_CPUSPD 14 /* CPU speed */ |
||||
#define HYMOD_EEREC_BUSSPD 15 /* bus speed */ |
||||
#define HYMOD_EEREC_CPMSPD 16 /* CPM speed */ |
||||
#define HYMOD_EEREC_HSTYPE 17 /* high-speed serial chip type */ |
||||
#define HYMOD_EEREC_HSCHIN 18 /* high-speed serial input channels */ |
||||
#define HYMOD_EEREC_HSCHOUT 19 /* high-speed serial output channels */ |
||||
|
||||
/* some dimensions */ |
||||
#define HYMOD_MAX_BATCH 32 /* max no. of bytes in batch id */ |
||||
#define HYMOD_MAX_SDRAM 4 /* max sdram "banks" on any board */ |
||||
#define HYMOD_MAX_FLASH 4 /* max flash "banks" on any board */ |
||||
#define HYMOD_MAX_ZBT 16 /* max ZBT rams on any board */ |
||||
#define HYMOD_MAX_XLX 4 /* max Xilinx fpgas on any board */ |
||||
|
||||
#define HYMOD_MAX_BYTES 16 /* enough to store any bytes array */ |
||||
|
||||
/* board types */ |
||||
#define HYMOD_BDTYPE_NONE 0 /* information not present */ |
||||
#define HYMOD_BDTYPE_IO 1 /* I/O main board */ |
||||
#define HYMOD_BDTYPE_CLP 2 /* CLP main board */ |
||||
#define HYMOD_BDTYPE_DSP 3 /* DSP main board */ |
||||
#define HYMOD_BDTYPE_INPUT 4 /* video input mezzanine board */ |
||||
#define HYMOD_BDTYPE_ALTINPUT 5 /* video input mezzanine board */ |
||||
#define HYMOD_BDTYPE_DISPLAY 6 /* video display mezzanine board */ |
||||
#define HYMOD_BDTYPE_MAX 7 /* first invalid value */ |
||||
|
||||
/* Xilinx fpga types */ |
||||
#define HYMOD_XTYP_NONE 0 /* information not present */ |
||||
#define HYMOD_XTYP_XCV300E 1 /* Xilinx Virtex 300 */ |
||||
#define HYMOD_XTYP_XCV400E 2 /* Xilinx Virtex 400 */ |
||||
#define HYMOD_XTYP_XCV600E 3 /* Xilinx Virtex 600 */ |
||||
#define HYMOD_XTYP_MAX 4 /* first invalid value */ |
||||
|
||||
/* Xilinx fpga speeds */ |
||||
#define HYMOD_XSPD_NONE 0 /* information not present */ |
||||
#define HYMOD_XSPD_SIX 1 |
||||
#define HYMOD_XSPD_SEVEN 2 |
||||
#define HYMOD_XSPD_EIGHT 3 |
||||
#define HYMOD_XSPD_MAX 4 /* first invalid value */ |
||||
|
||||
/* Xilinx fpga temperatures */ |
||||
#define HYMOD_XTMP_NONE 0 /* information not present */ |
||||
#define HYMOD_XTMP_COM 1 |
||||
#define HYMOD_XTMP_IND 2 |
||||
#define HYMOD_XTMP_MAX 3 /* first invalid value */ |
||||
|
||||
/* Xilinx fpga grades */ |
||||
#define HYMOD_XTMP_NONE 0 /* information not present */ |
||||
#define HYMOD_XTMP_NORMAL 1 |
||||
#define HYMOD_XTMP_ENGSAMP 2 |
||||
#define HYMOD_XTMP_MAX 3 /* first invalid value */ |
||||
|
||||
/* CPU types */ |
||||
#define HYMOD_CPUTYPE_NONE 0 /* information not present */ |
||||
#define HYMOD_CPUTYPE_MPC8260 1 /* Motorola MPC8260 embedded powerpc */ |
||||
#define HYMOD_CPUTYPE_MAX 2 /* first invalid value */ |
||||
|
||||
/* CPU/BUS/CPM clock speeds */ |
||||
#define HYMOD_CLKSPD_NONE 0 /* information not present */ |
||||
#define HYMOD_CLKSPD_33MHZ 1 |
||||
#define HYMOD_CLKSPD_66MHZ 2 |
||||
#define HYMOD_CLKSPD_100MHZ 3 |
||||
#define HYMOD_CLKSPD_133MHZ 4 |
||||
#define HYMOD_CLKSPD_166MHZ 5 |
||||
#define HYMOD_CLKSPD_200MHZ 6 |
||||
#define HYMOD_CLKSPD_MAX 7 /* first invalid value */ |
||||
|
||||
/* high speed serial chip types */ |
||||
#define HYMOD_HSSTYPE_NONE 0 /* information not present */ |
||||
#define HYMOD_HSSTYPE_AMCC52064 1 |
||||
#define HYMOD_HSSTYPE_MAX 2 /* first invalid value */ |
||||
|
||||
/* a date (yyyy-mm-dd) */ |
||||
typedef |
||||
struct { |
||||
unsigned short year; |
||||
unsigned char month; |
||||
unsigned char day; |
||||
} |
||||
hymod_date_t; |
||||
|
||||
/* describes a Xilinx fpga */ |
||||
typedef |
||||
struct { |
||||
unsigned char type; /* chip type */ |
||||
unsigned char speed; /* chip speed rating */ |
||||
unsigned char temp; /* chip temperature rating */ |
||||
unsigned char grade; /* chip grade */ |
||||
} |
||||
hymod_xlx_t; |
||||
|
||||
/* describes a Motorola embedded processor */ |
||||
typedef |
||||
struct { |
||||
unsigned char type; /* CPU type */ |
||||
unsigned char cpuspd; /* speed of the PowerPC core */ |
||||
unsigned char busspd; /* speed of the system and 60x bus */ |
||||
unsigned char cpmspd; /* speed of the CPM co-processor */ |
||||
} |
||||
hymod_mpc_t; |
||||
|
||||
/* info about high-speed (1Gbit) serial interface */ |
||||
typedef |
||||
struct { |
||||
unsigned char type; /* high-speed serial chip type */ |
||||
unsigned char nchin; /* number of input channels mounted */ |
||||
unsigned char nchout; /* number of output channels mounted */ |
||||
} |
||||
hymod_hss_t; |
||||
|
||||
/*
|
||||
* this defines the contents of the serial eeprom that exists on every |
||||
* hymod board, including mezzanine boards (the serial eeprom will be |
||||
* faked for early development boards that don't have one) |
||||
*/ |
||||
|
||||
typedef |
||||
struct { |
||||
unsigned char ver; /* eeprom contents version */ |
||||
unsigned char bdtype; /* board type */ |
||||
unsigned char bdrev; /* board revision */ |
||||
unsigned char batchlen; /* length of batch string below */ |
||||
unsigned long serno; /* serial number */ |
||||
hymod_date_t date; /* manufacture date */ |
||||
unsigned char batch[32]; /* manufacturer specific batch id */ |
||||
unsigned char nsdram; /* # of ram "banks" */ |
||||
unsigned char nflash; /* # of flash "banks" */ |
||||
unsigned char nzbt; /* # of ZBT rams */ |
||||
unsigned char nxlx; /* # of Xilinx fpgas */ |
||||
unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */ |
||||
unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */ |
||||
unsigned char zbtsz[HYMOD_MAX_ZBT]; /* log2 of ZBT ram size */ |
||||
hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */ |
||||
hymod_mpc_t mpc; /* Motorola MPC CPU info */ |
||||
hymod_hss_t hss; /* high-speed serial info */ |
||||
} |
||||
hymod_eeprom_t; |
||||
|
||||
/*
|
||||
* this defines a region in the processor's physical address space |
||||
*/ |
||||
typedef |
||||
struct { |
||||
unsigned long exists:1; /* 1 if the region exists, 0 if not */ |
||||
unsigned long size:31; /* size in bytes */ |
||||
unsigned long base; /* base address */ |
||||
} |
||||
xlx_prgn_t; |
||||
|
||||
/*
|
||||
* this defines where the various Xilinx fpga access regions are mapped |
||||
* into the physical address space of the processor |
||||
*/ |
||||
typedef |
||||
struct { |
||||
xlx_prgn_t prog; /* program access region */ |
||||
xlx_prgn_t reg; /* register access region */ |
||||
xlx_prgn_t port; /* port access region */ |
||||
} |
||||
xlx_mmap_t; |
||||
|
||||
/*
|
||||
* this defines which 8260 i/o port pins are connected to the various |
||||
* signals required for programming a Xilinx fpga |
||||
*/ |
||||
typedef |
||||
struct { |
||||
iopin_t prog_pin; /* assert for >= 300ns to program */ |
||||
iopin_t init_pin; /* goes high when fpga is cleared */ |
||||
iopin_t done_pin; /* goes high when program is done */ |
||||
iopin_t enable_pin; /* some fpgas need enabling */ |
||||
} |
||||
xlx_iopins_t; |
||||
|
||||
/* all info about one hymod board */ |
||||
typedef |
||||
struct { |
||||
unsigned char eeprom_valid:1; |
||||
hymod_eeprom_t eeprom; |
||||
xlx_mmap_t mmap[HYMOD_MAX_XLX]; |
||||
xlx_iopins_t iopins[HYMOD_MAX_XLX]; |
||||
} |
||||
hymod_board_t; |
||||
|
||||
/*
|
||||
* this defines the configuration information of a hymod board-set |
||||
* (main board + possible mezzanine board). In future, there may be |
||||
* more than one mezzanine board (stackable?) - if so, add a "mezz2" |
||||
* field, and so on... or make mezz an array? |
||||
*/ |
||||
typedef |
||||
struct { |
||||
hymod_board_t main; /* main board info */ |
||||
hymod_board_t mezz; /* mezzanine board info */ |
||||
unsigned long crc; /* ensures kernel and boot prom agree */ |
||||
} |
||||
hymod_conf_t; |
||||
|
||||
#endif /* _ASM_HYMOD_H_ */ |
@ -0,0 +1,52 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Murray Jensen <Murray.Jensen@cmst.csiro.au> and |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* KGDB support |
||||
*/ |
||||
#ifndef _CMD_KGDB_H |
||||
#define _CMD_KGDB_H |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CMD_TBL_KGDB MK_CMD_TBL_ENTRY( \ |
||||
"kgdb", 4, CFG_MAXARGS, 1, do_kgdb, \
|
||||
"kgdb - enter gdb remote debug mode\n", \
|
||||
"[arg0 arg1 .. argN]\n" \
|
||||
" - executes a breakpoint so that kgdb mode is\n" \
|
||||
" entered via the exception handler. To return\n" \
|
||||
" to the monitor, the remote gdb debugger must\n" \
|
||||
" execute a \"continue\" or \"quit\" command.\n" \
|
||||
"\n" \
|
||||
" if a program is loaded by the remote gdb, any args\n" \
|
||||
" passed to the kgdb command are given to the loaded\n" \
|
||||
" program if it is executed (see the \"hello_world\"\n" \
|
||||
" example program in the U-Boot examples directory)." \
|
||||
), |
||||
|
||||
int do_kgdb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
||||
#else |
||||
#define CMD_TBL_KGDB |
||||
#endif |
||||
|
||||
#endif /* _CMD_KGDB_H */ |
@ -0,0 +1,428 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __COMMON_H_ |
||||
#define __COMMON_H_ 1 |
||||
|
||||
#undef _LINUX_CONFIG_H |
||||
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ |
||||
|
||||
typedef unsigned char uchar; |
||||
typedef volatile unsigned long vu_long; |
||||
typedef volatile unsigned short vu_short; |
||||
typedef volatile unsigned char vu_char; |
||||
|
||||
#include <config.h> |
||||
#include <linux/bitops.h> |
||||
#include <linux/types.h> |
||||
#include <linux/string.h> |
||||
#include <asm/ptrace.h> |
||||
#include <stdarg.h> |
||||
#if defined(CONFIG_PCI) && defined(CONFIG_440) |
||||
#include <pci.h> |
||||
#endif |
||||
#ifdef CONFIG_8xx |
||||
#include <asm/8xx_immap.h> |
||||
#elif defined(CONFIG_8260) |
||||
#include <asm/immap_8260.h> |
||||
#endif |
||||
#ifdef CONFIG_4xx |
||||
#include <ppc4xx.h> |
||||
#endif |
||||
#ifdef CONFIG_HYMOD |
||||
#include <asm/hymod.h> |
||||
#endif |
||||
#ifdef CONFIG_ARM |
||||
#define asmlinkage /* nothing */ |
||||
#endif |
||||
|
||||
#include <part.h> |
||||
#include <flash.h> |
||||
#include <image.h> |
||||
|
||||
#ifdef DEBUG |
||||
#define debug(fmt,args...) printf (fmt ,##args) |
||||
#else |
||||
#define debug(fmt,args...) |
||||
#endif /* DEBUG */ |
||||
|
||||
typedef void (interrupt_handler_t)(void *); |
||||
|
||||
#include <asm/u-boot.h> /* boot information for Linux kernel */ |
||||
#include <asm/global_data.h> /* global data used for startup functions */ |
||||
|
||||
/* enable common handling for all TQM8xxL boards */ |
||||
#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \ |
||||
defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) |
||||
# ifndef CONFIG_TQM8xxL |
||||
# define CONFIG_TQM8xxL |
||||
# endif |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Function Prototypes |
||||
*/ |
||||
|
||||
#if CONFIG_SERIAL_SOFTWARE_FIFO |
||||
void serial_buffered_init (void); |
||||
void serial_buffered_putc (const char); |
||||
void serial_buffered_puts (const char *); |
||||
int serial_buffered_getc (void); |
||||
int serial_buffered_tstc (void); |
||||
#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ |
||||
|
||||
void hang (void) __attribute__ ((noreturn)); |
||||
|
||||
/* */ |
||||
long int initdram (int); |
||||
int display_options (void); |
||||
void print_size (ulong, const char *); |
||||
|
||||
/* common/main.c */ |
||||
void main_loop (void); |
||||
int run_command (const char *cmd, int flag); |
||||
int readline (const char *const prompt); |
||||
void reset_cmd_timeout(void); |
||||
|
||||
/* common/board.c */ |
||||
void board_init_f (ulong); |
||||
void board_init_r (gd_t *, ulong); |
||||
int checkboard (void); |
||||
int checkflash (void); |
||||
int checkdram (void); |
||||
char * strmhz(char *buf, long hz); |
||||
int last_stage_init(void); |
||||
|
||||
/* common/flash.c */ |
||||
void flash_perror (int); |
||||
|
||||
/* common/cmd_bootm.c */ |
||||
void print_image_hdr (image_header_t *hdr); |
||||
|
||||
extern ulong load_addr; /* Default Load Address */ |
||||
|
||||
/* common/cmd_nvedit.c */ |
||||
int env_init (void); |
||||
void env_relocate (void); |
||||
char *getenv (uchar *); |
||||
int getenv_r (uchar *name, uchar *buf, unsigned len); |
||||
int saveenv (void); |
||||
#ifdef CONFIG_PPC /* ARM version to be fixed! */ |
||||
void inline setenv (char *, char *); |
||||
#endif /* CONFIG_PPC */ |
||||
#ifdef CONFIG_ARM |
||||
# include <asm/u-boot-arm.h> /* ARM version to be fixed! */ |
||||
#endif /* CONFIG_ARM */ |
||||
|
||||
void pci_init (void); |
||||
void pciinfo (int, int); |
||||
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_440) |
||||
# if defined(CFG_PCI_PRE_INIT) |
||||
int pci_pre_init (struct pci_controller * ); |
||||
# endif |
||||
# if defined(CFG_PCI_TARGET_INIT) |
||||
void pci_target_init (struct pci_controller *); |
||||
# endif |
||||
# if defined(CFG_PCI_MASTER_INIT) |
||||
void pci_master_init (struct pci_controller *); |
||||
# endif |
||||
int is_pci_host (struct pci_controller *); |
||||
#endif |
||||
|
||||
int misc_init_f (void); |
||||
int misc_init_r (void); |
||||
|
||||
/* $(BOARD)/$(BOARD).c */ |
||||
void reset_phy (void); |
||||
|
||||
/* $(BOARD)/eeprom.c */ |
||||
void eeprom_init (void); |
||||
int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); |
||||
int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); |
||||
#ifdef CONFIG_LWMON |
||||
extern uchar pic_read (uchar reg); |
||||
extern void pic_write (uchar reg, uchar val); |
||||
#endif |
||||
|
||||
/*
|
||||
* Set this up regardless of board |
||||
* type, to prevent errors. |
||||
*/ |
||||
#if defined(CONFIG_SPI) || !defined(CFG_I2C_EEPROM_ADDR) |
||||
# define CFG_DEF_EEPROM_ADDR 0 |
||||
#else |
||||
# define CFG_DEF_EEPROM_ADDR CFG_I2C_EEPROM_ADDR |
||||
#endif /* CONFIG_SPI || !defined(CFG_I2C_EEPROM_ADDR) */ |
||||
|
||||
#if defined(CONFIG_PCU_E) || defined(CONFIG_CCM) |
||||
extern void spi_init_f (void); |
||||
extern void spi_init_r (void); |
||||
extern ssize_t spi_read (uchar *, int, uchar *, int); |
||||
extern ssize_t spi_write (uchar *, int, uchar *, int); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_RPXCLASSIC |
||||
void rpxclassic_init (void); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MBX |
||||
/* $(BOARD)/mbx8xx.c */ |
||||
void mbx_init (void); |
||||
void board_serial_init (void); |
||||
void board_ether_init (void); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || defined(CONFIG_IAD210) |
||||
void board_get_enetaddr (uchar *addr); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_HERMES |
||||
/* $(BOARD)/hermes.c */ |
||||
void hermes_start_lxt980 (int speed); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_EVB64260 |
||||
void evb64260_init(void); |
||||
void debug_led(int, int); |
||||
void display_mem_map(void); |
||||
void perform_soft_reset(void); |
||||
#endif |
||||
|
||||
void load_sernum_ethaddr (void); |
||||
|
||||
/* $(BOARD)/$(BOARD).c */ |
||||
int board_pre_init (void); |
||||
int board_postclk_init (void); /* after clocks/timebase, before env/serial */ |
||||
void board_poweroff (void); |
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int testdram(void); |
||||
#endif /* CFG_DRAM_TEST */ |
||||
|
||||
/* $(CPU)/start.S */ |
||||
#ifdef CONFIG_8xx |
||||
uint get_immr (uint); |
||||
#endif |
||||
uint get_pvr (void); |
||||
uint rd_ic_cst (void); |
||||
void wr_ic_cst (uint); |
||||
void wr_ic_adr (uint); |
||||
uint rd_dc_cst (void); |
||||
void wr_dc_cst (uint); |
||||
void wr_dc_adr (uint); |
||||
int icache_status (void); |
||||
void icache_enable (void); |
||||
void icache_disable(void); |
||||
int dcache_status (void); |
||||
void dcache_enable (void); |
||||
void dcache_disable(void); |
||||
void relocate_code (ulong, gd_t *, ulong); |
||||
ulong get_endaddr (void); |
||||
void trap_init (ulong); |
||||
#if defined (CONFIG_4xx) || \ |
||||
defined (CONFIG_74xx_7xx) || \
|
||||
defined (CONFIG_74x) || \
|
||||
defined (CONFIG_75x) || \
|
||||
defined (CONFIG_74xx) |
||||
unsigned char in8(unsigned int); |
||||
void out8(unsigned int, unsigned char); |
||||
unsigned short in16(unsigned int); |
||||
unsigned short in16r(unsigned int); |
||||
void out16(unsigned int, unsigned short value); |
||||
void out16r(unsigned int, unsigned short value); |
||||
unsigned long in32(unsigned int); |
||||
unsigned long in32r(unsigned int); |
||||
void out32(unsigned int, unsigned long value); |
||||
void out32r(unsigned int, unsigned long value); |
||||
void ppcDcbf(unsigned long value); |
||||
void ppcDcbi(unsigned long value); |
||||
void ppcSync(void); |
||||
#endif |
||||
|
||||
/* $(CPU)/cpu.c */ |
||||
int checkcpu (void); |
||||
int checkicache (void); |
||||
int checkdcache (void); |
||||
void upmconfig (unsigned int, unsigned int *, unsigned int); |
||||
ulong get_tbclk (void); |
||||
|
||||
/* $(CPU)/serial.c */ |
||||
int serial_init (void); |
||||
void serial_setbrg (void); |
||||
void serial_putc (const char); |
||||
void serial_puts (const char *); |
||||
void serial_addr (unsigned int); |
||||
int serial_getc (void); |
||||
int serial_tstc (void); |
||||
|
||||
/* $(CPU)/speed.c */ |
||||
int get_clocks (void); |
||||
#if defined(CONFIG_8260) |
||||
int prt_8260_clks (void); |
||||
#endif |
||||
#ifdef CONFIG_4xx |
||||
ulong get_OPB_freq (void); |
||||
ulong get_PCI_freq (void); |
||||
#endif |
||||
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) |
||||
ulong get_FCLK (void); |
||||
ulong get_HCLK (void); |
||||
ulong get_PCLK (void); |
||||
ulong get_UCLK (void); |
||||
#endif |
||||
ulong get_bus_freq (ulong); |
||||
|
||||
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480) |
||||
# if defined(CONFIG_440) |
||||
typedef PPC440_SYS_INFO sys_info_t; |
||||
# else |
||||
typedef PPC405_SYS_INFO sys_info_t; |
||||
# endif |
||||
void get_sys_info ( sys_info_t * ); |
||||
#endif |
||||
|
||||
/* $(CPU)/cpu_init.c */ |
||||
#if defined(CONFIG_8xx) || defined(CONFIG_8260) |
||||
void cpu_init_f (volatile immap_t *immr); |
||||
#endif |
||||
#ifdef CONFIG_4xx |
||||
void cpu_init_f (void); |
||||
#endif |
||||
int cpu_init_r (void); |
||||
#if defined(CONFIG_8260) |
||||
int prt_8260_rsr (void); |
||||
#endif |
||||
|
||||
/* $(CPU)/interrupts.c */ |
||||
int interrupt_init (void); |
||||
void timer_interrupt (struct pt_regs *); |
||||
void external_interrupt (struct pt_regs *); |
||||
void irq_install_handler(int, interrupt_handler_t *, void *); |
||||
void irq_free_handler (int); |
||||
void reset_timer (void); |
||||
ulong get_timer (ulong base); |
||||
void set_timer (ulong t); |
||||
void enable_interrupts (void); |
||||
int disable_interrupts (void); |
||||
|
||||
/* $(CPU)/.../commproc.c */ |
||||
int dpram_init (void); |
||||
uint dpram_base(void); |
||||
uint dpram_base_align(uint align); |
||||
uint dpram_alloc(uint size); |
||||
uint dpram_alloc_align(uint size,uint align); |
||||
void post_word_store (ulong); |
||||
ulong post_word_load (void); |
||||
|
||||
/* $(CPU)/.../<eth> */ |
||||
void mii_init (void); |
||||
|
||||
/* $(CPU)/.../lcd.c */ |
||||
ulong lcd_setmem (ulong); |
||||
|
||||
/* $(CPU)/.../vfd.c */ |
||||
ulong vfd_setmem (ulong); |
||||
|
||||
/* $(CPU)/.../video.c */ |
||||
ulong video_setmem (ulong); |
||||
|
||||
/* ppc/cache.c */ |
||||
void flush_cache (unsigned long, unsigned long); |
||||
|
||||
/* ppc/ticks.S */ |
||||
unsigned long long get_ticks(void); |
||||
void wait_ticks (unsigned long); |
||||
|
||||
/* ppc/time.c */ |
||||
void udelay (unsigned long); |
||||
ulong usec2ticks (unsigned long usec); |
||||
ulong ticks2usec (unsigned long ticks); |
||||
int init_timebase (void); |
||||
|
||||
/* ppc/vsprintf.c */ |
||||
ulong simple_strtoul(const char *cp,char **endp,unsigned int base); |
||||
long simple_strtol(const char *cp,char **endp,unsigned int base); |
||||
void panic(const char *fmt, ...); |
||||
int sprintf(char * buf, const char *fmt, ...); |
||||
int vsprintf(char *buf, const char *fmt, va_list args); |
||||
|
||||
/* ppc/crc32.c */ |
||||
ulong crc32 (ulong, const unsigned char *, uint); |
||||
ulong crc32_no_comp (ulong, const unsigned char *, uint); |
||||
|
||||
/* common/console.c */ |
||||
extern void **syscall_tbl; |
||||
|
||||
int console_init_f(void); /* Before relocation; uses the serial stuff */ |
||||
int console_init_r(void); /* After relocation; uses the console stuff */ |
||||
int console_assign (int file, char *devname); /* Assign the console */ |
||||
int ctrlc (void); |
||||
int had_ctrlc (void); /* have we had a Control-C since last clear? */ |
||||
void clear_ctrlc (void); /* clear the Control-C condition */ |
||||
int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */ |
||||
|
||||
/*
|
||||
* STDIO based functions (can always be used) |
||||
*/ |
||||
|
||||
/* serial stuff */ |
||||
void serial_printf (const char *fmt, ...); |
||||
|
||||
/* stdin */ |
||||
int getc(void); |
||||
int tstc(void); |
||||
|
||||
/* stdout */ |
||||
void putc(const char c); |
||||
void puts(const char *s); |
||||
void printf(const char *fmt, ...); |
||||
|
||||
/* stderr */ |
||||
#define eputc(c) fputc(stderr, c) |
||||
#define eputs(s) fputs(stderr, s) |
||||
#define eprintf(fmt,args...) fprintf(stderr,fmt ,##args) |
||||
|
||||
/*
|
||||
* FILE based functions (can only be used AFTER relocation!) |
||||
*/ |
||||
|
||||
#define stdin 0 |
||||
#define stdout 1 |
||||
#define stderr 2 |
||||
#define MAX_FILES 3 |
||||
|
||||
void fprintf(int file, const char *fmt, ...); |
||||
void fputs(int file, const char *s); |
||||
void fputc(int file, const char c); |
||||
int ftstc(int file); |
||||
int fgetc(int file); |
||||
|
||||
int pcmcia_init (void); |
||||
|
||||
#ifdef CONFIG_SHOW_BOOT_PROGRESS |
||||
void show_boot_progress (int status); |
||||
#endif |
||||
|
||||
#endif /* __COMMON_H_ */ |
@ -0,0 +1,452 @@ |
||||
/*
|
||||
* (C) Copyright 2002 ELTEC Elektronik AG |
||||
* Frank Gottschling <fgottschling@eltec.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <asm/processor.h> |
||||
|
||||
#undef DEBUG |
||||
#define GTREGREAD(x) 0xffffffff /* needed for debug */ |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
/* these hardware addresses are pretty bogus, please change them to
|
||||
suit your needs */ |
||||
|
||||
/* first ethernet */ |
||||
#define CONFIG_ETHADDR 00:00:5b:ee:de:ad |
||||
|
||||
#define CONFIG_IPADDR 192.168.0.105 |
||||
#define CONFIG_SERVERIP 192.168.0.100 |
||||
|
||||
#define CONFIG_BAB7xx 1 /* this is an BAB740/BAB750 board */ |
||||
|
||||
#define CONFIG_BAUDRATE 9600 /* console baudrate */ |
||||
|
||||
#undef CONFIG_WATCHDOG |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp 1000000; " \
|
||||
"setenv bootargs root=ramfs console=ttyS00,9600 " \
|
||||
"ip=$(ipaddr):$(serverip):$(rootpath):$(gatewayip):" \
|
||||
"$(netmask):$(hostname):eth0:none; " \
|
||||
"bootm" |
||||
|
||||
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\ |
||||
CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE |\
|
||||
CFG_CMD_FDC | CFG_CMD_ELF) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
/*
|
||||
* choose between COM1 and COM2 as serial console |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x1000000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* dec. freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
#define CFG_BOARD_ASM_INIT |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/*
|
||||
* Choose the address mapping scheme for the MPC106 mem controller. |
||||
* Default is mapping B (CHRP), set this define to choose mapping A (PReP). |
||||
*/ |
||||
#define CFG_ADDRESS_MAP_A |
||||
#ifdef CFG_ADDRESS_MAP_A |
||||
|
||||
#define CFG_PCI_MEMORY_BUS 0x80000000 |
||||
#define CFG_PCI_MEMORY_PHYS 0x00000000 |
||||
#define CFG_PCI_MEMORY_SIZE 0x80000000 |
||||
|
||||
#define CFG_PCI_MEM_BUS 0x00000000 |
||||
#define CFG_PCI_MEM_PHYS 0xc0000000 |
||||
#define CFG_PCI_MEM_SIZE 0x3f000000 |
||||
|
||||
#define CFG_ISA_MEM_BUS 0 |
||||
#define CFG_ISA_MEM_PHYS 0 |
||||
#define CFG_ISA_MEM_SIZE 0 |
||||
|
||||
#define CFG_PCI_IO_BUS 0x1000 |
||||
#define CFG_PCI_IO_PHYS 0x81000000 |
||||
#define CFG_PCI_IO_SIZE 0x01000000-CFG_PCI_IO_BUS |
||||
|
||||
#define CFG_ISA_IO_BUS 0x00000000 |
||||
#define CFG_ISA_IO_PHYS 0x80000000 |
||||
#define CFG_ISA_IO_SIZE 0x00800000 |
||||
|
||||
#else |
||||
|
||||
#define CFG_PCI_MEMORY_BUS 0x00000000 |
||||
#define CFG_PCI_MEMORY_PHYS 0x00000000 |
||||
#define CFG_PCI_MEMORY_SIZE 0x40000000 |
||||
|
||||
#define CFG_PCI_MEM_BUS 0x80000000 |
||||
#define CFG_PCI_MEM_PHYS 0x80000000 |
||||
#define CFG_PCI_MEM_SIZE 0x7d000000 |
||||
|
||||
#define CFG_ISA_MEM_BUS 0x00000000 |
||||
#define CFG_ISA_MEM_PHYS 0xfd000000 |
||||
#define CFG_ISA_MEM_SIZE 0x01000000 |
||||
|
||||
#define CFG_PCI_IO_BUS 0x00800000 |
||||
#define CFG_PCI_IO_PHYS 0xfe800000 |
||||
#define CFG_PCI_IO_SIZE 0x00400000 |
||||
|
||||
#define CFG_ISA_IO_BUS 0x00000000 |
||||
#define CFG_ISA_IO_PHYS 0xfe000000 |
||||
#define CFG_ISA_IO_SIZE 0x00800000 |
||||
|
||||
#endif /*CFG_ADDRESS_MAP_A */ |
||||
|
||||
#define CFG_60X_PCI_MEM_OFFSET 0x00000000 |
||||
|
||||
/* driver defines FDC,IDE,... */ |
||||
#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS |
||||
#define CFG_ISA_IO CFG_ISA_IO_PHYS |
||||
#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS |
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xfff00000 |
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */ |
||||
#define CFG_INIT_RAM_END 0x4000 |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*
|
||||
* Flash mapping/organization on the MPC10x. |
||||
*/ |
||||
#define FLASH_BASE0_PRELIM 0xff800000 |
||||
#define FLASH_BASE1_PRELIM 0xffc00000 |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ |
||||
#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ |
||||
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */ |
||||
#undef CFG_MEMTEST |
||||
|
||||
/*
|
||||
* Environment settings |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
||||
#define CFG_NVRAM_SIZE 0x1ff0 /* NVRAM size (8kB), we must protect the clock data (16 bytes) */ |
||||
#define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */ |
||||
/*
|
||||
* We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus, |
||||
* user applications can use the remaining space for other purposes. |
||||
*/ |
||||
#define CFG_ENV_ADDR (CFG_NVRAM_SIZE +0x10 -0x800) |
||||
#define CFG_NV_SROM_COPY_ADDR (CFG_NVRAM_SIZE +0x10 -0x400) |
||||
#define CFG_NVRAM_ACCESS_ROUTINE /* This board needs a special routine to access the NVRAM */ |
||||
#define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */ |
||||
|
||||
/*
|
||||
* Serial devices |
||||
*/ |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK 1843200 |
||||
#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) |
||||
#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) |
||||
|
||||
/*
|
||||
* PCI stuff |
||||
*/ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_PNP /* pci plug-and-play */ |
||||
#define CONFIG_PCI_HOST PCI_HOST_AUTO |
||||
#undef CONFIG_PCI_SCAN_SHOW |
||||
|
||||
/*
|
||||
* Video console (graphic: SMI LynxEM, keyboard: i8042) |
||||
*/ |
||||
#define CONFIG_VIDEO |
||||
#define CONFIG_CFB_CONSOLE |
||||
#define CONFIG_VIDEO_SMI_LYNXEM |
||||
#define CONFIG_I8042_KBD |
||||
#define CONFIG_VIDEO_LOGO |
||||
#define CONFIG_CONSOLE_TIME |
||||
#define CONFIG_CONSOLE_EXTRA_INFO |
||||
#define CONFIG_CONSOLE_CURSOR |
||||
#define CFG_CONSOLE_BLINK_COUNT 30000 /* approx. 2 HZ */ |
||||
|
||||
/*
|
||||
* IDE/SCSI globals |
||||
*/ |
||||
#ifndef __ASSEMBLY__ |
||||
extern unsigned int eltec_board; |
||||
extern unsigned int ata_reset_time; |
||||
extern unsigned int scsi_reset_time; |
||||
extern unsigned short scsi_dev_id; |
||||
extern unsigned int scsi_max_scsi_id; |
||||
extern unsigned char scsi_sym53c8xx_ccf; |
||||
#endif |
||||
|
||||
/*
|
||||
* ATAPI Support (experimental) |
||||
*/ |
||||
#define CONFIG_ATAPI |
||||
#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ |
||||
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ |
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_60X_PCI_IO_OFFSET /* base address */ |
||||
#define CFG_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offste */ |
||||
#define CFG_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */ |
||||
#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ |
||||
#define CFG_ATA_REG_OFFSET 0 /* reg offset */ |
||||
#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ |
||||
|
||||
#define ATA_RESET_TIME (ata_reset_time) |
||||
|
||||
#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ |
||||
#undef CONFIG_IDE_LED /* no led for ide supported */ |
||||
|
||||
/*
|
||||
* SCSI support (experimental) only SYM53C8xx supported |
||||
*/ |
||||
#define CONFIG_SCSI_SYM53C8XX |
||||
#define CONFIG_SCSI_DEV_ID (scsi_dev_id) /* 875 or 860 */ |
||||
#define CFG_SCSI_SYM53C8XX_CCF (scsi_sym53c8xx_ccf) /* value for none 40 mhz clocks */ |
||||
#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ |
||||
#define CFG_SCSI_MAX_SCSI_ID (scsi_max_scsi_id) /* max SCSI ID (0-6) */ |
||||
#define CFG_SCSI_MAX_DEVICE (15 * CFG_SCSI_MAX_LUN) /* max. Target devices */ |
||||
#define CFG_SCSI_SPIN_UP_TIME (scsi_reset_time) |
||||
|
||||
/*
|
||||
* Partion suppport |
||||
*/ |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_ISO_PARTITION |
||||
|
||||
/*
|
||||
* Winbond Configuration |
||||
*/ |
||||
#define CFG_WINBOND_83C553 1 /* has a winbond bridge */ |
||||
#define CFG_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */ |
||||
#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */ |
||||
#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */ |
||||
|
||||
/*
|
||||
* NS87308 Configuration |
||||
*/ |
||||
#define CFG_NS87308 /* Nat Semi super-io cntr on ISA bus */ |
||||
#define CFG_NS87308_BADDR_10 1 |
||||
#define CFG_NS87308_DEVS (CFG_NS87308_UART1 | \ |
||||
CFG_NS87308_UART2 | \
|
||||
CFG_NS87308_KBC1 | \
|
||||
CFG_NS87308_MOUSE | \
|
||||
CFG_NS87308_FDC | \
|
||||
CFG_NS87308_RARP | \
|
||||
CFG_NS87308_GPIO | \
|
||||
CFG_NS87308_POWRMAN | \
|
||||
CFG_NS87308_RTC_APC ) |
||||
|
||||
#define CFG_NS87308_PS2MOD |
||||
#define CFG_NS87308_GPIO_BASE 0x0220 |
||||
#define CFG_NS87308_PWMAN_BASE 0x0460 |
||||
#define CFG_NS87308_PMC2 0x00 /* SuperI/O clock source is 24MHz via X1 */ |
||||
|
||||
/*
|
||||
* set up the NVRAM access registers |
||||
* NVRAM's controlled by the configurable CS line from the 87308 |
||||
*/ |
||||
#define CFG_NS87308_CS0_BASE 0x0076 |
||||
#define CFG_NS87308_CS0_CONF 0x40 |
||||
#define CFG_NS87308_CS1_BASE 0x0070 |
||||
#define CFG_NS87308_CS1_CONF 0x1C |
||||
#define CFG_NS87308_CS2_BASE 0x0071 |
||||
#define CFG_NS87308_CS2_CONF 0x1C |
||||
|
||||
#define CONFIG_RTC_MK48T59 |
||||
|
||||
/*
|
||||
* Initial BATs |
||||
*/ |
||||
#if 1 |
||||
|
||||
#define CFG_IBAT0L 0 |
||||
#define CFG_IBAT0U 0 |
||||
#define CFG_DBAT0L CFG_IBAT1L |
||||
#define CFG_DBAT0U CFG_IBAT1U |
||||
|
||||
#define CFG_IBAT1L 0 |
||||
#define CFG_IBAT1U 0 |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
|
||||
#define CFG_IBAT2L 0 |
||||
#define CFG_IBAT2U 0 |
||||
#define CFG_DBAT2L CFG_IBAT2L |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
|
||||
#define CFG_IBAT3L 0 |
||||
#define CFG_IBAT3U 0 |
||||
#define CFG_DBAT3L CFG_IBAT3L |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
|
||||
#else |
||||
|
||||
/* SDRAM */ |
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW) |
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT0L CFG_IBAT1L |
||||
#define CFG_DBAT0U CFG_IBAT1U |
||||
|
||||
/* address range for flashes */ |
||||
#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
|
||||
/* ISA IO space */ |
||||
#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT2L CFG_IBAT2L |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
|
||||
/* ISA memory space */ |
||||
#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT3L CFG_IBAT3L |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* Speed settings are board specific |
||||
*/ |
||||
#ifndef __ASSEMBLY__ |
||||
extern unsigned long bab7xx_get_bus_freq (void); |
||||
extern unsigned long bab7xx_get_gclk_freq (void); |
||||
#endif |
||||
#define CFG_BUS_HZ bab7xx_get_bus_freq() |
||||
#define CFG_BUS_CLK CFG_BUS_HZ |
||||
#define CFG_CPU_CLK bab7xx_get_gclk_freq() |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* L2 Cache Configuration is board specific for BAB740/BAB750 |
||||
* Init values read from revision srom. |
||||
*/ |
||||
#undef CFG_L2 |
||||
#define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ |
||||
L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) |
||||
#define L2_ENABLE (L2_INIT | L2CR_L2E) |
||||
|
||||
#define CFG_L2_BAB7xx |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
#define CONFIG_NET_MULTI /* Multi ethernet cards support */ |
||||
#define CONFIG_TULIP |
||||
#define CONFIG_TULIP_SELECT_MEDIA |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,338 @@ |
||||
/*
|
||||
* (C) Copyright 2002 ELTEC Elektronik AG |
||||
* Frank Gottschling <fgottschling@eltec.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <asm/processor.h> |
||||
|
||||
#undef DEBUG |
||||
#define GTREGREAD(x) 0xffffffff /* needed for debug */ |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
/* these hardware addresses are pretty bogus, please change them to
|
||||
suit your needs */ |
||||
|
||||
/* first ethernet */ |
||||
#define CONFIG_ETHADDR 00:00:5b:ee:de:ad |
||||
|
||||
#define CONFIG_IPADDR 192.168.0.105 |
||||
#define CONFIG_SERVERIP 192.168.0.100 |
||||
|
||||
#define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */ |
||||
|
||||
#define CONFIG_BAUDRATE 9600 /* console baudrate */ |
||||
|
||||
#undef CONFIG_WATCHDOG |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp 1000000; " \
|
||||
"setenv bootargs root=ramfs console=ttyS00,9600 " \
|
||||
"ip=$(ipaddr):$(serverip):$(rootpath):$(gatewayip):" \
|
||||
"$(netmask):$(hostname):eth0:none; " \
|
||||
"bootm" |
||||
|
||||
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
/*
|
||||
* choose between COM1 and COM2 as serial console |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x1000000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* dec. freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
#define CFG_BOARD_ASM_INIT |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/*
|
||||
* Address mapping scheme for the MPC107 mem controller is mapping B (CHRP) |
||||
*/ |
||||
#undef CFG_ADDRESS_MAP_A |
||||
|
||||
#define CFG_PCI_MEMORY_BUS 0x00000000 |
||||
#define CFG_PCI_MEMORY_PHYS 0x00000000 |
||||
#define CFG_PCI_MEMORY_SIZE 0x40000000 |
||||
|
||||
#define CFG_PCI_MEM_BUS 0x80000000 |
||||
#define CFG_PCI_MEM_PHYS 0x80000000 |
||||
#define CFG_PCI_MEM_SIZE 0x7d000000 |
||||
|
||||
#define CFG_ISA_MEM_BUS 0x00000000 |
||||
#define CFG_ISA_MEM_PHYS 0xfd000000 |
||||
#define CFG_ISA_MEM_SIZE 0x01000000 |
||||
|
||||
#define CFG_PCI_IO_BUS 0x00800000 |
||||
#define CFG_PCI_IO_PHYS 0xfe800000 |
||||
#define CFG_PCI_IO_SIZE 0x00400000 |
||||
|
||||
#define CFG_ISA_IO_BUS 0x00000000 |
||||
#define CFG_ISA_IO_PHYS 0xfe000000 |
||||
#define CFG_ISA_IO_SIZE 0x00800000 |
||||
|
||||
/* driver defines FDC,IDE,... */ |
||||
#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS |
||||
#define CFG_ISA_IO CFG_ISA_IO_PHYS |
||||
#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS |
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
|
||||
#define CFG_USR_LED_BASE 0x78000000 |
||||
#define CFG_NVRAM_BASE 0xff000000 |
||||
#define CFG_UART_BASE 0xff400000 |
||||
#define CFG_FLASH_BASE 0xfff00000 |
||||
|
||||
#define MPC107_EUMB_ADDR 0xfce00000 |
||||
#define MPC107_EUMB_PI 0xfce41090 |
||||
#define MPC107_EUMB_GCR 0xfce41020 |
||||
#define MPC107_EUMB_IACKR 0xfce600a0 |
||||
#define MPC107_I2C_ADDR 0xfce03000 |
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */ |
||||
#define CFG_INIT_RAM_END 0x4000 |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*
|
||||
* Flash mapping/organization on the MPC10x. |
||||
*/ |
||||
#define FLASH_BASE0_PRELIM 0xff800000 |
||||
#define FLASH_BASE1_PRELIM 0xffc00000 |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ |
||||
#define CFG_JFFS2_NUM_BANKS 2 /* ! second bank contains U-Boot */ |
||||
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */ |
||||
#undef CFG_MEMTEST |
||||
|
||||
/*
|
||||
* Environment settings |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
||||
#define CFG_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */ |
||||
#define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */ |
||||
#define CFG_ENV_ADDR 0x0 |
||||
#define CFG_ENV_MAP_ADRS 0xff000000 |
||||
#define CFG_NV_SROM_COPY_ADDR (CFG_ENV_ADDR + CFG_ENV_SIZE) |
||||
#define CFG_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */ |
||||
#define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */ |
||||
|
||||
/*
|
||||
* Serial devices |
||||
*/ |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK 24000000 |
||||
#define CFG_NS16550_COM1 (CFG_UART_BASE + 0) |
||||
#define CFG_NS16550_COM2 (CFG_UART_BASE + 8) |
||||
|
||||
/*
|
||||
* PCI stuff |
||||
*/ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_PNP /* pci plug-and-play */ |
||||
#define CONFIG_PCI_HOST PCI_HOST_AUTO |
||||
#undef CONFIG_PCI_SCAN_SHOW |
||||
|
||||
/*
|
||||
* Optional Video console (graphic: SMI LynxEM) |
||||
*/ |
||||
#define CONFIG_VIDEO |
||||
#define CONFIG_CFB_CONSOLE |
||||
#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10)) |
||||
#define VIDEO_TSTC_FCT serial_tstc |
||||
#define VIDEO_GETC_FCT serial_getc |
||||
|
||||
#define CONFIG_VIDEO_SMI_LYNXEM |
||||
#define CONFIG_VIDEO_LOGO |
||||
#define CONFIG_CONSOLE_EXTRA_INFO |
||||
|
||||
/*
|
||||
* Initial BATs |
||||
*/ |
||||
#if 1 |
||||
|
||||
#define CFG_IBAT0L 0 |
||||
#define CFG_IBAT0U 0 |
||||
#define CFG_DBAT0L CFG_IBAT1L |
||||
#define CFG_DBAT0U CFG_IBAT1U |
||||
|
||||
#define CFG_IBAT1L 0 |
||||
#define CFG_IBAT1U 0 |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
|
||||
#define CFG_IBAT2L 0 |
||||
#define CFG_IBAT2U 0 |
||||
#define CFG_DBAT2L CFG_IBAT2L |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
|
||||
#define CFG_IBAT3L 0 |
||||
#define CFG_IBAT3U 0 |
||||
#define CFG_DBAT3L CFG_IBAT3L |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
|
||||
#else |
||||
|
||||
/* SDRAM */ |
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW) |
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT0L CFG_IBAT1L |
||||
#define CFG_DBAT0U CFG_IBAT1U |
||||
|
||||
/* address range for flashes */ |
||||
#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
|
||||
/* ISA IO space */ |
||||
#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT2L CFG_IBAT2L |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
|
||||
/* ISA memory space */ |
||||
#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT3L CFG_IBAT3L |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* Speed settings are board specific |
||||
*/ |
||||
#define CFG_BUS_HZ 100000000 |
||||
#define CFG_CPU_CLK 400000000 |
||||
#define CFG_BUS_CLK CFG_BUS_HZ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* L2CR setup -- make sure this is right for your board! |
||||
* look in include/mpc74xx.h for the defines used here |
||||
*/ |
||||
|
||||
#define CFG_L2 |
||||
|
||||
#if 1 |
||||
#define L2_INIT 0 /* cpu 750 CXe*/ |
||||
#else |
||||
#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ |
||||
L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) |
||||
#endif |
||||
#define L2_ENABLE (L2_INIT | L2CR_L2E) |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#define CONFIG_NET_MULTI /* Multi ethernet cards support */ |
||||
#define CONFIG_EEPRO100 |
||||
#define CONFIG_EEPRO100_SROM_WRITE |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,372 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_405GP 1 /* This is a PPC405 CPU */ |
||||
#define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
||||
#define CONFIG_ERIC 1 /* ...on a ERIC board */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* run board_pre_init() */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
||||
|
||||
#if 1 |
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
||||
#endif |
||||
#if 0 |
||||
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
||||
#endif |
||||
#if 0 |
||||
#define CFG_ENV_IS_IN_EEPROM 1 /* use I2C RTC X1240 for environment vars */ |
||||
#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
||||
#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */ |
||||
#endif /* total size of a X1240 is 2048 bytes */ |
||||
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x57 /* X1240 has two I2C slave addresses, one for EEPROM */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* address length for the eeprom */ |
||||
#define CONFIG_I2C_RTC 1 /* we have a Xicor X1240 RTC */ |
||||
#define CFG_I2C_RTC_ADDR 0x6F /* and one for RTC */ |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
#undef CFG_ENV_IS_IN_NVRAM |
||||
#undef CFG_ENV_IS_IN_EEPROM |
||||
#else |
||||
#ifdef CFG_ENV_IS_IN_NVRAM |
||||
#undef CFG_ENV_IS_IN_FLASH |
||||
#undef CFG_ENV_IS_IN_EEPROM |
||||
#else |
||||
#ifdef CFG_ENV_IS_IN_EEPROM |
||||
#undef CFG_ENV_IS_IN_NVRAM |
||||
#undef CFG_ENV_IS_IN_FLASH |
||||
#endif |
||||
#endif |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
||||
|
||||
#if 1 |
||||
#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ |
||||
#else |
||||
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs " \ |
||||
"nfsroot=192.168.1.2:/eric_root_devel " \
|
||||
"ip=192.168.1.22:192.168.1.2" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 1 /* PHY address */ |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_ENV | \
|
||||
CFG_CMD_FLASH) |
||||
|
||||
/*
|
||||
* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | \
|
||||
* CFG_CMD_KGDB | CFG_CMD_I2C | CFG_CMD_EEPROM | \
|
||||
* CFG_CMD_ENV | CFG_CMD_FLASH) |
||||
*/ |
||||
|
||||
/* CFG_CMD_ENV est definie */ |
||||
/* ((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_KGDB) & ~(CFG_CMD_ENV))
|
||||
*/ |
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#undef CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_EXT_SERIAL_CLOCK 14318180 |
||||
|
||||
/* The following table includes the supported baudrates */ |
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
|
||||
57600, 115200, 230400, 460800, 921600 } |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */ |
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
||||
|
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
||||
#undef CONFIG_PCI_PNP /* no pci plug-and-play */ |
||||
/* resource configuration */ |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1743 /* PCI Vendor ID: Peppercon AG */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: 405GP */ |
||||
#define CFG_PCI_PTM1LA 0xFFFC0000 /* point to flash */ |
||||
#define CFG_PCI_PTM1MS 0xFFFFF001 /* 4kB, enable hard-wired to 1 */ |
||||
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
||||
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External peripheral base address |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* Bank 0 - Flash/SRAM 0xFF000000 16MB 16 Bit */ |
||||
/* Bank 1 - NVRAM/RTC 0xF0000000 1MB 8 Bit */ |
||||
/* Bank 2 - A/D converter 0xF0100000 1MB 8 Bit */ |
||||
/* Bank 3 - Ethernet PHY Reset 0xF0200000 1MB 8 Bit */ |
||||
/* Bank 4 - PC-MIP PRSNT1# 0xF0300000 1MB 8 Bit */ |
||||
/* Bank 5 - PC-MIP PRSNT2# 0xF0400000 1MB 8 Bit */ |
||||
/* Bank 6 - CPU LED0 0xF0500000 1MB 8 Bit */ |
||||
/* Bank 7 - CPU LED1 0xF0600000 1MB 8 Bit */ |
||||
|
||||
/* ----------------------------------------------------------------------- */ |
||||
/* Memory Bank 0 (Flash) initialization */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
#define CS0_AP 0x9B015480 |
||||
#define CS0_CR 0xFF87A000 /* BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
/* Memory Bank 1 (NVRAM/RTC) initialization */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
#define CS1_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ |
||||
#define CS1_CR 0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
/* Memory Bank 2 (A/D converter) initialization */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
#define CS2_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ |
||||
#define CS2_CR 0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
/* Memory Bank 3 (Ethernet PHY Reset) initialization */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
#define CS3_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ |
||||
#define CS3_CR 0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
#define CS4_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ |
||||
#define CS4_CR 0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
#define CS5_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ |
||||
#define CS5_CR 0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
/* Memory Bank 6 (CPU LED0) initialization */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
#define CS6_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ |
||||
#define CS6_CR 0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
/* Memory Bank 7 (CPU LED1) initialization */ |
||||
/* ----------------------------------------------------------------------- */ |
||||
#define CS7_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ |
||||
#define CS7_CR 0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ |
||||
|
||||
#define CFG_NVRAM_REG_BASE_ADDR 0xF0000000 |
||||
#define CFG_RTC_REG_BASE_ADDR (0xF0000000 + 0x7F8) |
||||
#define CFG_ADC_REG_BASE_ADDR 0xF0100000 |
||||
#define CFG_PHYRES_REG_BASE_ADDR 0xF0200000 |
||||
#define CFG_PRSNT1_REG_BASE_ADDR 0xF0300000 |
||||
#define CFG_PRSNT2_REG_BASE_ADDR 0xF0400000 |
||||
#define CFG_LED0_REG_BASE_ADDR 0xF0500000 |
||||
#define CFG_LED1_REG_BASE_ADDR 0xF0600000 |
||||
|
||||
|
||||
/* SDRAM CONFIG */ |
||||
#define CFG_SDRAM_MANUALLY 1 |
||||
#define CFG_SDRAM_SINGLE_BANK 1 |
||||
|
||||
#ifdef CFG_SDRAM_MANUALLY |
||||
/*-----------------------------------------------------------------------
|
||||
* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) |
||||
*----------------------------------------------------------------------*/ |
||||
#define MB0CF 0x00062001 /* 32MB @ 0 */ |
||||
/*-----------------------------------------------------------------------
|
||||
* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) |
||||
*----------------------------------------------------------------------*/ |
||||
#ifdef CFG_SDRAM_SINGLE_BANK |
||||
#define MB1CF 0x0 /* 0MB @ 32MB */ |
||||
#else |
||||
#define MB1CF 0x02062001 /* 32MB @ 32MB */ |
||||
#endif |
||||
/*-----------------------------------------------------------------------
|
||||
* Set MB2CF for bank 2. off |
||||
*----------------------------------------------------------------------*/ |
||||
#define MB2CF 0x0 /* 0MB */ |
||||
/*-----------------------------------------------------------------------
|
||||
* Set MB3CF for bank 3. off |
||||
*----------------------------------------------------------------------*/ |
||||
#define MB3CF 0x0 /* 0MB */ |
||||
|
||||
#define SDTR_100 0x0086400D |
||||
#define RTR_100 0x05F0 |
||||
#define SDTR_66 0x00854006 /* orig U-Boot-wallnut says 0x00854006 */ |
||||
#define RTR_66 0x03f8 |
||||
|
||||
#endif /* CFG_SDRAM_MANUALLY */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_SDRAM_SIZE 32 |
||||
#define CFG_FLASH_BASE 0xFF800000 /* 8 MByte Flash */ |
||||
#define CFG_MONITOR_BASE 0xFFFE0000 /* last 128kByte within Flash */ |
||||
/*#define CFG_MONITOR_LEN (192 * 1024)*/ /* Reserve 196 kB for Monitor */ |
||||
#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ |
||||
#define CFG_FLASH_16BIT 1 /* Rom 16 bit data bus */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/* BEG ENVIRONNEMENT FLASH */ |
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_SECT_SIZE (128*1024) |
||||
|
||||
#if 0 /* force ENV to be NOT embedded */
|
||||
#define CFG_ENV_ADDR 0xfffa0000 |
||||
#else /* force ENV to be embedded */ |
||||
#define CFG_ENV_SIZE (2 * 1024) /* Total Size of Environment Sector 2k */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN - CFG_ENV_SIZE - 0x10) /* let space for reset vector */ |
||||
/* #define CFG_ENV_ADDR (CFG_MONITOR_BASE)*/ |
||||
#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) |
||||
#endif |
||||
|
||||
#endif |
||||
/* END ENVIRONNEMENT FLASH */ |
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM organization |
||||
*/ |
||||
#define CFG_NVRAM_BASE_ADDR CFG_NVRAM_REG_BASE_ADDR /* NVRAM base address */ |
||||
#define CFG_NVRAM_SIZE 0x7F8 /* NVRAM size 2kByte - 8 Byte for RTC */ |
||||
|
||||
#ifdef CFG_ENV_IS_IN_NVRAM |
||||
#define CFG_ENV_SIZE 0x7F8 /* Size of Environment vars */ |
||||
#define CFG_ENV_ADDR \ |
||||
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ |
||||
#endif |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */ |
||||
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ |
||||
|
||||
|
||||
/* Configuration Port location */ |
||||
/* #define CONFIG_PORT_ADDR 0xF0000500 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ |
||||
#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for Serial Presence Detect EEPROM address |
||||
* (to get SDRAM settings) |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x50 |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,356 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ |
||||
#define CONFIG_ETX094 1 /* ...on a ETX_094 board */ |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 57600 |
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */ |
||||
|
||||
#define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */ |
||||
#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */ |
||||
#define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */ |
||||
|
||||
#define CONFIG_ETHADDR 08:00:06:00:00:00 |
||||
|
||||
#ifdef CONFIG_ETHADDR |
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 /* default MAC can be overwritten once */ |
||||
#endif |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \
|
||||
"U-Boot_version=U-Boot-1.0.x-Date " \
|
||||
"panic=1 " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm" |
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(nfsip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm" |
||||
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#define CONFIG_WATCHDOG 1 /* watchdog enabled */ |
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x40000000 |
||||
#ifdef DEBUG |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#endif |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#ifdef CONFIG_FLASH_16BIT |
||||
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ |
||||
#else |
||||
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block |
||||
*/ |
||||
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
||||
#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
||||
#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit - leave PLL multiplication factor unchanged ! |
||||
*/ |
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CFG_SCCR (SCCR_TBS | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CFG_DER 0x2002000F*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | \ |
||||
OR_SCY_2_CLK | OR_TRLX ) |
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
||||
|
||||
#ifdef CONFIG_FLASH_16BIT /* 16 bit data port */ |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) |
||||
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) |
||||
#else /* 32 bit data port */ |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) |
||||
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) |
||||
#endif /* CONFIG_FLASH_16BIT */ |
||||
|
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP |
||||
#define CFG_OR1_PRELIM CFG_OR0_PRELIM |
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CFG_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) |
||||
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
#define CFG_OR3_PRELIM CFG_OR2_PRELIM |
||||
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTA 23 /* start with divider for 100 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) |
||||
/* 9 column SDRAM */ |
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) |
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,459 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ |
||||
#define CONFIG_IP860 1 /* ...on a IP860 board */ |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#define CONFIG_BAUDRATE 9600 |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \ |
||||
"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 $(filesize)\0" |
||||
|
||||
#define CONFIG_ETHADDR 00:30:bf:01:02:d2 |
||||
#define CONFIG_IPADDR 10.0.0.5 |
||||
#define CONFIG_SERVERIP 10.0.0.2 |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
|
||||
/* enable I2C and select the hardware/software driver */ |
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PB_SCL 0x00000020 /* PB 26 */ |
||||
#define PB_SDA 0x00000010 /* PB 27 */ |
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA |
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
|
||||
|
||||
# define CFG_I2C_SPEED 50000 |
||||
# define CFG_I2C_SLAVE 0xFE |
||||
# define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ |
||||
# define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM) |
||||
|
||||
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT |
||||
|
||||
/*----------------------------------------------------------------------*/ |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*----------------------------------------------------------------------*/ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000 /* default load address */ |
||||
|
||||
#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xF1000000 /* Non-standard value!! */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x10000000 |
||||
#ifdef DEBUG |
||||
#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ |
||||
#else |
||||
#if 0 /* need more space for I2C tests */
|
||||
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
||||
#else |
||||
#define CFG_MONITOR_LEN (256 << 10) |
||||
#endif |
||||
#endif |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#undef CFG_ENV_IS_IN_FLASH |
||||
#undef CFG_ENV_IS_IN_NVRAM |
||||
#undef CFG_ENV_IS_IN_NVRAM |
||||
#undef DEBUG_I2C |
||||
#define CFG_ENV_IS_IN_EEPROM |
||||
|
||||
#ifdef CFG_ENV_IS_IN_NVRAM |
||||
#define CFG_ENV_ADDR 0x20000000 /* use SRAM */ |
||||
#define CFG_ENV_SIZE (16<<10) /* use 16 kB */ |
||||
#endif /* CFG_ENV_IS_IN_NVRAM */ |
||||
|
||||
#ifdef CFG_ENV_IS_IN_EEPROM |
||||
#define CFG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */ |
||||
#define CFG_ENV_SIZE 1536 /* Use remaining space */ |
||||
#endif /* CFG_ENV_IS_IN_EEPROM */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
* +0x0004 |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* +0x0000 => 0x80600800 |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_EARB | SIUMCR_EARP0 | \ |
||||
SIUMCR_DBGC11 | SIUMCR_MLRC10) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Clock Setting - the IP860 has no 32kHz clock, so automatic detection fails |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_8xx_GCLK_FREQ 50000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
* +0x0200 => 0x00C2 |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
* +0x0240 => 0x0082 |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit, set PLL multiplication factor ! |
||||
*/ |
||||
/* +0x0286 => was: 0x0000D000 */ |
||||
#define CFG_PLPRCR \ |
||||
( PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
|
||||
/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
|
||||
PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
|
||||
) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \ |
||||
SCCR_RTDIV | SCCR_RTSEL | \
|
||||
/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
|
||||
SCCR_EBDF00 | SCCR_DFSYNC00 | \
|
||||
SCCR_DFBRG00 | SCCR_DFNL000 | \
|
||||
SCCR_DFNH000) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* +0x0220 => 0x00C3 */ |
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration Register 19-4 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* +0x09C4 => TIMEP=1 */ |
||||
#define CFG_RCCR 0x0100 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMDS - RISC Microcode Development Support Control Register |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RMDS 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DER - Debug Event Register |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CFG_DER 0x2002000F*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
*/ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM - 16-14 |
||||
* => 0xC3804114 |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTA 0xC3 |
||||
|
||||
#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/*
|
||||
* BR1 and OR1 (FLASH) |
||||
*/ |
||||
#define FLASH_BASE 0x10000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
/* allow for max 8 MB of Flash */ |
||||
#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ |
||||
|
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK) |
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
||||
/* 16 bit, bank valid */ |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V ) |
||||
|
||||
#define CFG_OR1_PRELIM CFG_OR0_PRELIM |
||||
#define CFG_BR1_PRELIM CFG_BR0_PRELIM |
||||
|
||||
/*
|
||||
* BR2/OR2 - SDRAM |
||||
*/ |
||||
#define SDRAM_BASE 0x00000000 /* SDRAM bank */ |
||||
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ |
||||
#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */ |
||||
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ |
||||
|
||||
#define CFG_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) |
||||
#define CFG_BR2 ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
/*
|
||||
* BR3/OR3 - SRAM (16 bit) |
||||
*/ |
||||
#define SRAM_BASE 0x20000000 |
||||
#define CFG_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */ |
||||
#define CFG_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) |
||||
#define SRAM_SIZE (1 + (~(CFG_OR3 & BR_BA_MSK))) |
||||
#define CFG_OR3_PRELIM CFG_OR3 /* Make sure to map early */ |
||||
#define CFG_BR3_PRELIM CFG_BR3 /* in case it's used for ENV */ |
||||
|
||||
/*
|
||||
* BR4/OR4 - Board Control & Status (8 bit) |
||||
*/ |
||||
#define BCSR_BASE 0xFC000000 |
||||
#define CFG_OR4 0xFFFF0120 /* BI (internal) */ |
||||
#define CFG_BR4 ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) |
||||
|
||||
/*
|
||||
* BR5/OR5 - IP Slot A/B (16 bit) |
||||
*/ |
||||
#define IP_SLOT_BASE 0x40000000 |
||||
#define CFG_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */ |
||||
#define CFG_BR5 ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) |
||||
|
||||
/*
|
||||
* BR6/OR6 - VME STD (16 bit) |
||||
*/ |
||||
#define VME_STD_BASE 0xFE000000 |
||||
#define CFG_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */ |
||||
#define CFG_BR6 ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) |
||||
|
||||
/*
|
||||
* BR7/OR7 - SHORT I/O + RTC + IACK (16 bit) |
||||
*/ |
||||
#define VME_SHORT_BASE 0xFF000000 |
||||
#define CFG_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */ |
||||
#define CFG_BR7 ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Board Control and Status Region: |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#ifndef __ASSEMBLY__ |
||||
typedef struct ip860_bcsr_s { |
||||
unsigned char shmem_addr; /* +00 shared memory address register */ |
||||
unsigned char reserved0; |
||||
unsigned char mbox_addr; /* +02 mailbox address register */ |
||||
unsigned char reserved1; |
||||
unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */ |
||||
unsigned char reserved2; |
||||
unsigned char vme_int_pend; /* +06 VME interrupt pending register */ |
||||
unsigned char reserved3; |
||||
unsigned char bd_int_mask; /* +08 board interrupt mask register */ |
||||
unsigned char reserved4; |
||||
unsigned char bd_int_pend; /* +0A board interrupt pending register */ |
||||
unsigned char reserved5; |
||||
unsigned char bd_ctrl; /* +0C board control register */ |
||||
unsigned char reserved6; |
||||
unsigned char bd_status; /* +0E board status register */ |
||||
unsigned char reserved7; |
||||
unsigned char vme_irq; /* +10 VME interrupt request register */ |
||||
unsigned char reserved8; |
||||
unsigned char vme_ivec; /* +12 VME interrupt vector register */ |
||||
unsigned char reserved9; |
||||
unsigned char cli_mbox; /* +14 clear mailbox irq */ |
||||
unsigned char reservedA; |
||||
unsigned char rtc; /* +16 RTC control register */ |
||||
unsigned char reservedB; |
||||
unsigned char mbox_data; /* +18 mailbox read/write register */ |
||||
unsigned char reservedC; |
||||
unsigned char wd_trigger; /* +1A Watchdog trigger register */ |
||||
unsigned char reservedD; |
||||
unsigned char rmw_req; /* +1C RMW request register */ |
||||
} ip860_bcsr_t; |
||||
#endif /* __ASSEMBLY__ */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Board Control Register: bd_ctrl (Offset 0x0C) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */ |
||||
#define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */ |
||||
#define BD_CTRL_FLWE 0x20 /* Flash Write Enable */ |
||||
#define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,354 @@ |
||||
/*
|
||||
* (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de> |
||||
* |
||||
* This file is based on similar values for other boards found in |
||||
* other U-Boot config files, mainly tqm8260.h and mpc8260ads.h. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#undef DEBUG /* General debug */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ |
||||
#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* select serial console configuration |
||||
* |
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
* |
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must |
||||
* defined elsewhere (for example, on the cogent platform, there are serial |
||||
* ports on the motherboard which are used for the serial console - see |
||||
* cogent/cma101/serial.[ch]). |
||||
*/ |
||||
#define CONFIG_CONS_ON_SMC /* define if console on SMC */ |
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ |
||||
#undef CONFIG_CONS_NONE /* define if console on something else */ |
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* select ethernet configuration |
||||
* |
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
||||
* for FCC) |
||||
* |
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
||||
* from CONFIG_COMMANDS to remove support for networking. |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
||||
#define CONFIG_ETHER_INDEX 3 /* which channel for ether */ |
||||
|
||||
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* - Rx-CLK is CLK14 |
||||
* - Tx-CLK is CLK16 |
||||
* - Select bus for bd/buffers (see 28-13) |
||||
* - Half duplex |
||||
*/ |
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) |
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16) |
||||
# define CFG_CPMFCR_RAMTYPE 0 |
||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ |
||||
|
||||
/* other options */ |
||||
|
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
||||
#define CONFIG_BAUDRATE 19200 |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
/*
|
||||
* select i2c support configuration |
||||
* |
||||
* Supported configurations are {none, software, hardware} drivers. |
||||
* If the software driver is chosen, there are some additional |
||||
* configuration items that the driver uses to drive the port pins. |
||||
*/ |
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#ifdef CONFIG_SOFT_I2C |
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ |
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000) |
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000) |
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0) |
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ |
||||
else iop->pdat &= ~0x00010000 |
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ |
||||
else iop->pdat &= ~0x00020000 |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
#endif /* CONFIG_SOFT_I2C */ |
||||
|
||||
#define CONFIG_COMMANDS CONFIG_CMD_DFL |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */ |
||||
#define CONFIG_BOOTARGS "root=/dev/ram rw" |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
||||
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ |
||||
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ |
||||
#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ |
||||
#endif |
||||
|
||||
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */ |
||||
/* for versions < 2.4.5-pre5 */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CFG_RESET_ADDRESS 0x04400000 |
||||
|
||||
#define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration (Setup by the |
||||
* startup code). Please note that CFG_SDRAM_BASE _must_ start at 0. |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFF800000 |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */ |
||||
#define CFG_MAX_FLASH_SIZE (CFG_MAX_FLASH_SECT * 0x10000) /* 4 MB */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
/* Environment in FLASH, there is little space left in Serial EEPROM */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x10000) /* 2. sector */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words |
||||
* |
||||
* if you change bits in the HRCW, you must also change the CFG_* |
||||
* defines for the various registers affected by the HRCW e.g. changing |
||||
* HRCW_DPPCxx requires you to also change CFG_SIUMCR. |
||||
*/ |
||||
#define CFG_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\ |
||||
( HRCW_L2CPC10 | HRCW_ISB110 ) |\
|
||||
( HRCW_MMR11 | HRCW_APPC10 ) |\
|
||||
( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
|
||||
) /* 0x14863245 */ |
||||
|
||||
/* no slaves */ |
||||
#define CFG_HRCW_SLAVE1 0 |
||||
#define CFG_HRCW_SLAVE2 0 |
||||
#define CFG_HRCW_SLAVE3 0 |
||||
#define CFG_HRCW_SLAVE4 0 |
||||
#define CFG_HRCW_SLAVE5 0 |
||||
#define CFG_HRCW_SLAVE6 0 |
||||
#define CFG_HRCW_SLAVE7 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFF000000 /* We keep original value */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11 |
||||
*----------------------------------------------------------------------- |
||||
* HID0 also contains cache control. |
||||
* |
||||
* HID1 has only read-only information - nothing to set. |
||||
*/ |
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
||||
HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID2 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5 |
||||
*----------------------------------------------------------------------- |
||||
* turn on Checkstop Reset Enable |
||||
*/ |
||||
#define CFG_RMR RMR_CSRE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_BCR 0xA01C0000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_SIUMCR 0X4205C000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable |
||||
*/ |
||||
#if defined (CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP) |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40 |
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, |
||||
* and enable Time Counter |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable |
||||
* Periodic timer |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8 |
||||
*----------------------------------------------------------------------- |
||||
* Ensure DFBRG is Divide by 16 |
||||
*/ |
||||
#define CFG_SCCR 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RCCR 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Init Memory Controller: |
||||
* |
||||
* Bank Bus Machine PortSz Device |
||||
* ---- --- ------- ------ ------ |
||||
* 0 60x GPCM 64 bit FLASH |
||||
* 1 60x SDRAM 64 bit SDRAM |
||||
*/ |
||||
|
||||
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) | 0x0801) |
||||
#define CFG_OR0_PRELIM 0xFF800882 |
||||
#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) | 0x0041) |
||||
#define CFG_OR1_PRELIM 0xF8002CD0 |
||||
|
||||
#define CFG_PSDMR 0x404A241A |
||||
#define CFG_MPTPR 0x00007400 |
||||
#define CFG_PSRT 0x00000007 |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,307 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* Configuation settings for the MBX8xx board. |
||||
* |
||||
* ----------------------------------------------------------------- |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
/*
|
||||
* Changed 2002-10-01 |
||||
* Added PCMCIA defines mostly taken from other U-Boot boards that |
||||
* have PCMCIA already working. If you find any bugs, incorrect assumptions |
||||
* feel free to fix them yourself and submit a patch. |
||||
* Rod Boyce <rod_boyce@stratexnet.com. |
||||
*/ |
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ |
||||
#define CONFIG_MBX 1 /* ...on an MBX module */ |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 9600 |
||||
/* Define this to use the PCI bus */ |
||||
#undef CONFIG_USE_PCI |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
#define CONFIG_8xx_GCLK_FREQ (50000000UL) |
||||
#if 1 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
#define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */ |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ |
||||
"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
|
||||
"nfsaddrs=10.0.0.99:10.0.0.2" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_COMMANDS ( CFG_CMD_NET | CONFIG_CMD_DFL | CFG_CMD_SDRAM | \ |
||||
CFG_CMD_PCMCIA | CFG_CMD_IDE ) |
||||
|
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#undef CFG_HUSH_PARSER /* Hush parse for U-Boot */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical memory map as defined by the MBX PGM |
||||
*/ |
||||
#define CFG_IMMR 0xFA200000 /* Internal Memory Mapped Register*/ |
||||
#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */ |
||||
#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ |
||||
#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */ |
||||
#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ |
||||
#define CFG_PCIMEM_OR 0xA0000108 |
||||
#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ |
||||
#define CFG_PCIBRIDGE_OR 0xFFFF0108 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ |
||||
#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE) |
||||
#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Offset in DPMEM where we keep the VPD data |
||||
*/ |
||||
#define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xfe000000 |
||||
#ifdef DEBUG |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#endif |
||||
#undef CFG_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */ |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM Configuration |
||||
* |
||||
* Note: the MBX is special because there is already a firmware on this |
||||
* board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we |
||||
* access the NVRAM at the offset 0x1000. |
||||
*/ |
||||
#define CFG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ |
||||
#define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000) |
||||
#define CFG_ENV_SIZE 0x1000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
/* #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit - leave PLL multiplication factor unchanged ! |
||||
*/ |
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) |
||||
#define CFG_SCCR SCCR_TBS |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6 |
||||
|
||||
#define CONFIG_PCMCIA_SLOT_A 1 |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Debug Entry Mode |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,371 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de |
||||
* |
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* Configuation settings for the miniHiPerCam. |
||||
* |
||||
* ----------------------------------------------------------------- |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ |
||||
#define CONFIG_MHPC 1 /* on a miniHiPerCam */ |
||||
#define CONFIG_BOARD_PRE_INIT 1 /* do special hardware init. */ |
||||
#define CONFIG_MISC_INIT_R 1 |
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED |
||||
#undef CONFIG_8xx_CONS_SMC1 |
||||
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 9600 |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
#define CONFIG_ETHADDR 00:00:5b:ee:de:ad |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp;" \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
|
||||
"bootm" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
#undef CONFIG_UCODE_PATCH |
||||
|
||||
/* enable I2C and select the hardware/software driver */ |
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PB_SCL 0x00000020 /* PB 26 */ |
||||
#define PB_SDA 0x00000010 /* PB 27 */ |
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA |
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
|
||||
#define CFG_I2C_SPEED 50000 |
||||
#define CFG_I2C_SLAVE 0xFE |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
|
||||
#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE) |
||||
#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */ |
||||
#define LCD_VIDEO_COLS 640 |
||||
#define LCD_VIDEO_ROWS 480 |
||||
#define LCD_VIDEO_FG 255 |
||||
#define LCD_VIDEO_BG 0 |
||||
|
||||
#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */ |
||||
#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */ |
||||
#define CONFIG_VIDEO_LOGO |
||||
|
||||
#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */ |
||||
#define VIDEO_TSTC_FCT serial_tstc |
||||
#define VIDEO_GETC_FCT serial_getc |
||||
|
||||
#define CONFIG_BR0_WORKAROUND 1 |
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_REGINFO ) |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x300000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical memory map |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xfe000000 |
||||
|
||||
#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ |
||||
#undef CFG_MONITOR_BASE /* to run U-Boot from RAM */ |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ |
||||
#define CFG_JFFS2_NUM_BANKS 1 /* one flash only */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET CFG_MONITOR_LEN /* Offset of Environment */ |
||||
#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_SEME) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 12-18 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit - leave PLL multiplication factor unchanged ! |
||||
*/ |
||||
#define MPC8XX_SPEED 50000000L |
||||
#define MPC8XX_XIN 5000000L /* ref clk */ |
||||
#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) |
||||
#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ |
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
|
||||
#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */ |
||||
#define CFG_SCCR (SCCR_TBS | SCCR_DFLCD001) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* MAMR settings for SDRAM - 16-14 |
||||
* => 0xC080200F |
||||
*----------------------------------------------------------------------- |
||||
* periodic timer for refresh |
||||
*/ |
||||
#define CFG_MAMR_PTA 0xC0 |
||||
#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK) |
||||
|
||||
/*
|
||||
* BR0 and OR0 (FLASH) used to re-map FLASH |
||||
*/ |
||||
|
||||
/* allow for max 8 MB of Flash */ |
||||
#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/ |
||||
#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/ |
||||
#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ |
||||
|
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/ |
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V ) |
||||
|
||||
/*
|
||||
* BR1 and OR1 (SDRAM) |
||||
*/ |
||||
#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ |
||||
#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */ |
||||
|
||||
/* SDRAM timing: drive GPL5 high on first cycle */ |
||||
#define CFG_OR_TIMING_SDRAM (OR_G5LS) |
||||
|
||||
#define CFG_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CFG_OR_TIMING_SDRAM ) |
||||
#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
/*
|
||||
* BR2/OR2 - DIMM |
||||
*/ |
||||
#define CFG_OR2 (OR_ACS_DIV4) |
||||
#define CFG_BR2 (BR_MS_UPMA) |
||||
|
||||
/*
|
||||
* BR3/OR3 - DIMM |
||||
*/ |
||||
#define CFG_OR3 (OR_ACS_DIV4) |
||||
#define CFG_BR3 (BR_MS_UPMA) |
||||
|
||||
/*
|
||||
* BR4/OR4 |
||||
*/ |
||||
#define CFG_OR4 0 |
||||
#define CFG_BR4 0 |
||||
|
||||
/*
|
||||
* BR5/OR5 |
||||
*/ |
||||
#define CFG_OR5 0 |
||||
#define CFG_BR5 0 |
||||
|
||||
/*
|
||||
* BR6/OR6 |
||||
*/ |
||||
#define CFG_OR6 0 |
||||
#define CFG_BR6 0 |
||||
|
||||
/*
|
||||
* BR7/OR7 |
||||
*/ |
||||
#define CFG_OR7 0 |
||||
#define CFG_BR7 0 |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Debug Entry Mode |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,267 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Stuart Hughes <stuarth@lineo.com> |
||||
* This file is based on similar values for other boards found in other |
||||
* U-Boot config files, and some that I found in the mpc8260ads manual. |
||||
* |
||||
* Note: my board is a PILOT rev. |
||||
* Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Config header file for a MPC8260ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ |
||||
#define CONFIG_MPC8260ADS 1 /* ...on motorola ads board */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
||||
|
||||
/* allow serial and ethaddr to be overwritten */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
* |
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
* |
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must |
||||
* defined elsewhere (for example, on the cogent platform, there are serial |
||||
* ports on the motherboard which are used for the serial console - see |
||||
* cogent/cma101/serial.[ch]). |
||||
*/ |
||||
#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ |
||||
#define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
||||
#undef CONFIG_CONS_NONE /* define if console on something else */ |
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ |
||||
|
||||
/*
|
||||
* select ethernet configuration |
||||
* |
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
||||
* for FCC) |
||||
* |
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
||||
* from CONFIG_COMMANDS to remove support for networking. |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
||||
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ |
||||
|
||||
#if (CONFIG_ETHER_INDEX == 2) |
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK13 |
||||
* - Tx-CLK is CLK14 |
||||
* - Select bus for bd/buffers (see 28-13) |
||||
* - Half duplex |
||||
*/ |
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) |
||||
# define CFG_CPMFCR_RAMTYPE 0 |
||||
# define CFG_FCC_PSMR 0 |
||||
|
||||
#endif /* CONFIG_ETHER_INDEX */ |
||||
|
||||
/* other options */ |
||||
#define CONFIG_HARD_I2C 1 /* To enable I2C support */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
|
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ |
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_BSP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DOC | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_FDC | \
|
||||
CFG_CMD_HWFLOW | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_KGDB | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PCMCIA | \
|
||||
CFG_CMD_SCSI | \
|
||||
CFG_CMD_VFD | \
|
||||
CFG_CMD_USB ) ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */ |
||||
#define CONFIG_BOOTARGS "root=/dev/ram rw" |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
||||
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ |
||||
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ |
||||
#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ |
||||
#endif |
||||
|
||||
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
/* for versions < 2.4.5-pre5 */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
#define CFG_FLASH_BASE 0xff800000 |
||||
#define FLASH_BASE 0xff800000 |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ |
||||
#define CFG_FLASH_SIZE 8 |
||||
#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/* this is stuff came out of the Motorola docs */ |
||||
#define CFG_DEFAULT_IMMR 0x0F010000 |
||||
|
||||
#define CFG_IMMR 0x04700000 |
||||
#define CFG_BCSR 0x04500000 |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_LSDRAM_BASE 0x04000000 |
||||
|
||||
#define RS232EN_1 0x02000002 |
||||
#define RS232EN_2 0x01000001 |
||||
#define FETHIEN 0x08000008 |
||||
#define FETH_RST 0x04000004 |
||||
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
|
||||
/* 0x0EA28205 */ |
||||
#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ |
||||
( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
|
||||
( HRCW_BMS | HRCW_APPC10 ) |\
|
||||
( HRCW_MODCK_H0101 ) \
|
||||
) |
||||
|
||||
/* no slaves */ |
||||
#define CFG_HRCW_SLAVE1 0 |
||||
#define CFG_HRCW_SLAVE2 0 |
||||
#define CFG_HRCW_SLAVE3 0 |
||||
#define CFG_HRCW_SLAVE4 0 |
||||
#define CFG_HRCW_SLAVE5 0 |
||||
#define CFG_HRCW_SLAVE6 0 |
||||
#define CFG_HRCW_SLAVE7 0 |
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
# define CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
#ifndef CFG_RAMBOOT |
||||
# define CFG_ENV_IS_IN_FLASH 1 |
||||
# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
# define CFG_ENV_SECT_SIZE 0x40000 |
||||
#else |
||||
# define CFG_ENV_IS_IN_NVRAM 1 |
||||
# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
# define CFG_ENV_SIZE 0x200 |
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
|
||||
#define CFG_HID0_INIT 0 |
||||
#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) |
||||
|
||||
#define CFG_HID2 0 |
||||
|
||||
#define CFG_SYPCR 0xFFFFFFC3 |
||||
#define CFG_BCR 0x100C0000 |
||||
#define CFG_SIUMCR 0x0A200000 |
||||
#define CFG_SCCR 0x00000000 |
||||
#define CFG_BR0_PRELIM 0xFF801801 |
||||
#define CFG_OR0_PRELIM 0xFF800836 |
||||
#define CFG_BR1_PRELIM 0x04501801 |
||||
#define CFG_OR1_PRELIM 0xFFFF8010 |
||||
|
||||
#define CFG_RMR 0 |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
#define CFG_RCCR 0 |
||||
#define CFG_PSDMR 0x016EB452 |
||||
#define CFG_MPTPR 0x00001900 |
||||
#define CFG_PSRT 0x00000021 |
||||
|
||||
#define CFG_RESET_ADDRESS 0x04400000 |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,266 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* |
||||
* Configuration settings for the PCIPPC-2 board. |
||||
* |
||||
*/ |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 |
||||
#define CONFIG_MISC_INIT_R 1 |
||||
|
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 9600 |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */ |
||||
|
||||
#define CONFIG_PREBOOT "" |
||||
#define CONFIG_BOOTDELAY 5 |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ |
||||
CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_BSP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DOC | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_PCI ) |
||||
|
||||
#define CONFIG_PCI 1 |
||||
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ |
||||
|
||||
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
|
||||
*/ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
|
||||
/* Print Buffer Size
|
||||
*/ |
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) |
||||
|
||||
#define CFG_MAXARGS 64 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFFF00000 |
||||
#define CFG_FLASH_MAX_SIZE 0x00100000 |
||||
/* Maximum amount of RAM.
|
||||
*/ |
||||
#define CFG_MAX_RAM_SIZE 0x20000000 /* 512Mb */ |
||||
|
||||
#define CFG_RESET_ADDRESS 0xFFF00100 |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \ |
||||
CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area |
||||
*/ |
||||
|
||||
/* Size in bytes reserved for initial data
|
||||
*/ |
||||
#define CFG_GBL_DATA_SIZE 128 |
||||
|
||||
#define CFG_INIT_RAM_ADDR 0x40000000 |
||||
#define CFG_INIT_RAM_END 0x8000 |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_INIT_RAM_LOCK |
||||
|
||||
/*
|
||||
* Temporary buffer for serial data until the real serial driver |
||||
* is initialised (memtest will destroy this buffer) |
||||
*/ |
||||
#define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR |
||||
#define CFG_SCONSOLE_SIZE 0x0002000 |
||||
|
||||
/* SDRAM 0 - 256MB
|
||||
*/ |
||||
#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_DBAT0U (CFG_SDRAM_BASE | \ |
||||
BATU_BL_256M | BATU_VS | BATU_VP) |
||||
/* SDRAM 1 - 256MB
|
||||
*/ |
||||
#define CFG_DBAT1L ((CFG_SDRAM_BASE + 0x10000000) | \ |
||||
BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_DBAT1U ((CFG_SDRAM_BASE + 0x10000000) | \ |
||||
BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* Init RAM in the CPU DCache (no backing memory)
|
||||
*/ |
||||
#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | \ |
||||
BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | \ |
||||
BATU_BL_128K | BATU_VS | BATU_VP) |
||||
|
||||
/* I/O and PCI memory at 0xf0000000
|
||||
*/ |
||||
#define CFG_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
||||
#define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
#define CFG_IBAT0L CFG_DBAT0L |
||||
#define CFG_IBAT0U CFG_DBAT0U |
||||
#define CFG_IBAT1L CFG_DBAT1L |
||||
#define CFG_IBAT1U CFG_DBAT1U |
||||
#define CFG_IBAT2L CFG_DBAT2L |
||||
#define CFG_IBAT2U CFG_DBAT2U |
||||
#define CFG_IBAT3L CFG_DBAT3L |
||||
#define CFG_IBAT3U CFG_DBAT3U |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
* For the detail description refer to the PCIPPC2 user's manual. |
||||
*/ |
||||
#define CFG_HZ 1000 |
||||
#define CFG_BUS_HZ 100000000 /* bus speed - 100 mhz */ |
||||
#define CFG_CPU_CLK 300000000 |
||||
#define CFG_BUS_CLK 100000000 |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ |
||||
#define CFG_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/*
|
||||
* Note: environment is not EMBEDDED in the U-Boot code. |
||||
* It's stored in flash separately. |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x70000) |
||||
#define CFG_ENV_SIZE 0x1000 /* Size of the Environment */ |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* L2 cache |
||||
*/ |
||||
#undef CFG_L2 |
||||
#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ |
||||
L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) |
||||
#define L2_ENABLE (L2_INIT | L2CR_L2E) |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Disk-On-Chip configuration |
||||
*/ |
||||
|
||||
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ |
||||
|
||||
#define CFG_DOC_SUPPORT_2000 |
||||
#undef CFG_DOC_SUPPORT_MILLENNIUM |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
RTC m48t59 |
||||
*/ |
||||
#define CONFIG_RTC_MK48T59 |
||||
|
||||
#define CONFIG_WATCHDOG |
||||
|
||||
#define CONFIG_NET_MULTI /* Multi ethernet cards support */ |
||||
|
||||
#define CONFIG_EEPRO100 |
||||
#define CONFIG_TULIP |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,282 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* |
||||
* Configuration settings for the PCIPPC-6 board. |
||||
* |
||||
*/ |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 |
||||
#define CONFIG_MISC_INIT_R 1 |
||||
|
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 9600 |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */ |
||||
|
||||
#define CONFIG_PREBOOT "" |
||||
#define CONFIG_BOOTDELAY 5 |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ |
||||
CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_BSP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DOC | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_SCSI ) |
||||
|
||||
|
||||
#define CONFIG_PCI 1 |
||||
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ |
||||
|
||||
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
|
||||
*/ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
|
||||
/* Print Buffer Size
|
||||
*/ |
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) |
||||
|
||||
#define CFG_MAXARGS 64 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFFF00000 |
||||
#define CFG_FLASH_MAX_SIZE 0x00100000 |
||||
/* Maximum amount of RAM.
|
||||
*/ |
||||
#define CFG_MAX_RAM_SIZE 0x20000000 /* 512Mb */ |
||||
|
||||
#define CFG_RESET_ADDRESS 0xFFF00100 |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \ |
||||
CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area |
||||
*/ |
||||
|
||||
/* Size in bytes reserved for initial data
|
||||
*/ |
||||
#define CFG_GBL_DATA_SIZE 128 |
||||
|
||||
#define CFG_INIT_RAM_ADDR 0x40000000 |
||||
#define CFG_INIT_RAM_END 0x8000 |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_INIT_RAM_LOCK |
||||
|
||||
/*
|
||||
* Temporary buffer for serial data until the real serial driver |
||||
* is initialised (memtest will destroy this buffer) |
||||
*/ |
||||
#define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR |
||||
#define CFG_SCONSOLE_SIZE 0x0002000 |
||||
|
||||
/* SDRAM 0 - 256MB
|
||||
*/ |
||||
#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_DBAT0U (CFG_SDRAM_BASE | \ |
||||
BATU_BL_256M | BATU_VS | BATU_VP) |
||||
/* SDRAM 1 - 256MB
|
||||
*/ |
||||
#define CFG_DBAT1L ((CFG_SDRAM_BASE + 0x10000000) | \ |
||||
BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_DBAT1U ((CFG_SDRAM_BASE + 0x10000000) | \ |
||||
BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* Init RAM in the CPU DCache (no backing memory)
|
||||
*/ |
||||
#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | \ |
||||
BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | \ |
||||
BATU_BL_128K | BATU_VS | BATU_VP) |
||||
|
||||
/* I/O and PCI memory at 0xf0000000
|
||||
*/ |
||||
#define CFG_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
||||
#define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
#define CFG_IBAT0L CFG_DBAT0L |
||||
#define CFG_IBAT0U CFG_DBAT0U |
||||
#define CFG_IBAT1L CFG_DBAT1L |
||||
#define CFG_IBAT1U CFG_DBAT1U |
||||
#define CFG_IBAT2L CFG_DBAT2L |
||||
#define CFG_IBAT2U CFG_DBAT2U |
||||
#define CFG_IBAT3L CFG_DBAT3L |
||||
#define CFG_IBAT3U CFG_DBAT3U |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
* For the detail description refer to the PCIPPC2 user's manual. |
||||
*/ |
||||
#define CFG_HZ 1000 |
||||
#define CFG_BUS_HZ 100000000 /* bus speed - 100 mhz */ |
||||
#define CFG_CPU_CLK 300000000 |
||||
#define CFG_BUS_CLK 100000000 |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ |
||||
#define CFG_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/*
|
||||
* Note: environment is not EMBEDDED in the U-Boot code. |
||||
* It's stored in flash separately. |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x70000) |
||||
#define CFG_ENV_SIZE 0x1000 /* Size of the Environment */ |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* L2 cache |
||||
*/ |
||||
#undef CFG_L2 |
||||
#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ |
||||
L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) |
||||
#define L2_ENABLE (L2_INIT | L2CR_L2E) |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Disk-On-Chip configuration |
||||
*/ |
||||
|
||||
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ |
||||
|
||||
#define CFG_DOC_SUPPORT_2000 |
||||
#undef CFG_DOC_SUPPORT_MILLENNIUM |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
RTC m48t59 |
||||
*/ |
||||
#define CONFIG_RTC_MK48T59 |
||||
|
||||
#define CONFIG_WATCHDOG |
||||
|
||||
#define CONFIG_NET_MULTI /* Multi ethernet cards support */ |
||||
|
||||
#define CONFIG_EEPRO100 |
||||
#define CONFIG_TULIP |
||||
|
||||
|
||||
#define CONFIG_SCSI_SYM53C8XX |
||||
#define CONFIG_SCSI_DEV_ID 0x000B /* 53c896 */ |
||||
#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ |
||||
#define CFG_SCSI_MAX_SCSI_ID 15 /* maximum SCSI ID (0..6) */ |
||||
#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */ |
||||
#define CFG_SCSI_SPIN_UP_TIME 2 |
||||
#define CFG_SCSI_SCAN_BUS_REVERSE 0 |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_ISO_PARTITION |
||||
|
||||
|
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,467 @@ |
||||
/*
|
||||
* (C) Copyright 2000, 2001, 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ |
||||
#define CONFIG_RRVISION 1 /* ...on a RRvision board */ |
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ 64000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_PREBOOT "setenv stdout serial" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_ETHADDR 00:50:C2:00:E0:70 |
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 |
||||
#define CONFIG_IPADDR 10.0.0.5 |
||||
#define CONFIG_SERVERIP 10.0.0.2 |
||||
#define CONFIG_NETMASK 255.0.0.0 |
||||
#define CONFIG_ROOTPATH /opt/eldk/ppc_8xx |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip)" \
|
||||
":$(gatewayip):$(netmask):$(hostname):$(netdev):off\0" \
|
||||
"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
|
||||
"load=tftp 100000 /tftpboot/u-boot.bin\0" \
|
||||
"update=protect off 1:0-8;era 1:0-8;" \
|
||||
"cp.b 100000 40000000 $(filesize);" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"kernel_addr=40040000\0" \
|
||||
"ramdisk_addr=40100000\0" \
|
||||
"kernel_img=/tftpboot/pImage\0" \
|
||||
"kernel_load=tftp 200000 $(kernel_img)\0" \
|
||||
"net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \
|
||||
"flash_nfs=run nfsargs addip addtty;bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm $(kernel_addr) $(ramdisk_addr)\0" |
||||
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#undef CONFIG_STATUS_LED /* disturbs display */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
|
||||
#if 1 |
||||
#define CONFIG_VIDEO 1 /* To enable the video initialization */ |
||||
|
||||
/* Video related */ |
||||
#define CONFIG_VIDEO_LOGO 1 /* Show the logo */ |
||||
#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */ |
||||
#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x2A /* ALSB to ground */ |
||||
#endif |
||||
|
||||
/* enable I2C and select the hardware/software driver */ |
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
|
||||
# define CFG_I2C_SPEED 50000 /* 50 kHz is supposed to work */ |
||||
# define CFG_I2C_SLAVE 0xFE |
||||
|
||||
#ifdef CONFIG_SOFT_I2C |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PB_SCL 0x00000020 /* PB 26 */ |
||||
#define PB_SDA 0x00000010 /* PB 27 */ |
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA |
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL |
||||
#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */ |
||||
#endif /* CONFIG_SOFT_I2C */ |
||||
|
||||
|
||||
|
||||
#define CONFIG_COMMANDS ( ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_DATE ) & \
|
||||
~( CFG_CMD_PCMCIA | \
|
||||
CFG_CMD_IDE ) ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x40000000 |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
||||
|
||||
/* timeout values are in ticks = ms */ |
||||
#define CFG_FLASH_ERASE_TOUT (120*CFG_HZ) /* Timeout for Flash Erase */ |
||||
#define CFG_FLASH_WRITE_TOUT (1 * CFG_HZ) /* Timeout for Flash Write */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit |
||||
*/ |
||||
|
||||
/* for 64 MHz, we use a 16 MHz clock * 4 */ |
||||
#define CFG_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CFG_SCCR (/* SCCR_TBS | */ SCCR_RTSEL | SCCR_RTDIV | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CFG_DER 0x2002000F*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/*
|
||||
* FLASH timing: |
||||
*/ |
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI) |
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CFG_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) |
||||
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CFG_OR3_PRELIM CFG_OR2_PRELIM |
||||
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
||||
#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
||||
#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
||||
#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) |
||||
#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ |
||||
BR_PS_8 | BR_MS_UPMB | BR_V ) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
* |
||||
* The Divider for PTA (refresh timer) configuration is based on an |
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to |
||||
* the number of chip selects (NCS) and the actually needed refresh |
||||
* rate is done by setting MPTPR. |
||||
* |
||||
* PTA is calculated from |
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) |
||||
* |
||||
* gclk CPU clock (not bus clock!) |
||||
* Trefresh Refresh cycle * 4 (four word bursts used) |
||||
* |
||||
* 4096 Rows from SDRAM example configuration |
||||
* 1000 factor s -> ms |
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration |
||||
* 4 Number of refresh cycles per period |
||||
* 64 Refresh cycle in ms per number of rows |
||||
* -------------------------------------------- |
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 |
||||
* |
||||
* 50 MHz => 50.000.000 / Divider = 98 |
||||
* 66 Mhz => 66.000.000 / Divider = 129 |
||||
* 80 Mhz => 80.000.000 / Divider = 156 |
||||
*/ |
||||
#define CFG_MAMR_PTA 129 |
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us |
||||
* (= 64 ms / 2K = 125 / quad bursts). |
||||
* For a simpler initialization, 15.6 us is used instead. |
||||
* |
||||
* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
||||
* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
||||
*/ |
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,326 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ |
||||
#define CONFIG_4xx 1 /* ...member of PPC405 family */ |
||||
#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ |
||||
#define CONFIG_W7OLMC 1 /* ...specifically an LMC */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
||||
|
||||
#define CONFIG_BAUDRATE 9600 |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
||||
|
||||
#if 1 |
||||
#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */ |
||||
#else |
||||
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ |
||||
#endif |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_LOADADDR F0080000 |
||||
|
||||
#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */ |
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE |
||||
#define CONFIG_IPADDR 192.168.1.1 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_SERVERIP 192.168.1.2 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* disallow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */ |
||||
|
||||
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ |
||||
|
||||
#define CONFIG_COMMANDS \ |
||||
(CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ |
||||
|
||||
#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ |
||||
#undef CFG_HUSH_PARSER /* No hush parse for U-Boot */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ |
||||
#define CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
||||
#define CFG_BASE_BAUD 384000 |
||||
|
||||
|
||||
/* The following table includes the supported baudrates */ |
||||
#define CFG_BAUDRATE_TABLE {9600} |
||||
|
||||
#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* use extended board_info (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */ |
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
||||
|
||||
|
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
||||
#define CONFIG_PCI_PNP /* pci plug-and-play */ |
||||
/* resource configuration */ |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ |
||||
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
||||
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ |
||||
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
||||
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Set up values for external bus controller |
||||
* used by cpu_init.c |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */ |
||||
#undef CONFIG_USE_PERWE |
||||
|
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
||||
#define CFG_TEMP_STACK_OCM 1 |
||||
|
||||
/* bank 0 is boot flash */ |
||||
/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ |
||||
#define CFG_W7O_EBC_PB0AP 0x03050440 |
||||
/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */ |
||||
#define CFG_W7O_EBC_PB0CR 0xFFE38000 |
||||
|
||||
/* bank 1 is main flash */ |
||||
/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */ |
||||
#define CFG_EBC_PB1AP 0x05850240 |
||||
/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */ |
||||
#define CFG_EBC_PB1CR 0xF00FC000 |
||||
|
||||
/* bank 2 is RTC/NVRAM */ |
||||
/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ |
||||
#define CFG_EBC_PB2AP 0x03000440 |
||||
/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ |
||||
#define CFG_EBC_PB2CR 0xFC018000 |
||||
|
||||
/* bank 3 is FPGA 0 */ |
||||
/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */ |
||||
#define CFG_EBC_PB3AP 0x02000400 |
||||
/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */ |
||||
#define CFG_EBC_PB3CR 0xFD01A000 |
||||
|
||||
/* bank 4 is FPGA 1 */ |
||||
/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ |
||||
#define CFG_EBC_PB4AP 0x02000400 |
||||
/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */ |
||||
#define CFG_EBC_PB4CR 0xFD11A000 |
||||
|
||||
/* bank 5 is FPGA 2 */ |
||||
/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ |
||||
#define CFG_EBC_PB5AP 0x02000400 |
||||
/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */ |
||||
#define CFG_EBC_PB5CR 0xFD21A000 |
||||
|
||||
/* bank 6 is unused */ |
||||
/* pb6ap = 0 */ |
||||
#define CFG_EBC_PB6AP 0x00000000 |
||||
/* pb6cr = 0 */ |
||||
#define CFG_EBC_PB6CR 0x00000000 |
||||
|
||||
/* bank 7 is LED register */ |
||||
/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ |
||||
#define CFG_W7O_EBC_PB7AP 0x03050440 |
||||
/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */ |
||||
#define CFG_W7O_EBC_PB7CR 0xFE01C000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFFFC0000 |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ |
||||
#define CFG_FLASH_PROTECTION 1 /* Use real Flash protection */ |
||||
|
||||
#if 1 /* Use NVRAM for environment variables */ |
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM organization |
||||
*/ |
||||
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ |
||||
#define CFG_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ |
||||
#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ |
||||
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
||||
/*define CFG_ENV_ADDR \
|
||||
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env */ |
||||
#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR |
||||
|
||||
#else /* Use Boot Flash for environment variables */ |
||||
/*-----------------------------------------------------------------------
|
||||
* Flash EEPROM for environment |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x10000 /* Total Size of env. sector */ |
||||
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (CAT24WC08) for environment |
||||
*/ |
||||
#define CONFIG_HARD_I2C /* I2c with hardware support */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
||||
/* 16 byte page write mode using*/ |
||||
/* last 4 bits of the address */ |
||||
#define CFG_I2C_MULTI_EEPROMS |
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for Serial Presence Detect EEPROM address |
||||
* (to get SDRAM settings) |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
*/ |
||||
#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ |
||||
|
||||
/* On Chip Memory location */ |
||||
#define CFG_OCM_DATA_ADDR 0xF8000000 |
||||
#define CFG_OCM_DATA_SIZE 0x1000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in RAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ |
||||
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* FPGA(s) configuration |
||||
*/ |
||||
#define CFG_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ |
||||
#define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */ |
||||
#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ |
||||
#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ |
||||
#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
|
@ -0,0 +1,326 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ |
||||
#define CONFIG_4xx 1 /* ...member of PPC405 family */ |
||||
#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ |
||||
#define CONFIG_W7OLMG 1 /* ...specifically an LMG */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
||||
|
||||
#define CONFIG_BAUDRATE 9600 |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
||||
|
||||
#if 1 |
||||
#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */ |
||||
#else |
||||
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ |
||||
#endif |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_LOADADDR F0080000 |
||||
|
||||
#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */ |
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE |
||||
#define CONFIG_IPADDR 192.168.1.1 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_SERVERIP 192.168.1.2 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* disallow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */ |
||||
|
||||
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ |
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
||||
#define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */ |
||||
#define CFG_DTT_MAX_TEMP 70 |
||||
#define CFG_DTT_LOW_TEMP -30 |
||||
#define CFG_DTT_HYSTERESIS 3 |
||||
|
||||
#define CONFIG_COMMANDS \ |
||||
(CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO | \
|
||||
CFG_CMD_DTT) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ |
||||
|
||||
#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ |
||||
#undef CFG_HUSH_PARSER /* No hush parse for U-Boot */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ |
||||
#define CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
||||
#define CFG_BASE_BAUD 384000 |
||||
|
||||
|
||||
/* The following table includes the supported baudrates */ |
||||
#define CFG_BAUDRATE_TABLE {9600} |
||||
|
||||
#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* use extended board_info (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */ |
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
||||
|
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
||||
#define CONFIG_PCI_PNP /* pci plug-and-play */ |
||||
/* resource configuration */ |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ |
||||
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
||||
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ |
||||
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
||||
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Set up values for external bus controller |
||||
* used by cpu_init.c |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* use PerWE instead of PCI_INT ( these functions share a pin ) */ |
||||
#define CONFIG_USE_PERWE 1 |
||||
|
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
||||
#define CFG_TEMP_STACK_OCM 1 |
||||
|
||||
/* bank 0 is boot flash */ |
||||
/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ |
||||
#define CFG_W7O_EBC_PB0AP 0x03050440 |
||||
/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */ |
||||
#define CFG_W7O_EBC_PB0CR 0xFFE38000 |
||||
|
||||
/* bank 1 is main flash */ |
||||
/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */ |
||||
#define CFG_EBC_PB1AP 0x04850240 |
||||
/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */ |
||||
#define CFG_EBC_PB1CR 0xF00FC000 |
||||
|
||||
/* bank 2 is RTC/NVRAM */ |
||||
/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ |
||||
#define CFG_EBC_PB2AP 0x03000440 |
||||
/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ |
||||
#define CFG_EBC_PB2CR 0xFC018000 |
||||
|
||||
/* bank 3 is FPGA 0 */ |
||||
/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */ |
||||
#define CFG_EBC_PB3AP 0x02000400 |
||||
/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */ |
||||
#define CFG_EBC_PB3CR 0xFD01A000 |
||||
|
||||
/* bank 4 is SAM 8 bit range */ |
||||
/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ |
||||
#define CFG_EBC_PB4AP 0x02840380 |
||||
/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */ |
||||
#define CFG_EBC_PB4CR 0xFE878000 |
||||
|
||||
/* bank 5 is SAM 16 bit range */ |
||||
/* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */ |
||||
#define CFG_EBC_PB5AP 0x05040d80 |
||||
/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */ |
||||
#define CFG_EBC_PB5CR 0xFD87A000 |
||||
|
||||
/* bank 6 is unused */ |
||||
/* pb6ap = 0 */ |
||||
#define CFG_EBC_PB6AP 0x00000000 |
||||
/* pb6cr = 0 */ |
||||
#define CFG_EBC_PB6CR 0x00000000 |
||||
|
||||
/* bank 7 is LED register */ |
||||
/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ |
||||
#define CFG_W7O_EBC_PB7AP 0x03050440 |
||||
/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */ |
||||
#define CFG_W7O_EBC_PB7CR 0xFE01C000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFFFC0000 |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ |
||||
#define CFG_FLASH_PROTECTION 1 /* Use real Flash protection */ |
||||
|
||||
#if 1 /* Use NVRAM for environment variables */ |
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM organization |
||||
*/ |
||||
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ |
||||
#define CFG_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ |
||||
#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ |
||||
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
||||
/*define CFG_ENV_ADDR \
|
||||
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env */ |
||||
#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR |
||||
|
||||
#else /* Use Boot Flash for environment variables */ |
||||
/*-----------------------------------------------------------------------
|
||||
* Flash EEPROM for environment |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x10000 /* Total Size of env. sector */ |
||||
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (ATMEL 24C04N) |
||||
*/ |
||||
#define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CFG_I2C_MULTI_EEPROMS |
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for Serial Presence Detect EEPROM address |
||||
* (to get SDRAM settings) |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
*/ |
||||
#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ |
||||
|
||||
/* On Chip Memory location */ |
||||
#define CFG_OCM_DATA_ADDR 0xF8000000 |
||||
#define CFG_OCM_DATA_SIZE 0x1000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in RAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ |
||||
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* FPGA(s) configuration |
||||
*/ |
||||
#define CFG_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ |
||||
#define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */ |
||||
#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ |
||||
#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ |
||||
#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,534 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823E CPU */ |
||||
#define CONFIG_LWMON 1 /* ...on a LWMON board */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
||||
|
||||
#define CONFIG_LCD 1 /* use LCD controller ... */ |
||||
#define CONFIG_HLD1045 1 /* ... with a HLD1045 display */ |
||||
|
||||
#if 1 |
||||
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ |
||||
#else |
||||
#define CONFIG_8xx_CONS_SCC2 |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */ |
||||
|
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
/* pre-boot commands */ |
||||
#define CONFIG_PREBOOT "setenv bootdelay 15" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
/* POST support */ |
||||
#define CONFIG_POST (CFG_POST_CACHE | \ |
||||
CFG_POST_WATCHDOG | \
|
||||
CFG_POST_RTC | \
|
||||
CFG_POST_MEMORY | \
|
||||
CFG_POST_CPU | \
|
||||
CFG_POST_UART | \
|
||||
CFG_POST_ETHER | \
|
||||
CFG_POST_SPI | \
|
||||
CFG_POST_USB | \
|
||||
CFG_POST_SPR) |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"kernel_addr=40040000\0" \
|
||||
"ramdisk_addr=40100000\0" \
|
||||
"magic_keys=#3\0" \
|
||||
"key_magic#=28\0" \
|
||||
"key_cmd#=setenv addfb setenv bootargs \\$(bootargs) console=tty0\0" \
|
||||
"key_magic3=24\0" \
|
||||
"key_cmd3=echo *** Entering Test Mode ***;" \
|
||||
"setenv add_misc setenv bootargs \\$(bootargs) testmode\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addfb=setenv bootargs $(bootargs) console=ttyS1,$(baudrate)\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off " \
|
||||
"panic=1\0" \
|
||||
"add_wdt=setenv bootargs $(bootargs) $(wdt_args)\0" \
|
||||
"flash_nfs=run nfsargs addip add_wdt addfb;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip add_wdt addfb;" \
|
||||
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 100000 /tftpboot/pImage.lwmon;" \
|
||||
"run nfsargs addip add_wdt addfb;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_8xx\0" \
|
||||
"load=tftp 100000 /tftpboot/u-boot.bin\0" \
|
||||
"update=protect off 1:0;era 1:0;cp.b 100000 40000000 $(filesize)\0" \
|
||||
"wdt_args=wdt_8xx=off\0" \
|
||||
"verify=no" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#define CONFIG_WATCHDOG 1 /* watchdog enabled */ |
||||
|
||||
#undef CONFIG_STATUS_LED /* Status LED disabled */ |
||||
|
||||
/* enable I2C and select the hardware/software driver */ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
|
||||
#ifdef CONFIG_HARD_I2C |
||||
/*
|
||||
* Hardware (CPM) I2C driver configuration |
||||
*/ |
||||
# define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ |
||||
# define CFG_I2C_SLAVE 0xFE |
||||
#endif /* CONFIG_HARD_I2C */ |
||||
|
||||
#ifdef CONFIG_SOFT_I2C |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PB_SCL 0x00000020 /* PB 26 */ |
||||
#define PB_SDA 0x00000010 /* PB 27 */ |
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA |
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL |
||||
#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */ |
||||
#endif /* CONFIG_SOFT_I2C */ |
||||
|
||||
|
||||
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ |
||||
|
||||
#ifdef CONFIG_POST |
||||
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG |
||||
#else |
||||
#define CFG_CMD_POST_DIAG 0 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_8xx_CONS_SCC2 /* Can't use ethernet, then */ |
||||
#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \ |
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_BSP | \
|
||||
CFG_CMD_POST_DIAG ) |
||||
#else |
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_BSP | \
|
||||
CFG_CMD_POST_DIAG ) |
||||
#endif |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*----------------------------------------------------------------------*/ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#undef CFG_HUSH_PARSER /* enable "hush" shell */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000 /* default load address */ |
||||
|
||||
#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x40000000 |
||||
#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
||||
#endif |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#if 1 |
||||
/* Put environment in flash which is much faster to boot */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR 0x40040000 /* Address of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */ |
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */ |
||||
#else |
||||
/* Environment in EEPROM */ |
||||
#define CFG_ENV_IS_IN_EEPROM 1 |
||||
#define CFG_ENV_OFFSET 0 |
||||
#define CFG_ENV_SIZE 2048 |
||||
#endif |
||||
/*-----------------------------------------------------------------------
|
||||
* I2C/EEPROM Configuration |
||||
*/ |
||||
|
||||
#define CFG_I2C_AUDIO_ADDR 0x28 /* Audio volume control */ |
||||
#define CFG_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */ |
||||
#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ |
||||
#define CFG_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */ |
||||
#define CFG_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */ |
||||
#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ |
||||
#define CFG_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */ |
||||
|
||||
#define CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */ |
||||
#ifdef CONFIG_USE_FRAM /* use FRAM */ |
||||
#define CFG_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 |
||||
#else /* use EEPROM */ |
||||
#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ |
||||
#endif /* CONFIG_USE_FRAM */ |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
/* EARB, DBGC and DBPC are initialised by the HCW */ |
||||
/* => 0x000000C0 */ |
||||
#define CFG_SIUMCR (SIUMCR_GB5E) |
||||
/*#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit, set PLL multiplication factor ! |
||||
*/ |
||||
/* 0x00405000 */ |
||||
#define CFG_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */ |
||||
#define CFG_PLPRCR \ |
||||
( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
|
||||
/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
|
||||
PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
|
||||
) |
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*13200000) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
/* 0x01800000 */ |
||||
#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ |
||||
SCCR_RTDIV | SCCR_RTSEL | \
|
||||
/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
|
||||
SCCR_EBDF00 | SCCR_DFSYNC00 | \
|
||||
SCCR_DFBRG00 | SCCR_DFNL000 | \
|
||||
SCCR_DFNH000 | SCCR_DFLCD100 | \
|
||||
SCCR_DFALCD01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* 0x00C3 => 0x0003 */ |
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration Register 19-4 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RCCR 0x0000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMDS - RISC Microcode Development Support Control Register |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RMDS 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
* Interrupt Levels |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_PCMCIA_MEM_ADDR (0x50000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0x54000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0x58000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0x5C000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CFG_DER 0x2002000F*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) - second Flash bank optional |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */ |
||||
|
||||
/* used to re-map FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CFG_REMAP_OR_AM 0xFF000000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK) |
||||
|
||||
#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ |
||||
CFG_OR_TIMING_FLASH) |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ |
||||
CFG_OR_TIMING_FLASH) |
||||
/* 16 bit, bank valid */ |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) |
||||
|
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP |
||||
#define CFG_OR1_PRELIM CFG_OR0_PRELIM |
||||
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) |
||||
|
||||
/*
|
||||
* BR3/OR3: SDRAM |
||||
* |
||||
* Multiplexed addresses, GPL5 output to GPL5_A (don't care) |
||||
*/ |
||||
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ |
||||
#define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */ |
||||
#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ |
||||
|
||||
#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */ |
||||
|
||||
#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) |
||||
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
/*
|
||||
* BR5/OR5: Touch Panel |
||||
* |
||||
* AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 |
||||
*/ |
||||
#define TOUCHPNL_BASE 0x20000000 |
||||
#define TOUCHPNL_OR_AM 0xFFFF8000 |
||||
#define TOUCHPNL_TIMING OR_SCY_0_CLK |
||||
|
||||
#define CFG_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ |
||||
TOUCHPNL_TIMING ) |
||||
#define CFG_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V ) |
||||
|
||||
#define CFG_MEMORY_75 |
||||
#undef CFG_MEMORY_7E |
||||
#undef CFG_MEMORY_8E |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MPTPR 0x200 |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
#define CFG_MAMR_8COL 0x80802114 |
||||
#define CFG_MAMR_9COL 0x80904114 |
||||
|
||||
/*
|
||||
* MAR setting for SDRAM |
||||
*/ |
||||
#define CFG_MAR 0x00000088 |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,415 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Murray Jensen <Murray.Jensen@cmst.csiro.au> |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* Configuation settings for the R&S Protocol Board board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ |
||||
#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
* |
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
* |
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must |
||||
* defined elsewhere. |
||||
*/ |
||||
#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ |
||||
#define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
||||
#undef CONFIG_CONS_NONE /* define if console on neither */ |
||||
#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ |
||||
|
||||
/*
|
||||
* select ethernet configuration |
||||
* |
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
||||
* for FCC) |
||||
* |
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
||||
* from CONFIG_COMMANDS to remove support for networking. |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ |
||||
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ |
||||
#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ |
||||
|
||||
#if (CONFIG_ETHER_INDEX == 2) |
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK13 |
||||
* - Tx-CLK is CLK14 |
||||
* - Select bus for bd/buffers (see 28-13) |
||||
* - Enable Full Duplex in FSMR |
||||
*/ |
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) |
||||
# define CFG_CPMFCR_RAMTYPE (0) |
||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) |
||||
|
||||
#endif /* CONFIG_ETHER_INDEX */ |
||||
|
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/* enable I2C */ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
||||
#define CONFIG_8260_CLKIN 50000000 /* in Hz */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_KGDB) |
||||
|
||||
/* Define this if you want to boot from 0x00000100. If you don't define
|
||||
* this, you will need to program the bootloader to 0xfff00000, and |
||||
* get the hardware reset config words at 0xfe000000. The simplest |
||||
* way to do that is to program the bootloader at both addresses. |
||||
* It is suggested that you just let U-Boot live at 0x00000000. |
||||
*/ |
||||
#define CFG_RSD_BOOT_LOW 1 |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CONFIG_BOOTDELAY 5 |
||||
#define CONFIG_BOOTARGS "devfs=mount root=ramfs" |
||||
#define CONFIG_ETHADDR 08:00:3e:26:0a:5a |
||||
#define CONFIG_NETMASK 255.255.0.0 |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
/* valid baudrates */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */ |
||||
#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */ |
||||
|
||||
#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */ |
||||
#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */ |
||||
|
||||
#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */ |
||||
#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */ |
||||
|
||||
/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */ |
||||
/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */ |
||||
|
||||
#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */ |
||||
#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */ |
||||
|
||||
/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */ |
||||
/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */ |
||||
|
||||
#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */ |
||||
#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100 |
||||
|
||||
#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */ |
||||
#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */ |
||||
|
||||
#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */ |
||||
|
||||
#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */ |
||||
#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ |
||||
|
||||
#define CFG_IMMR PHYS_IMMR |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Reset Address |
||||
* |
||||
* In order to reset the CPU, U-Boot jumps to a special address which |
||||
* causes a machine check exception. The default address for this is |
||||
* CFG_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when |
||||
* testing the monitor in RAM using a JTAG debugger. |
||||
* |
||||
* Just set CFG_RESET_ADDRESS to an address that you know is sure to |
||||
* cause a bus error on your hardware. |
||||
*/ |
||||
#define CFG_RESET_ADDRESS 0x20000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words |
||||
*/ |
||||
|
||||
#if defined(CFG_RSD_BOOT_LOW) |
||||
# define CFG_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) |
||||
#else |
||||
# define CFG_RSD_HRCW_BOOT_FLAGS (0) |
||||
#endif /* defined(CFG_RSD_BOOT_LOW) */ |
||||
|
||||
/* get the HRCW ISB field from CFG_IMMR */ |
||||
#define CFG_RSD_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\ |
||||
((CFG_IMMR & 0x01000000) >> 7) |\
|
||||
((CFG_IMMR & 0x00100000) >> 4) ) |
||||
|
||||
#define CFG_HRCW_MASTER (HRCW_L2CPC10 | \ |
||||
HRCW_DPPC11 | \
|
||||
CFG_RSD_HRCW_IMMR |\
|
||||
HRCW_MMR00 | \
|
||||
HRCW_APPC10 | \
|
||||
HRCW_CS10PC00 | \
|
||||
HRCW_MODCK_H0000 |\
|
||||
CFG_RSD_HRCW_BOOT_FLAGS) |
||||
|
||||
/* no slaves */ |
||||
#define CFG_HRCW_SLAVE1 0 |
||||
#define CFG_HRCW_SLAVE2 0 |
||||
#define CFG_HRCW_SLAVE3 0 |
||||
#define CFG_HRCW_SLAVE4 0 |
||||
#define CFG_HRCW_SLAVE5 0 |
||||
#define CFG_HRCW_SLAVE6 0 |
||||
#define CFG_HRCW_SLAVE7 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
* Note also that the logic that sets CFG_RAMBOOT is platform dependend. |
||||
*/ |
||||
#define CFG_SDRAM_BASE PHYS_SDRAM_60X |
||||
#define CFG_FLASH_BASE PHYS_FLASH |
||||
/*#define CFG_MONITOR_BASE 0x200000 */ |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#if CFG_MONITOR_BASE < CFG_FLASH_BASE |
||||
#define CFG_RAMBOOT |
||||
#endif |
||||
#define CFG_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 63 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/* turn off NVRAM env feature */ |
||||
#undef CONFIG_NVRAM_ENV |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */ |
||||
#define CFG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11 |
||||
*----------------------------------------------------------------------- |
||||
* HID0 also contains cache control - initially enable both caches and |
||||
* invalidate contents, then the final state leaves only the instruction |
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches, |
||||
* but Soft reset does not. |
||||
* |
||||
* HID1 has only read-only information - nothing to set. |
||||
*/ |
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP) |
||||
#define CFG_HID2 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RMR 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_BCR 0x100c0000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CFG_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \ |
||||
SIUMCR_CS10PC01 | SIUMCR_BCTLC01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable |
||||
*/ |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \ |
||||
SYPCR_SWRI | SYPCR_SWP) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40 |
||||
*----------------------------------------------------------------------- |
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, |
||||
* and enable Time Counter |
||||
*/ |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable |
||||
* Periodic timer |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_SCCR 0x00000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RCCR 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
*/ |
||||
|
||||
#define CFG_PSDMR 0x494D2452 |
||||
#define CFG_LSDMR 0x49492552 |
||||
|
||||
/* Flash */ |
||||
#define CFG_BR0_PRELIM (PHYS_FLASH | BRx_V) |
||||
#define CFG_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \ |
||||
ORxG_BCTLD | \
|
||||
ORxG_SCY_5_CLK) |
||||
|
||||
/* DPRAM to the PCI BUS on the protocol board */ |
||||
#define CFG_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V) |
||||
#define CFG_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \ |
||||
ORxG_ACS_DIV4) |
||||
|
||||
/* 60x Bus SDRAM */ |
||||
#define CFG_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V) |
||||
#define CFG_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \ |
||||
ORxS_BPD_4 | \
|
||||
ORxS_ROWST_PBI1_A2 | \
|
||||
ORxS_NUMR_13 | \
|
||||
ORxS_IBID) |
||||
|
||||
/* Virtex-FPGA - Register */ |
||||
#define CFG_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V) |
||||
#define CFG_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \ |
||||
ORxG_SCY_1_CLK | \
|
||||
ORxG_ACS_DIV2 | \
|
||||
ORxG_CSNT ) |
||||
|
||||
/* local bus SDRAM */ |
||||
#define CFG_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V) |
||||
#define CFG_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \ |
||||
ORxS_BPD_4 | \
|
||||
ORxS_ROWST_PBI1_A4 | \
|
||||
ORxS_NUMR_13) |
||||
|
||||
/* DPRAM to the Sharc-Bus on the protocol board */ |
||||
#define CFG_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V) |
||||
#define CFG_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \ |
||||
ORxG_ACS_DIV4) |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,87 @@ |
||||
/*
|
||||
* u-boot/include/linux/mtd/nand.h |
||||
* |
||||
* Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> |
||||
* Steven J. Hill <sjhill@cotw.com> |
||||
* |
||||
* $Id: nand.h,v 1.8 2000/10/30 17:16:17 sjhill Exp $ |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* Info: |
||||
* Contains standard defines and IDs for NAND flash devices |
||||
* |
||||
* Changelog: |
||||
* 01-31-2000 DMW Created |
||||
* 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers |
||||
* so it can be used by other NAND flash device |
||||
* drivers. I also changed the copyright since none |
||||
* of the original contents of this file are specific |
||||
* to DoC devices. David can whack me with a baseball |
||||
* bat later if I did something naughty. |
||||
* 10-11-2000 SJH Added private NAND flash structure for driver |
||||
* 10-24-2000 SJH Added prototype for 'nand_scan' function |
||||
*/ |
||||
#ifndef __LINUX_MTD_NAND_H |
||||
#define __LINUX_MTD_NAND_H |
||||
|
||||
/*
|
||||
* Standard NAND flash commands |
||||
*/ |
||||
#define NAND_CMD_READ0 0 |
||||
#define NAND_CMD_READ1 1 |
||||
#define NAND_CMD_PAGEPROG 0x10 |
||||
#define NAND_CMD_READOOB 0x50 |
||||
#define NAND_CMD_ERASE1 0x60 |
||||
#define NAND_CMD_STATUS 0x70 |
||||
#define NAND_CMD_SEQIN 0x80 |
||||
#define NAND_CMD_READID 0x90 |
||||
#define NAND_CMD_ERASE2 0xd0 |
||||
#define NAND_CMD_RESET 0xff |
||||
|
||||
/*
|
||||
* NAND Flash Manufacturer ID Codes |
||||
*/ |
||||
#define NAND_MFR_TOSHIBA 0x98 |
||||
#define NAND_MFR_SAMSUNG 0xec |
||||
|
||||
/*
|
||||
* NAND Flash Device ID Structure |
||||
* |
||||
* Structure overview: |
||||
* |
||||
* name - Complete name of device |
||||
* |
||||
* manufacture_id - manufacturer ID code of device. |
||||
* |
||||
* model_id - model ID code of device. |
||||
* |
||||
* chipshift - total number of address bits for the device which |
||||
* is used to calculate address offsets and the total |
||||
* number of bytes the device is capable of. |
||||
* |
||||
* page256 - denotes if flash device has 256 byte pages or not. |
||||
* |
||||
* pageadrlen - number of bytes minus one needed to hold the |
||||
* complete address into the flash array. Keep in |
||||
* mind that when a read or write is done to a |
||||
* specific address, the address is input serially |
||||
* 8 bits at a time. This structure member is used |
||||
* by the read/write routines as a loop index for |
||||
* shifting the address out 8 bits at a time. |
||||
* |
||||
* erasesize - size of an erase block in the flash device. |
||||
*/ |
||||
struct nand_flash_dev { |
||||
char * name; |
||||
int manufacture_id; |
||||
int model_id; |
||||
int chipshift; |
||||
char page256; |
||||
char pageadrlen; |
||||
unsigned long erasesize; |
||||
}; |
||||
|
||||
#endif /* __LINUX_MTD_NAND_H */ |
@ -0,0 +1,52 @@ |
||||
/*
|
||||
* u-boot/include/linux/mtd/nand_ids.h |
||||
* |
||||
* Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> |
||||
* Steven J. Hill <sjhill@cotw.com> |
||||
* |
||||
* $Id: nand_ids.h,v 1.1 2000/10/13 16:16:26 mdeans Exp $ |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* Info: |
||||
* Contains standard defines and IDs for NAND flash devices |
||||
* |
||||
* Changelog: |
||||
* 01-31-2000 DMW Created |
||||
* 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers |
||||
* so it can be used by other NAND flash device |
||||
* drivers. I also changed the copyright since none |
||||
* of the original contents of this file are specific |
||||
* to DoC devices. David can whack me with a baseball |
||||
* bat later if I did something naughty. |
||||
* 10-11-2000 SJH Added private NAND flash structure for driver |
||||
* 2000-10-13 BE Moved out of 'nand.h' - avoids duplication. |
||||
*/ |
||||
|
||||
#ifndef __LINUX_MTD_NAND_IDS_H |
||||
#define __LINUX_MTD_NAND_IDS_H |
||||
|
||||
static struct nand_flash_dev nand_flash_ids[] = { |
||||
{"Toshiba TC5816BDC", NAND_MFR_TOSHIBA, 0x64, 21, 1, 2, 0x1000}, |
||||
{"Toshiba TC5832DC", NAND_MFR_TOSHIBA, 0x6b, 22, 0, 2, 0x2000}, |
||||
{"Toshiba TH58V128DC", NAND_MFR_TOSHIBA, 0x73, 24, 0, 2, 0x4000}, |
||||
{"Toshiba TC58256FT/DC", NAND_MFR_TOSHIBA, 0x75, 25, 0, 2, 0x4000}, |
||||
{"Toshiba TH58512FT", NAND_MFR_TOSHIBA, 0x76, 26, 0, 3, 0x4000}, |
||||
{"Toshiba TC58V32DC", NAND_MFR_TOSHIBA, 0xe5, 22, 0, 2, 0x2000}, |
||||
{"Toshiba TC58V64AFT/DC", NAND_MFR_TOSHIBA, 0xe6, 23, 0, 2, 0x2000}, |
||||
{"Toshiba TC58V16BDC", NAND_MFR_TOSHIBA, 0xea, 21, 1, 2, 0x1000}, |
||||
{"Samsung KM29N16000", NAND_MFR_SAMSUNG, 0x64, 21, 1, 2, 0x1000}, |
||||
{"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0x6b, 22, 0, 2, 0x2000}, |
||||
{"Samsung KM29U128T", NAND_MFR_SAMSUNG, 0x73, 24, 0, 2, 0x4000}, |
||||
{"Samsung KM29U256T", NAND_MFR_SAMSUNG, 0x75, 25, 0, 2, 0x4000}, |
||||
{"Samsung unknown 64Mb", NAND_MFR_SAMSUNG, 0x76, 26, 0, 3, 0x4000}, |
||||
{"Samsung KM29W32000", NAND_MFR_SAMSUNG, 0xe3, 22, 0, 2, 0x2000}, |
||||
{"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0xe5, 22, 0, 2, 0x2000}, |
||||
{"Samsung KM29U64000", NAND_MFR_SAMSUNG, 0xe6, 23, 0, 2, 0x2000}, |
||||
{"Samsung KM29W16000", NAND_MFR_SAMSUNG, 0xea, 21, 1, 2, 0x1000}, |
||||
{NULL,} |
||||
}; |
||||
|
||||
#endif /* __LINUX_MTD_NAND_IDS_H */ |
Loading…
Reference in new issue