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exynos: clock: use the clear and set bits macros.

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Use setbits/clrbits macro instead of readl/writel function.
(Suggested by Wolfgang)

Signed-off-by: Inha Song <ideal.song@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
master
Inha Song 11 years ago committed by Minkyu Kang
parent 3cb007a9f2
commit e25bfecf7b
1 changed files with 20 additions and 65 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 85
      arch/arm/cpu/armv7/exynos/clock.c

85
arch/arm/cpu/armv7/exynos/clock.c
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@ -870,7 +870,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned int addr;
unsigned int val;
/*
* CLK_DIV_FSYS1
@ -890,10 +889,8 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
dev_index -= 2;
}
val = readl(addr);
val &= ~(0xff << ((dev_index << 4) + 8));
val |= (div & 0xff) << ((dev_index << 4) + 8);
writel(val, addr);
clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
(div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos4x12: set the mmc clock */
@ -902,7 +899,6 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
struct exynos4x12_clock *clk =
(struct exynos4x12_clock *)samsung_get_base_clock();
unsigned int addr;
unsigned int val;
/*
* CLK_DIV_FSYS1
@ -917,10 +913,8 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
dev_index -= 2;
}
val = readl(addr);
val &= ~(0xff << ((dev_index << 4) + 8));
val |= (div & 0xff) << ((dev_index << 4) + 8);
writel(val, addr);
clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
(div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos5: set the mmc clock */
@ -929,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned int addr;
unsigned int val;
/*
* CLK_DIV_FSYS1
@ -944,10 +937,8 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
dev_index -= 2;
}
val = readl(addr);
val &= ~(0xff << ((dev_index << 4) + 8));
val |= (div & 0xff) << ((dev_index << 4) + 8);
writel(val, addr);
clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
(div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos5: set the mmc clock */
@ -956,7 +947,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned int addr;
unsigned int val, shift;
unsigned int shift;
/*
* CLK_DIV_FSYS1
@ -967,10 +958,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
addr = (unsigned int)&clk->div_fsys1;
shift = dev_index * 10;
val = readl(addr);
val &= ~(0x3ff << shift);
val |= (div & 0x3ff) << shift;
writel(val, addr);
clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
}
/* get_lcd_clk: return lcd clock frequency */
@ -1061,7 +1049,6 @@ void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned int cfg = 0;
/*
* CLK_GATE_BLOCK
@ -1073,9 +1060,7 @@ void exynos4_set_lcd_clk(void)
* CLK_LCD1 [5]
* CLK_GPS [7]
*/
cfg = readl(&clk->gate_block);
cfg |= 1 << 4;
writel(cfg, &clk->gate_block);
setbits_le32(&clk->gate_block, 1 << 4);
/*
* CLK_SRC_LCD0
@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
* MIPI0_SEL [12:15]
* set lcd0 src clock 0x6: SCLK_MPLL
*/
cfg = readl(&clk->src_lcd0);
cfg &= ~(0xf);
cfg |= 0x6;
writel(cfg, &clk->src_lcd0);
clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
/*
* CLK_GATE_IP_LCD0
@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for FIMD0
*/
cfg = readl(&clk->gate_ip_lcd0);
cfg |= 1 << 0;
writel(cfg, &clk->gate_ip_lcd0);
setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
/*
* CLK_DIV_LCD0
@ -1114,17 +1094,13 @@ void exynos4_set_lcd_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
cfg = readl(&clk->div_lcd0);
cfg &= ~(0xf);
cfg |= 0x1;
writel(cfg, &clk->div_lcd0);
clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
}
void exynos5_set_lcd_clk(void)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned int cfg = 0;
/*
* CLK_GATE_BLOCK
@ -1136,9 +1112,7 @@ void exynos5_set_lcd_clk(void)
* CLK_LCD1 [5]
* CLK_GPS [7]
*/
cfg = readl(&clk->gate_block);
cfg |= 1 << 4;
writel(cfg, &clk->gate_block);
setbits_le32(&clk->gate_block, 1 << 4);
/*
* CLK_SRC_LCD0
@ -1148,10 +1122,7 @@ void exynos5_set_lcd_clk(void)
* MIPI0_SEL [12:15]
* set lcd0 src clock 0x6: SCLK_MPLL
*/
cfg = readl(&clk->src_disp1_0);
cfg &= ~(0xf);
cfg |= 0x6;
writel(cfg, &clk->src_disp1_0);
clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
/*
* CLK_GATE_IP_LCD0
@ -1163,9 +1134,7 @@ void exynos5_set_lcd_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for FIMD0
*/
cfg = readl(&clk->gate_ip_disp1);
cfg |= 1 << 0;
writel(cfg, &clk->gate_ip_disp1);
setbits_le32(&clk->gate_ip_disp1, 1 << 0);
/*
* CLK_DIV_LCD0
@ -1177,17 +1146,13 @@ void exynos5_set_lcd_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
cfg = readl(&clk->div_disp1_0);
cfg &= ~(0xf);
cfg |= 0x0;
writel(cfg, &clk->div_disp1_0);
clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
}
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned int cfg = 0;
/*
* CLK_SRC_LCD0
@ -1197,10 +1162,7 @@ void exynos4_set_mipi_clk(void)
* MIPI0_SEL [12:15]
* set mipi0 src clock 0x6: SCLK_MPLL
*/
cfg = readl(&clk->src_lcd0);
cfg &= ~(0xf << 12);
cfg |= (0x6 << 12);
writel(cfg, &clk->src_lcd0);
clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
/*
* CLK_SRC_MASK_LCD0
@ -1210,9 +1172,7 @@ void exynos4_set_mipi_clk(void)
* MIPI0_MASK [12]
* set src mask mipi0 0x1: Unmask
*/
cfg = readl(&clk->src_mask_lcd0);
cfg |= (0x1 << 12);
writel(cfg, &clk->src_mask_lcd0);
setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
/*
* CLK_GATE_IP_LCD0
@ -1224,9 +1184,7 @@ void exynos4_set_mipi_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for MIPI0
*/
cfg = readl(&clk->gate_ip_lcd0);
cfg |= 1 << 3;
writel(cfg, &clk->gate_ip_lcd0);
setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
/*
* CLK_DIV_LCD0
@ -1238,10 +1196,7 @@ void exynos4_set_mipi_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set mipi ratio
*/
cfg = readl(&clk->div_lcd0);
cfg &= ~(0xf << 16);
cfg |= (0x1 << 16);
writel(cfg, &clk->div_lcd0);
clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
}
/*

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