From 55fe0e2b54173ebdc2aa87c329750c2a70e84fb2 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:43 +0100 Subject: [PATCH 01/31] spl: fix binman_sym output check A previous commit introduced the use of binman in the SPL. After the binman_sym call over the 'pos' symbol, the output value is checked against BINMAN_SYM_MISSING (-1UL). According to the documentation (tools/binman/README), when it comes to the 'pos' attribute: pos: This sets the position of an entry within the image. The first byte of the image is normally at position 0. If 'pos' is not provided, binman sets it to the end of the previous region, or the start of the image's entry area (normally 0) if there is no previous region. So instead of checking if the return value is BINMAN_SYM_MISSING, we should also check if the value is not null. The failure happens when using both the SPL file and the U-Boot file independently instead of the concatenated file (SPL + padding + U-Boot). This is because the U-Boot binary file alone does not have the U-Boot header while it is present in the concatenation file. Not having the header forces the SPL to discover where it should load U-Boot. The binman_sym call is supposed to do that but fails. Because of the wrong check, the destination address was set to 0 while it should have been somewhere in RAM. This, obviously, stalls the board. Fixes: 8bee2d251afb ("binman: Add binman symbol support to SPL") Reviewed-by: Simon Glass Signed-off-by: Miquel Raynal Signed-off-by: Maxime Ripard --- common/spl/spl.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/common/spl/spl.c b/common/spl/spl.c index b1ce56d..61d3071 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -127,8 +127,14 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) ulong u_boot_pos = binman_sym(ulong, u_boot_any, pos); spl_image->size = CONFIG_SYS_MONITOR_LEN; - if (u_boot_pos != BINMAN_SYM_MISSING) { - /* biman does not support separate entry addresses at present */ + + /* + * Binman error cases: address of the end of the previous region or the + * start of the image's entry area (usually 0) if there is no previous + * region. + */ + if (u_boot_pos && u_boot_pos != BINMAN_SYM_MISSING) { + /* Binman does not support separated entry addresses */ spl_image->entry_point = u_boot_pos; spl_image->load_addr = u_boot_pos; } else { From f3aff376892a5af55a090d29e53e10391f886d80 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:44 +0100 Subject: [PATCH 02/31] mtd: nand: sunxi: fix ECC strength choice When the requested ECC strength does not exactly match the strengths supported by the ECC engine, the driver is selecting the closest strength meeting the 'selected_strength > requested_strength' constraint. Fix the fact that, in this particular case, ecc->strength value was not updated to match the 'selected_strength'. For instance, one can encounter this issue when no ECC requirement is filled in the device tree while the NAND chip minimum requirement is not a strength/step_size combo natively supported by the ECC engine. Suggested-by: Boris Brezillon Signed-off-by: Miquel Raynal Acked-by: Boris Brezillon Signed-off-by: Maxime Ripard --- drivers/mtd/nand/sunxi_nand.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c index 532e03c..37160aa 100644 --- a/drivers/mtd/nand/sunxi_nand.c +++ b/drivers/mtd/nand/sunxi_nand.c @@ -1407,8 +1407,14 @@ static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd, /* Add ECC info retrieval from DT */ for (i = 0; i < ARRAY_SIZE(strengths); i++) { - if (ecc->strength <= strengths[i]) + if (ecc->strength <= strengths[i]) { + /* + * Update ecc->strength value with the actual strength + * that will be used by the ECC engine. + */ + ecc->strength = strengths[i]; break; + } } if (i >= ARRAY_SIZE(strengths)) { From a0a984e14a41bf07f6b3f563a2a8bd22c03aea3a Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:45 +0100 Subject: [PATCH 03/31] spl: nand: sunxi: fix second case of modulo by zero error In the nand_read_buffer() step, the seed is calculated by doing a modulo by conf->nseeds which is always zero when not using the randomizer (most of SLC NANDs). This situation turns out to lead to a run time freeze with certain toolchains. Derive this seed only when the randomizer is enabled (and conf->nseeds logically not zero), exactly like what has been done before with an identical situation, see commit ea3f750c73e3 ("nand: sunxi: Fix modulo by zero error"). Signed-off-by: Miquel Raynal Acked-by: Boris Brezillon Signed-off-by: Maxime Ripard --- drivers/mtd/nand/sunxi_nand_spl.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index eed4472..06695fc 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -475,11 +475,12 @@ static int nand_detect_config(struct nfc_config *conf, u32 offs, void *dest) static int nand_read_buffer(struct nfc_config *conf, uint32_t offs, unsigned int size, void *dest) { - int first_seed, page, ret; + int first_seed = 0, page, ret; size = ALIGN(size, conf->page_size); page = offs / conf->page_size; - first_seed = page % conf->nseeds; + if (conf->randomize) + first_seed = page % conf->nseeds; for (; size; size -= conf->page_size) { if (nand_load_page(conf, offs)) From 802f766994ded5afc9d89e93556011063a430e0d Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:46 +0100 Subject: [PATCH 04/31] spl: nand: sunxi: fix typo on register name Change NFC_SEND_ADR to NFC_SEND_ADDR. Signed-off-by: Miquel Raynal Acked-by: Boris Brezillon Signed-off-by: Maxime Ripard --- drivers/mtd/nand/sunxi_nand_spl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index 06695fc..608cc99 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -55,7 +55,7 @@ #define NFC_ADDR_NUM_OFFSET 16 -#define NFC_SEND_ADR (1 << 19) +#define NFC_SEND_ADDR (1 << 19) #define NFC_ACCESS_DIR (1 << 20) #define NFC_DATA_TRANS (1 << 21) #define NFC_SEND_CMD1 (1 << 22) @@ -208,7 +208,7 @@ static int nand_load_page(const struct nfc_config *conf, u32 offs) writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH); writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST); writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | NFC_WAIT_FLAG | - ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADR, + ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR, SUNXI_NFC_BASE + NFC_CMD); if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG, @@ -228,7 +228,7 @@ static int nand_reset_column(void) SUNXI_NFC_BASE + NFC_RCMD_SET); writel(0, SUNXI_NFC_BASE + NFC_ADDR_LOW); writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | - (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADR | NFC_CMD_RNDOUT, + (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR | NFC_CMD_RNDOUT, SUNXI_NFC_BASE + NFC_CMD); if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG, From 28f7a9d375c8bc7a30563b8d995b9baa355c7e41 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:47 +0100 Subject: [PATCH 05/31] spl: nand: sunxi: introduce the nand_wait_int() helper The pattern of polling on a status register until a bit is set or a timeout occurs is repeated multiple times in the driver. Mutualize the code by introducing the nand_wait_int() helper that does wait for the bit to flip or returns an error in case of timeout. Signed-off-by: Miquel Raynal Acked-by: Boris Brezillon Signed-off-by: Maxime Ripard --- drivers/mtd/nand/sunxi_nand_spl.c | 34 ++++++++++++++-------------------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index 608cc99..c2f4f2c 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -155,6 +155,17 @@ static inline int check_value_negated(int offset, int unexpected_bits, return check_value_inner(offset, unexpected_bits, timeout_us, 1); } +static int nand_wait_int(void) +{ + if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG, + DEFAULT_TIMEOUT_US)) { + printf("nand: timeout waiting for interruption\n"); + return -ETIMEDOUT; + } + + return 0; +} + void nand_init(void) { uint32_t val; @@ -176,12 +187,7 @@ void nand_init(void) writel(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET, SUNXI_NFC_BASE + NFC_CMD); - if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG, - DEFAULT_TIMEOUT_US)) { - printf("Error timeout waiting for nand reset\n"); - return; - } - writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST); + nand_wait_int(); } static void nand_apply_config(const struct nfc_config *conf) @@ -211,13 +217,7 @@ static int nand_load_page(const struct nfc_config *conf, u32 offs) ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR, SUNXI_NFC_BASE + NFC_CMD); - if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG, - DEFAULT_TIMEOUT_US)) { - printf("Error while initializing dma interrupt\n"); - return -EIO; - } - - return 0; + return nand_wait_int(); } static int nand_reset_column(void) @@ -231,13 +231,7 @@ static int nand_reset_column(void) (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR | NFC_CMD_RNDOUT, SUNXI_NFC_BASE + NFC_CMD); - if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG, - DEFAULT_TIMEOUT_US)) { - printf("Error while initializing dma interrupt\n"); - return -1; - } - - return 0; + return nand_wait_int(); } static int nand_read_page(const struct nfc_config *conf, u32 offs, From 60fb17913354757d015ade2b5457675a0506903a Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:48 +0100 Subject: [PATCH 06/31] spl: nand: sunxi: introduce the nand_wait_cmd_fifo_empty() helper One bit in the control registers indicates if the NAND controller is ready to receive a new command. Otherwise, the command FIFO is full and we should wait for this bit to flip. It then states that the last command has been processed and the FIFO is now free to welcome another command. Add this sanity check before starting any new command. Signed-off-by: Miquel Raynal Acked-by: Boris Brezillon Signed-off-by: Maxime Ripard --- drivers/mtd/nand/sunxi_nand_spl.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index c2f4f2c..cd823cd 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -155,6 +155,17 @@ static inline int check_value_negated(int offset, int unexpected_bits, return check_value_inner(offset, unexpected_bits, timeout_us, 1); } +static int nand_wait_cmd_fifo_empty(void) +{ + if (!check_value_negated(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_FIFO_STAT, + DEFAULT_TIMEOUT_US)) { + printf("nand: timeout waiting for empty cmd FIFO\n"); + return -ETIMEDOUT; + } + + return 0; +} + static int nand_wait_int(void) { if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG, @@ -183,6 +194,8 @@ void nand_init(void) } /* reset NAND */ + nand_wait_cmd_fifo_empty(); + writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST); writel(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET, SUNXI_NFC_BASE + NFC_CMD); @@ -194,6 +207,8 @@ static void nand_apply_config(const struct nfc_config *conf) { u32 val; + nand_wait_cmd_fifo_empty(); + val = readl(SUNXI_NFC_BASE + NFC_CTL); val &= ~NFC_CTL_PAGE_SIZE_MASK; writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size), @@ -206,6 +221,8 @@ static int nand_load_page(const struct nfc_config *conf, u32 offs) { int page = offs / conf->page_size; + nand_wait_cmd_fifo_empty(); + writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) | (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) | (NFC_CMD_READSTART << NFC_READ_CMD_OFFSET), @@ -222,6 +239,8 @@ static int nand_load_page(const struct nfc_config *conf, u32 offs) static int nand_reset_column(void) { + nand_wait_cmd_fifo_empty(); + writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) | (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) | (NFC_CMD_RNDOUTSTART << NFC_READ_CMD_OFFSET), From 781e70cff12916ae6698cc77a22e0ce687f39e3b Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:49 +0100 Subject: [PATCH 07/31] spl: nand: sunxi: add missing status clear It is best practice to always clear the status register before executing a command to be sure that the status read afterwards is relevant. Signed-off-by: Miquel Raynal Acked-by: Boris Brezillon Signed-off-by: Maxime Ripard --- drivers/mtd/nand/sunxi_nand_spl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index cd823cd..913de7d 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -245,6 +245,7 @@ static int nand_reset_column(void) (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) | (NFC_CMD_RNDOUTSTART << NFC_READ_CMD_OFFSET), SUNXI_NFC_BASE + NFC_RCMD_SET); + writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST); writel(0, SUNXI_NFC_BASE + NFC_ADDR_LOW); writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR | NFC_CMD_RNDOUT, From a084cb6664e0de40f33da1c8ec6de816a9852f6d Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:50 +0100 Subject: [PATCH 08/31] spl: nand: sunxi: create an helper to handle command execution Executing a command is matter of always doing the following sequence: * Waiting for the FIFO to be empty so we can fill it with the new command. * Clearing the status register. * Writing the command in the FIFO. * Waiting for the command to finish. Add a nand_exec_cmd() helper to handle this instead of repeating the logic through the various functions. Signed-off-by: Miquel Raynal Acked-by: Boris Brezillon Signed-off-by: Maxime Ripard --- drivers/mtd/nand/sunxi_nand_spl.c | 42 +++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index 913de7d..25a0941 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -177,6 +177,20 @@ static int nand_wait_int(void) return 0; } +static int nand_exec_cmd(u32 cmd) +{ + int ret; + + ret = nand_wait_cmd_fifo_empty(); + if (ret) + return ret; + + writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST); + writel(cmd, SUNXI_NFC_BASE + NFC_CMD); + + return nand_wait_int(); +} + void nand_init(void) { uint32_t val; @@ -194,13 +208,7 @@ void nand_init(void) } /* reset NAND */ - nand_wait_cmd_fifo_empty(); - - writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST); - writel(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET, - SUNXI_NFC_BASE + NFC_CMD); - - nand_wait_int(); + nand_exec_cmd(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET); } static void nand_apply_config(const struct nfc_config *conf) @@ -221,37 +229,29 @@ static int nand_load_page(const struct nfc_config *conf, u32 offs) { int page = offs / conf->page_size; - nand_wait_cmd_fifo_empty(); - writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) | (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) | (NFC_CMD_READSTART << NFC_READ_CMD_OFFSET), SUNXI_NFC_BASE + NFC_RCMD_SET); writel(((page & 0xFFFF) << 16), SUNXI_NFC_BASE + NFC_ADDR_LOW); writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH); - writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST); - writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | NFC_WAIT_FLAG | - ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR, - SUNXI_NFC_BASE + NFC_CMD); - return nand_wait_int(); + return nand_exec_cmd(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | + NFC_SEND_ADDR | NFC_WAIT_FLAG | + ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET)); } static int nand_reset_column(void) { - nand_wait_cmd_fifo_empty(); - writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) | (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) | (NFC_CMD_RNDOUTSTART << NFC_READ_CMD_OFFSET), SUNXI_NFC_BASE + NFC_RCMD_SET); - writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST); writel(0, SUNXI_NFC_BASE + NFC_ADDR_LOW); - writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | - (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR | NFC_CMD_RNDOUT, - SUNXI_NFC_BASE + NFC_CMD); - return nand_wait_int(); + return nand_exec_cmd(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | + (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR | + NFC_CMD_RNDOUT); } static int nand_read_page(const struct nfc_config *conf, u32 offs, From 4dac80a5e991dd3b5b99910d7927edfdf4c99bb3 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:51 +0100 Subject: [PATCH 09/31] spl: nand: sunxi: ensure enough time has passed after changing the column When changing the column, the ONFI specification states that a minimum time of tCCS (Change Column Setup time) must elapse between the last address cycle is asserted on the bus and the first data cycle is clocked. An usual value for average NANDs is 500 nanoseconds. Round it up to 1 microsecond to be safe. Signed-off-by: Miquel Raynal Acked-by: Boris Brezillon Signed-off-by: Maxime Ripard --- drivers/mtd/nand/sunxi_nand_spl.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index 25a0941..d63aa97 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -243,15 +243,24 @@ static int nand_load_page(const struct nfc_config *conf, u32 offs) static int nand_reset_column(void) { + int ret; + writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) | (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) | (NFC_CMD_RNDOUTSTART << NFC_READ_CMD_OFFSET), SUNXI_NFC_BASE + NFC_RCMD_SET); writel(0, SUNXI_NFC_BASE + NFC_ADDR_LOW); - return nand_exec_cmd(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | - (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR | - NFC_CMD_RNDOUT); + ret = nand_exec_cmd(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | + (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR | + NFC_CMD_RNDOUT); + if (ret) + return ret; + + /* Ensure tCCS has passed before reading data */ + udelay(1); + + return 0; } static int nand_read_page(const struct nfc_config *conf, u32 offs, From 22f0aa0528a48cb9eb72abb065071e47c4215af9 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:52 +0100 Subject: [PATCH 10/31] spl: nand: sunxi: make the reset column helper more generic Prepare the future use of an helper to move the data pointer (the column) of the NAND chip by renaming nand_reset_column() to nand_change_column(). Resetting the column is just a matter of giving 0 as argument. Signed-off-by: Miquel Raynal Acked-by: Boris Brezillon Signed-off-by: Maxime Ripard --- drivers/mtd/nand/sunxi_nand_spl.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index d63aa97..9ebdcee 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -241,7 +241,7 @@ static int nand_load_page(const struct nfc_config *conf, u32 offs) ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET)); } -static int nand_reset_column(void) +static int nand_change_column(u16 column) { int ret; @@ -249,7 +249,7 @@ static int nand_reset_column(void) (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) | (NFC_CMD_RNDOUTSTART << NFC_READ_CMD_OFFSET), SUNXI_NFC_BASE + NFC_RCMD_SET); - writel(0, SUNXI_NFC_BASE + NFC_ADDR_LOW); + writel(column, SUNXI_NFC_BASE + NFC_ADDR_LOW); ret = nand_exec_cmd(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR | @@ -416,7 +416,7 @@ static int nand_detect_ecc_config(struct nfc_config *conf, u32 offs, conf->ecc_strength >= 0; conf->ecc_strength--) { conf->randomize = false; - if (nand_reset_column()) + if (nand_change_column(0)) return -EIO; /* @@ -436,7 +436,7 @@ static int nand_detect_ecc_config(struct nfc_config *conf, u32 offs, conf->randomize = true; conf->nseeds = ARRAY_SIZE(random_seed); do { - if (nand_reset_column()) + if (nand_change_column(0)) return -EIO; if (!nand_read_page(conf, offs, dest, @@ -528,7 +528,7 @@ static int nand_read_buffer(struct nfc_config *conf, uint32_t offs, /* Try to adjust ->nseeds and read the page again... */ conf->nseeds = cur_seed; - if (nand_reset_column()) + if (nand_change_column(0)) return -EIO; /* ... it still fails => it's a real corruption. */ From ba1c98bae2649e990c6af04545e422042cb58b27 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:53 +0100 Subject: [PATCH 11/31] sunxi: spl: deassert the NAND controller reset line Ensure the NAND controller reset line is deasserted before use. Signed-off-by: Miquel Raynal Signed-off-by: Maxime Ripard --- board/sunxi/board.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index e08e22f..ee3bfda 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -286,6 +286,10 @@ static void nand_clock_setup(void) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \ + defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I + setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); +#endif #ifdef CONFIG_MACH_SUN9I setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); #else From 7440bd7885da984dc20e2e8c8a0b167911e9dce1 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:54 +0100 Subject: [PATCH 12/31] spl: nand: sunxi: declare the ecc_bytes array globally Move the ecc_bytes array out of nand_max_ecc_strength() for future use by nand_read_page(). Signed-off-by: Miquel Raynal Acked-by: Boris Brezillon Signed-off-by: Maxime Ripard --- drivers/mtd/nand/sunxi_nand_spl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index 9ebdcee..af1e964 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -263,6 +263,8 @@ static int nand_change_column(u16 column) return 0; } +static const int ecc_bytes[] = {32, 46, 54, 60, 74, 88, 102, 110, 116}; + static int nand_read_page(const struct nfc_config *conf, u32 offs, void *dest, int len) { @@ -350,7 +352,6 @@ static int nand_read_page(const struct nfc_config *conf, u32 offs, static int nand_max_ecc_strength(struct nfc_config *conf) { - static const int ecc_bytes[] = { 32, 46, 54, 60, 74, 88, 102, 110, 116 }; int max_oobsize, max_ecc_bytes; int nsectors = conf->page_size / conf->ecc_size; int i; From 6ddbb1e936c78cdef1e7395039fa7020c5c75326 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:55 +0100 Subject: [PATCH 13/31] spl: nand: sunxi: use PIO instead of DMA SPL support was first written to support only the earlier generations of Allwinner SoCs, and was only really enabled on the A13 / GR8. However, those old SoCs had a DMA engine that has been replaced since the A31 by another DMA controller that is no longer compatible. Since the code directly uses that DMA controller, it cannot operate properly on the later SoCs, while the NAND controller has not changed. There's two paths forward, the first one would have been to add support for that DMA controller too, the second to just remove the DMA usage entirely and rely on PIO. The later has been chosen because CPU overload at this stage is not an issue and it makes the driver more generic, and easier to understand. Signed-off-by: Miquel Raynal Acked-by: Boris Brezillon Signed-off-by: Maxime Ripard --- drivers/mtd/nand/sunxi_nand_spl.c | 135 ++++++++++++++++---------------------- 1 file changed, 55 insertions(+), 80 deletions(-) diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index af1e964..7241e9a 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -10,6 +10,7 @@ #include #include #include +#include /* registers */ #define NFC_CTL 0x00000000 @@ -67,10 +68,12 @@ #define NFC_SEND_CMD3 (1 << 28) #define NFC_SEND_CMD4 (1 << 29) #define NFC_RAW_CMD (0 << 30) +#define NFC_ECC_CMD (1 << 30) #define NFC_PAGE_CMD (2 << 30) #define NFC_ST_CMD_INT_FLAG (1 << 1) #define NFC_ST_DMA_INT_FLAG (1 << 2) +#define NFC_ST_CMD_FIFO_STAT (1 << 3) #define NFC_READ_CMD_OFFSET 0 #define NFC_RANDOM_READ_CMD0_OFFSET 8 @@ -80,22 +83,6 @@ #define NFC_CMD_RNDOUT 0x05 #define NFC_CMD_READSTART 0x30 -#define SUNXI_DMA_CFG_REG0 0x300 -#define SUNXI_DMA_SRC_START_ADDR_REG0 0x304 -#define SUNXI_DMA_DEST_START_ADDRR_REG0 0x308 -#define SUNXI_DMA_DDMA_BC_REG0 0x30C -#define SUNXI_DMA_DDMA_PARA_REG0 0x318 - -#define SUNXI_DMA_DDMA_CFG_REG_LOADING (1 << 31) -#define SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 (2 << 25) -#define SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM (1 << 16) -#define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 (2 << 9) -#define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO (1 << 5) -#define SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC (3 << 0) - -#define SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC (0x0F << 0) -#define SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE (0x7F << 8) - struct nfc_config { int page_size; int ecc_strength; @@ -268,86 +255,74 @@ static const int ecc_bytes[] = {32, 46, 54, 60, 74, 88, 102, 110, 116}; static int nand_read_page(const struct nfc_config *conf, u32 offs, void *dest, int len) { - dma_addr_t dst = (dma_addr_t)dest; int nsectors = len / conf->ecc_size; u16 rand_seed = 0; - u32 val; - int page; - - page = offs / conf->page_size; + int oob_chunk_sz = ecc_bytes[conf->ecc_strength]; + int page = offs / conf->page_size; + u32 ecc_st; + int i; if (offs % conf->page_size || len % conf->ecc_size || len > conf->page_size || len < 0) return -EINVAL; - /* clear ecc status */ - writel(0, SUNXI_NFC_BASE + NFC_ECC_ST); - /* Choose correct seed if randomized */ if (conf->randomize) rand_seed = random_seed[page % conf->nseeds]; - writel((rand_seed << 16) | (conf->ecc_strength << 12) | - (conf->randomize ? NFC_ECC_RANDOM_EN : 0) | - (conf->ecc_size == 512 ? NFC_ECC_BLOCK_SIZE : 0) | - NFC_ECC_EN | NFC_ECC_PIPELINE | NFC_ECC_EXCEPTION, - SUNXI_NFC_BASE + NFC_ECC_CTL); - - flush_dcache_range(dst, ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN)); - - /* SUNXI_DMA */ - writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */ - /* read from REG_IO_DATA */ - writel(SUNXI_NFC_BASE + NFC_IO_DATA, - SUNXI_DMA_BASE + SUNXI_DMA_SRC_START_ADDR_REG0); - /* read to RAM */ - writel(dst, SUNXI_DMA_BASE + SUNXI_DMA_DEST_START_ADDRR_REG0); - writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC | - SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE, - SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0); - writel(len, SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0); - writel(SUNXI_DMA_DDMA_CFG_REG_LOADING | - SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 | - SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM | - SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 | - SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO | - SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC, - SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); - - writel(nsectors, SUNXI_NFC_BASE + NFC_SECTOR_NUM); - writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST); - writel(NFC_DATA_TRANS | NFC_PAGE_CMD | NFC_DATA_SWAP_METHOD, - SUNXI_NFC_BASE + NFC_CMD); - - if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_DMA_INT_FLAG, - DEFAULT_TIMEOUT_US)) { - printf("Error while initializing dma interrupt\n"); - return -EIO; - } - writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST); + /* Retrieve data from SRAM (PIO) */ + for (i = 0; i < nsectors; i++) { + int data_off = i * conf->ecc_size; + int oob_off = conf->page_size + (i * oob_chunk_sz); + u8 *data = dest + data_off; + + /* Clear ECC status and restart ECC engine */ + writel(0, SUNXI_NFC_BASE + NFC_ECC_ST); + writel((rand_seed << 16) | (conf->ecc_strength << 12) | + (conf->randomize ? NFC_ECC_RANDOM_EN : 0) | + (conf->ecc_size == 512 ? NFC_ECC_BLOCK_SIZE : 0) | + NFC_ECC_EN | NFC_ECC_EXCEPTION, + SUNXI_NFC_BASE + NFC_ECC_CTL); + + /* Move the data in SRAM */ + nand_change_column(data_off); + writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT); + nand_exec_cmd(NFC_DATA_TRANS); - if (!check_value_negated(SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0, - SUNXI_DMA_DDMA_CFG_REG_LOADING, - DEFAULT_TIMEOUT_US)) { - printf("Error while waiting for dma transfer to finish\n"); - return -EIO; - } + /* + * Let the ECC engine consume the ECC bytes and possibly correct + * the data. + */ + nand_change_column(oob_off); + nand_exec_cmd(NFC_DATA_TRANS | NFC_ECC_CMD); - invalidate_dcache_range(dst, - ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN)); + /* Get the ECC status */ + ecc_st = readl(SUNXI_NFC_BASE + NFC_ECC_ST); - val = readl(SUNXI_NFC_BASE + NFC_ECC_ST); + /* ECC error detected. */ + if (ecc_st & 0xffff) + return -EIO; - /* ECC error detected. */ - if (val & 0xffff) - return -EIO; + /* + * Return 1 if the first chunk is empty (needed for + * configuration detection). + */ + if (!i && (ecc_st & 0x10000)) + return 1; - /* - * Return 1 if the page is empty. - * We consider the page as empty if the first ECC block is marked - * empty. - */ - return (val & 0x10000) ? 1 : 0; + /* Retrieve the data from SRAM */ + memcpy_fromio(data, SUNXI_NFC_BASE + NFC_RAM0_BASE, + conf->ecc_size); + + /* Stop the ECC engine */ + writel(readl(SUNXI_NFC_BASE + NFC_ECC_CTL) & ~NFC_ECC_EN, + SUNXI_NFC_BASE + NFC_ECC_CTL); + + if (data_off + conf->ecc_size >= len) + break; + } + + return 0; } static int nand_max_ecc_strength(struct nfc_config *conf) From 136e32593335e031558a573158b6180fc80b551f Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:56 +0100 Subject: [PATCH 14/31] sunxi: spl: remove DMA related settings of the NAND controller Code has been changed to do not use DMA anymore with the NAND controller, instead PIO is used. Then, DMA-specific initialization may be dropped. Signed-off-by: Miquel Raynal Signed-off-by: Maxime Ripard --- board/sunxi/board.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index ee3bfda..322dd9e 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -290,11 +290,6 @@ static void nand_clock_setup(void) defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); #endif -#ifdef CONFIG_MACH_SUN9I - setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); -#else - setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); -#endif setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); } From 663e8a9b54ccbc9b939e4e3696a84fdf2f5a43fc Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:57 +0100 Subject: [PATCH 15/31] sunxi: allow NAND support to be compiled for sun8i platforms Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I in Kconfig. Signed-off-by: Miquel Raynal Signed-off-by: Maxime Ripard --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 6 ++++++ drivers/mtd/nand/Kconfig | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index d328df9..d35aa47 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -192,6 +192,7 @@ struct sunxi_ccm_reg { #define ATB_DIV_1 0 #define ATB_DIV_2 1 #define ATB_DIV_4 2 +#define AHB_DIV_1 0 #define CPU_CLK_SRC_OSC24M 1 #define CPU_CLK_SRC_PLL1 2 @@ -317,6 +318,11 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_LCD0 3 #endif +#define CCM_NAND_CTRL_M(x) ((x) - 1) +#define CCM_NAND_CTRL_N(x) ((x) << 16) +#define CCM_NAND_CTRL_PLL6 (0x1 << 24) +#define CCM_NAND_CTRL_ENABLE (0x1 << 31) + #define CCM_MMC_CTRL_M(x) ((x) - 1) #define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) #define CCM_MMC_CTRL_N(x) ((x) << 16) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index a820af6..dcb8ff6 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -95,7 +95,7 @@ config NAND_PXA3XX config NAND_SUNXI bool "Support for NAND on Allwinner SoCs" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I select SYS_NAND_SELF_INIT select SYS_NAND_U_BOOT_LOCATIONS imply CMD_NAND From 491feffa88f403a791c71ec8dd1b2c5943c83d61 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:58 +0100 Subject: [PATCH 16/31] sunxi: dts: enable NAND on NES classic Let the Nintendo NES Classic use the Macronix NAND chip on it. Signed-off-by: Miquel Raynal Signed-off-by: Maxime Ripard --- arch/arm/dts/sun8i-a23-a33.dtsi | 17 +++++++++++++++++ arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts | 14 ++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi index ea50dda..ffd2148 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -289,6 +289,23 @@ function = "uart1"; }; + nand_pins_a: nand-base0@0 { + pins = "PC0", "PC1", "PC2", "PC5", + "PC8", "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", "PC15"; + function = "nand0"; + }; + + nand_cs0_pins_a: nand-cs@0 { + pins = "PC4"; + function = "nand0"; + }; + + nand_rb0_pins_a: nand-rb@0 { + pins = "PC6"; + function = "nand0"; + }; + mmc0_pins_a: mmc0@0 { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; diff --git a/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts b/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts index dce688e..72a8505 100644 --- a/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts +++ b/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts @@ -61,3 +61,17 @@ pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; + status = "okay"; + + nand@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + allwinner,rb = <0>; + nand-ecc-mode = "hw"; + }; +}; From 6d094d535c121637775b5108f1e78e426017f757 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:51:59 +0100 Subject: [PATCH 17/31] sunxi: automatically select SPL_NAND_SUPPORT in Kconfig Make SUNXI_NAND select SPL_NAND_SUPPORT in Kconfig, this limit the number of entries to add in defconfig files when adding NAND support. For now, the only board using it is the CHIP pro. Signed-off-by: Miquel Raynal Acked-by: Maxime Ripard Signed-off-by: Maxime Ripard --- configs/CHIP_pro_defconfig | 1 - drivers/mtd/nand/Kconfig | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 60dcaa7..a969fc0 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_SPL_NAND_SUPPORT=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index dcb8ff6..75eefc8 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -98,6 +98,7 @@ config NAND_SUNXI depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I select SYS_NAND_SELF_INIT select SYS_NAND_U_BOOT_LOCATIONS + select SPL_NAND_SUPPORT imply CMD_NAND ---help--- Enable support for NAND. This option enables the standard and From b56052f4ca40d0d8b29fb7bd3be4c104618e4fc8 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:52:00 +0100 Subject: [PATCH 18/31] sunxi: make NAND_SUNXI use ARCH_SUNXI as default in Kconfig Remove NAND_SUNXI from the CHIP pro defconfig to be automatically selected depending on the state of ARCH_SUNXI. Signed-off-by: Miquel Raynal Acked-by: Maxime Ripard Signed-off-by: Maxime Ripard --- configs/CHIP_pro_defconfig | 1 - drivers/mtd/nand/Kconfig | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index a969fc0..9235e34 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -15,7 +15,6 @@ CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot-env" # CONFIG_MMC is not set CONFIG_NAND=y -CONFIG_NAND_SUNXI=y CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 CONFIG_CONS_INDEX=2 diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 75eefc8..cf323c5 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -95,6 +95,7 @@ config NAND_PXA3XX config NAND_SUNXI bool "Support for NAND on Allwinner SoCs" + default ARCH_SUNXI depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I select SYS_NAND_SELF_INIT select SYS_NAND_U_BOOT_LOCATIONS From 748b5b34d3d0e67923cac5f8606b7a209e063df6 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:52:01 +0100 Subject: [PATCH 19/31] sunxi: move the NAND parameters to Kconfig Move the NAND parameters from defconfig files to Kconfig for SUNXI architecture only. Fort now only the CHIP pro is migrated. It would have been better to convert this defconfig entry to Kconfig for all supported machines/architectures but it has been abandoned due to a fairly high amount of errors reported by the moveconfig.py tool. This is due to defines quite often being multiplications of values/other defines not correctly handled. Signed-off-by: Miquel Raynal Acked-by: Maxime Ripard Signed-off-by: Maxime Ripard --- configs/CHIP_pro_defconfig | 4 +++- drivers/mtd/nand/Kconfig | 22 ++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 9235e34..faaee83 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -4,7 +4,9 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" CONFIG_DEFAULT_DEVICE_TREE="sun5i-gr8-chip-pro" -CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCK_SIZE=0x40000,SYS_NAND_PAGE_SIZE=4096,SYS_NAND_OOBSIZE=256" +CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 +CONFIG_SYS_NAND_OOBSIZE=0x1000 +CONFIG_SYS_NAND_OOBSIZE=0x100 CONFIG_SPL=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index cf323c5..94fbf89 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -168,6 +168,28 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS comment "Generic NAND options" +config SYS_NAND_BLOCK_SIZE + hex "NAND chip eraseblock size" + depends on ARCH_SUNXI + help + Number of data bytes in one eraseblock for the NAND chip on the + board. This is the multiple of NAND_PAGE_SIZE and the number of + pages. + +config SYS_NAND_PAGE_SIZE + hex "NAND chip page size" + depends on ARCH_SUNXI + help + Number of data bytes in one page for the NAND chip on the + board, not including the OOB area. + +config SYS_NAND_OOBSIZE + hex "NAND chip OOB size" + depends on ARCH_SUNXI + help + Number of bytes in the Out-Of-Band area for the NAND chip on + the board. + # Enhance depends when converting drivers to Kconfig which use this config # option (mxc_nand, ndfc, omap_gpmc). config SYS_NAND_BUSWIDTH_16BIT From e71553fe7572c32f1d10717c0094c47064a2ef87 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 28 Feb 2018 20:52:02 +0100 Subject: [PATCH 20/31] configs: add NAND support for NES Classic Add NAND parameters to the Nintendo NES Classic configuration file which features a Macronix NAND flash chip with 128kiB blocks of 2kiB pages plus 64 OOB bytes. Signed-off-by: Miquel Raynal Acked-by: Maxime Ripard Signed-off-by: Maxime Ripard --- configs/Nintendo_NES_Classic_Edition_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig index 31d38af..62bee97 100644 --- a/configs/Nintendo_NES_Classic_Edition_defconfig +++ b/configs/Nintendo_NES_Classic_Edition_defconfig @@ -9,6 +9,10 @@ CONFIG_AXP_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_NAND=y +CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 +CONFIG_SYS_NAND_PAGE_SIZE=0x800 +CONFIG_SYS_NAND_OOBSIZE=0x40 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_ISO_PARTITION is not set From 35debf8a4585469f5eb192f1d779a4cff69087bb Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 4 Apr 2018 01:31:13 +0100 Subject: [PATCH 21/31] sunxi: README.sunxi64: Add hint about non-debug of ARM Trusted Firmware As we are running into issues where the final U-Boot FIT image file is exceeding our size limit, add a hint to the README.sunxi64 file to point out the possibility of building non-debug versions of the ATF binary. These are about 12KB smaller than the standard debug build, and so allow successful U-Boot builds for many boards with the Allwinner H5 SoC. Please note that under normal circumstances the debug build is still recommended, as it gives valuable clues in case something goes wrong in the ATF. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- board/sunxi/README.sunxi64 | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/sunxi/README.sunxi64 b/board/sunxi/README.sunxi64 index 5a363d2..df1dbc8 100644 --- a/board/sunxi/README.sunxi64 +++ b/board/sunxi/README.sunxi64 @@ -38,6 +38,12 @@ the root of your U-Boot build directory (or create a symbolic link). $ export BL31=/src/arm-trusted-firmware/build/sun50iw1p1/debug/bl31.bin (adjust the actual path accordingly) +If you run into size issues with the resulting U-Boot image file, it might +help to use a release build, by using "DEBUG=0" when building bl31.bin. +As sometimes the ATF build process is a bit picky about the toolchain used, +or if you can't be bothered with building ATF, there are known working +binaries in the firmware repository[3], purely for convenience reasons. + SPL/U-Boot ------------ Both U-Boot proper and the SPL are using the 64-bit mode. As the boot ROM From 381996c5edaf9d63fe93a12eb84aa260d1f9500f Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 4 Apr 2018 01:31:14 +0100 Subject: [PATCH 22/31] sunxi: gpio: add missing compatible strings The sunxi GPIO driver is missing some compatible strings for recent SoCs. While most of the sunxi GPIO code seems to not rely on this (and so works anyway), the sunxi_name_to_gpio() function does and fails at the moment (for instance when resolving the MMC CD pin name). Add the compatible strings for the A64 and V3s, which were missing from the list. This now covers all pinctrl nodes in our own DTs. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- drivers/gpio/sunxi_gpio.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 3cf01b6..ea6f359 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -354,12 +354,15 @@ static const struct udevice_id sunxi_gpio_ids[] = { ID("allwinner,sun8i-a83t-pinctrl", a_all), ID("allwinner,sun8i-h3-pinctrl", a_all), ID("allwinner,sun8i-r40-pinctrl", a_all), + ID("allwinner,sun8i-v3s-pinctrl", a_all), ID("allwinner,sun9i-a80-pinctrl", a_all), + ID("allwinner,sun50i-a64-pinctrl", a_all), ID("allwinner,sun6i-a31-r-pinctrl", l_2), ID("allwinner,sun8i-a23-r-pinctrl", l_1), ID("allwinner,sun8i-a83t-r-pinctrl", l_1), ID("allwinner,sun8i-h3-r-pinctrl", l_1), ID("allwinner,sun9i-a80-r-pinctrl", l_3), + ID("allwinner,sun50i-a64-r-pinctrl", l_1), { } }; From c03411730215dadec9e4c2edcb8119e85bc4a406 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 4 Apr 2018 01:31:15 +0100 Subject: [PATCH 23/31] net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- drivers/net/sun8i_emac.c | 52 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 39 insertions(+), 13 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index be43472..c8c8ef7 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -21,6 +21,7 @@ #include #include #include +#include #ifdef CONFIG_DM_GPIO #include #endif @@ -465,30 +466,55 @@ static int parse_phy_pins(struct udevice *dev) } drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, - "allwinner,drive", 4); - pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, - "allwinner,pull", 0); + "drive-strength", ~0); + if (drive != ~0) { + if (drive <= 10) + drive = SUN4I_PINCTRL_10_MA; + else if (drive <= 20) + drive = SUN4I_PINCTRL_20_MA; + else if (drive <= 30) + drive = SUN4I_PINCTRL_30_MA; + else + drive = SUN4I_PINCTRL_40_MA; + } else { + drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, + "allwinner,drive", 4); + } + + if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL)) + pull = SUN4I_PINCTRL_PULL_UP; + else if (fdt_get_property(gd->fdt_blob, offset, "bias-disable", NULL)) + pull = SUN4I_PINCTRL_NO_PULL; + else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL)) + pull = SUN4I_PINCTRL_PULL_DOWN; + else + pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, + "allwinner,pull", 0); for (i = 0; ; i++) { int pin; pin_name = fdt_stringlist_get(gd->fdt_blob, offset, "allwinner,pins", i, NULL); - if (!pin_name) - break; - if (pin_name[0] != 'P') - continue; - pin = (pin_name[1] - 'A') << 5; - if (pin >= 26 << 5) + if (!pin_name) { + pin_name = fdt_stringlist_get(gd->fdt_blob, offset, + "pins", i, NULL); + if (!pin_name) + break; + } + + pin = sunxi_name_to_gpio(pin_name); + if (pin < 0) continue; - pin += simple_strtol(&pin_name[2], NULL, 10); sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC); - sunxi_gpio_set_drv(pin, drive); - sunxi_gpio_set_pull(pin, pull); + if (drive != ~0) + sunxi_gpio_set_drv(pin, drive); + if (pull != ~0) + sunxi_gpio_set_pull(pin, pull); } if (!i) { - printf("WARNING: emac: cannot find allwinner,pins property\n"); + printf("WARNING: emac: cannot find pins property\n"); return -2; } From 12afd95711b78fe59a1ba6a8e39ed7830d25be80 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 4 Apr 2018 01:31:16 +0100 Subject: [PATCH 24/31] net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- drivers/net/sun8i_emac.c | 59 +++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 51 insertions(+), 8 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index c8c8ef7..55d82f8 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -279,7 +279,7 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) int ret; u32 reg; - reg = readl(priv->sysctl_reg); + reg = readl(priv->sysctl_reg + 0x30); if (priv->variant == H3_EMAC) { ret = sun8i_emac_set_syscon_ephy(priv, ®); @@ -310,7 +310,7 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) return -EINVAL; } - writel(reg, priv->sysctl_reg); + writel(reg, priv->sysctl_reg + 0x30); return 0; } @@ -806,17 +806,52 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) #endif pdata->iobase = devfdt_get_addr_name(dev, "emac"); + if (pdata->iobase == FDT_ADDR_T_NONE) + pdata->iobase = devfdt_get_addr(dev); + if (pdata->iobase == FDT_ADDR_T_NONE) { + debug("%s: Cannot find MAC base address\n", __func__); + return -EINVAL; + } + priv->sysctl_reg = devfdt_get_addr_name(dev, "syscon"); + if (priv->sysctl_reg == FDT_ADDR_T_NONE) { + const fdt32_t *reg; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); + if (offset < 0) { + debug("%s: cannot find syscon node\n", __func__); + return -EINVAL; + } + reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL); + if (!reg) { + debug("%s: cannot find reg property in syscon node\n", + __func__); + return -EINVAL; + } + priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, + offset, reg); + } else { + priv->sysctl_reg -= 0x30; + } + + if (priv->sysctl_reg == FDT_ADDR_T_NONE) { + debug("%s: Cannot find syscon base address\n", __func__); + return -EINVAL; + } pdata->phy_interface = -1; priv->phyaddr = -1; priv->use_internal_phy = false; - offset = fdtdec_lookup_phandle(gd->fdt_blob, node, - "phy"); - if (offset > 0) - priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", - -1); + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy"); + if (offset < 0) + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, + "phy-handle"); + if (offset < 0) { + debug("%s: Cannot find PHY address\n", __func__); + return -EINVAL; + } + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); @@ -839,8 +874,16 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) if (priv->variant == H3_EMAC) { if (fdt_getprop(gd->fdt_blob, node, - "allwinner,use-internal-phy", NULL)) + "allwinner,use-internal-phy", NULL)) { priv->use_internal_phy = true; + } else { + int parent = fdt_parent_offset(gd->fdt_blob, offset); + + if (parent >= 0 && + !fdt_node_check_compatible(gd->fdt_blob, parent, + "allwinner,sun8i-h3-mdio-internal")) + priv->use_internal_phy = true; + } } priv->interface = pdata->phy_interface; From 06a57f656b606906d541426845a81d4de4aa491c Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 4 Apr 2018 01:31:17 +0100 Subject: [PATCH 25/31] arm: dts: sunxi: update A64 to new EMAC binding The U-Boot driver for the sun8i-emac was using some preliminary DT binding. Now since Linux got its own driver in v4.15 and our driver can now cope with both bindings, let's convert the DT nodes used for the Pine64+ board over to the new bindings used by the kernel. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi | 51 +++++++++++++++---------- 1 file changed, 30 insertions(+), 21 deletions(-) diff --git a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi index 9c61bea..32a263c 100644 --- a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi +++ b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi @@ -4,25 +4,38 @@ }; soc { - emac: ethernet@01c30000 { + syscon: syscon@1c00000 { + compatible = "allwinner,sun50i-a64-system-controller", + "syscon"; + reg = <0x01c00000 0x1000>; + }; + + emac: ethernet@1c30000 { compatible = "allwinner,sun50i-a64-emac"; - reg = <0x01c30000 0x2000>, <0x01c00030 0x4>; - reg-names = "emac", "syscon"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; interrupts = ; + interrupt-names = "macirq"; resets = <&ccu RST_BUS_EMAC>; - reset-names = "ahb"; + reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "ahb"; + clock-names = "stmmaceth"; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; phy-mode = "rgmii"; - phy = <&phy1>; + phy-handle = <&ext_rgmii_phy>; status = "okay"; - phy1: ethernet-phy@1 { - reg = <1>; + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; }; }; }; @@ -30,21 +43,17 @@ &pio { rmii_pins: rmii_pins { - allwinner,pins = "PD10", "PD11", "PD13", "PD14", - "PD17", "PD18", "PD19", "PD20", - "PD22", "PD23"; - allwinner,function = "emac"; - allwinner,drive = <3>; - allwinner,pull = <0>; + pins = "PD10", "PD11", "PD13", "PD14", "PD17", + "PD18", "PD19", "PD20", "PD22", "PD23"; + function = "emac"; + drive-strength = <40>; }; rgmii_pins: rgmii_pins { - allwinner,pins = "PD8", "PD9", "PD10", "PD11", - "PD12", "PD13", "PD15", - "PD16", "PD17", "PD18", "PD19", - "PD20", "PD21", "PD22", "PD23"; - allwinner,function = "emac"; - allwinner,drive = <3>; - allwinner,pull = <0>; + pins = "PD8", "PD9", "PD10", "PD11", "PD12", + "PD13", "PD15", "PD16", "PD17", "PD18", + "PD19", "PD20", "PD21", "PD22", "PD23"; + function = "emac"; + drive-strength = <40>; }; }; From e88d2a57f3a01c774471e32bf35d871682cfffe8 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 4 Apr 2018 01:31:18 +0100 Subject: [PATCH 26/31] arm: dts: sunxi: update H3 to new EMAC binding The U-Boot driver for the sun8i-emac was using some preliminary DT binding. Now since Linux got its own driver in v4.15 and our driver can now cope with both bindings, let's convert the DT nodes used by the various H3 boards over to the new bindings used by the kernel. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 6 +-- arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts | 7 +-- arch/arm/dts/sun8i-h3-nanopi-neo.dts | 6 +-- arch/arm/dts/sun8i-h3-orangepi-2.dts | 7 +-- arch/arm/dts/sun8i-h3-orangepi-one.dts | 7 +-- arch/arm/dts/sun8i-h3-orangepi-pc.dts | 7 +-- arch/arm/dts/sun8i-h3-orangepi-plus.dts | 8 +++- arch/arm/dts/sun8i-h3-orangepi-plus2e.dts | 9 +++- arch/arm/dts/sun8i-h3.dtsi | 69 ++++++++++++++++++++------- 9 files changed, 75 insertions(+), 51 deletions(-) diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts index 20d489c..e0efcb3 100644 --- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts @@ -100,14 +100,10 @@ }; &emac { - phy = <&phy1>; + phy-handle = <&int_mii_phy>; phy-mode = "mii"; - allwinner,use-internal-phy; allwinner,leds-active-low; status = "okay"; - phy1: ethernet-phy@1 { - reg = <1>; - }; }; &mmc0 { diff --git a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts index 97b993f..c8fd69f 100644 --- a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts +++ b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts @@ -125,15 +125,10 @@ }; &emac { - phy = <&phy1>; + phy-handle = <&int_mii_phy>; phy-mode = "mii"; - allwinner,use-internal-phy; allwinner,leds-active-low; status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; }; &ir { diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/dts/sun8i-h3-nanopi-neo.dts index 5113059..78f6c24 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-neo.dts @@ -48,12 +48,8 @@ }; &emac { - phy = <&phy1>; + phy-handle = <&int_mii_phy>; phy-mode = "mii"; - allwinner,use-internal-phy; allwinner,leds-active-low; status = "okay"; - phy1: ethernet-phy@1 { - reg = <1>; - }; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts index caa1a69..d97fdac 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts @@ -55,6 +55,7 @@ aliases { serial0 = &uart0; /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &rtl8189; }; @@ -110,14 +111,10 @@ }; &emac { - phy = <&phy1>; + phy-handle = <&int_mii_phy>; phy-mode = "mii"; - allwinner,use-internal-phy; allwinner,leds-active-low; status = "okay"; - phy1: ethernet-phy@1 { - reg = <1>; - }; }; &ir { diff --git a/arch/arm/dts/sun8i-h3-orangepi-one.dts b/arch/arm/dts/sun8i-h3-orangepi-one.dts index 8df5c74..adab1cb 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-one.dts @@ -53,6 +53,7 @@ compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -95,14 +96,10 @@ }; &emac { - phy = <&phy1>; + phy-handle = <&int_mii_phy>; phy-mode = "mii"; - allwinner,use-internal-phy; allwinner,leds-active-low; status = "okay"; - phy1: ethernet-phy@1 { - reg = <1>; - }; }; &mmc0 { diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts index b8340f7..afba264 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts @@ -53,6 +53,7 @@ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -167,12 +168,8 @@ }; &emac { - phy = <&phy1>; + phy-handle = <&int_mii_phy>; phy-mode = "mii"; - allwinner,use-internal-phy; allwinner,leds-active-low; status = "okay"; - phy1: ethernet-phy@1 { - reg = <1>; - }; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-plus.dts index e7079b2..136e441 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-plus.dts @@ -82,7 +82,13 @@ pinctrl-0 = <&emac_rgmii_pins>; phy-supply = <®_gmac_3v3>; phy-mode = "rgmii"; - /delete-property/allwinner,use-internal-phy; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; }; &mmc2 { diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts index f97b040..51aaf49 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts @@ -69,8 +69,15 @@ pinctrl-names = "default"; pinctrl-0 = <&emac_rgmii_pins>; phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; phy-mode = "rgmii"; - /delete-property/allwinner,use-internal-phy; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; }; &pio { diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi index afa6079..d9d31fa 100644 --- a/arch/arm/dts/sun8i-h3.dtsi +++ b/arch/arm/dts/sun8i-h3.dtsi @@ -144,9 +144,10 @@ #size-cells = <1>; ranges; - syscon: syscon@01c00000 { - compatible = "allwinner,sun8i-h3-syscon","syscon"; - reg = <0x01c00000 0x34>; + syscon: syscon@1c00000 { + compatible = "allwinner,sun8i-h3-system-controller", + "syscon"; + reg = <0x01c00000 0x1000>; }; dma: dma-controller@01c02000 { @@ -339,15 +340,12 @@ interrupt-controller; #interrupt-cells = <3>; - emac_rgmii_pins: emac0@0 { - allwinner,pins = "PD0", "PD1", "PD2", "PD3", - "PD4", "PD5", "PD7", - "PD8", "PD9", "PD10", - "PD12", "PD13", "PD15", - "PD16", "PD17"; - allwinner,function = "emac"; - allwinner,drive = ; - allwinner,pull = ; + emac_rgmii_pins: emac0 { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", + "PD5", "PD7", "PD8", "PD9", "PD10", + "PD12", "PD13", "PD15", "PD16", "PD17"; + function = "emac"; + drive-strength = <40>; }; mmc0_pins_a: mmc0@0 { @@ -466,16 +464,51 @@ emac: ethernet@1c30000 { compatible = "allwinner,sun8i-h3-emac"; - reg = <0x01c30000 0x104>, <0x01c00030 0x4>; - reg-names = "emac", "syscon"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; interrupts = ; - resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>; - reset-names = "ahb", "ephy"; - clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>; - clock-names = "ahb", "ephy"; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + mdio-parent-bus = <&mdio>; + /* Only one MDIO is usable at the time */ + internal_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + + external_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; gic: interrupt-controller@01c81000 { From 0bb48ef24326cf4df4ef0d2739fbbe5764b55f43 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 4 Apr 2018 01:31:19 +0100 Subject: [PATCH 27/31] arm: dts: sunxi: update H5 to new EMAC binding The U-Boot driver for the sun8i-emac was using some preliminary DT binding. Now since Linux got its own driver in v4.15 and our driver can now cope with both bindings, let's convert the DT nodes used by the OrangePi PC2 over to the new bindings used by the kernel. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts index 780d59a..d1c347d 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts @@ -108,10 +108,13 @@ pinctrl-names = "default"; pinctrl-0 = <&emac_rgmii_pins>; phy-mode = "rgmii"; - phy = <&phy1>; + phy-handle = <&ext_rgmii_phy>; status = "okay"; +}; - phy1: ethernet-phy@1 { +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; }; }; From ecd0cec04ca672b9ca8d003ef2a07429f7d4c101 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 4 Apr 2018 01:31:20 +0100 Subject: [PATCH 28/31] net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- drivers/net/sun8i_emac.c | 78 ++++++++++++++++-------------------------------- 1 file changed, 25 insertions(+), 53 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 55d82f8..b6e5daf 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -456,7 +456,7 @@ static int parse_phy_pins(struct udevice *dev) { int offset; const char *pin_name; - int drive, pull, i; + int drive, pull = SUN4I_PINCTRL_NO_PULL, i; offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "pinctrl-0"); @@ -476,31 +476,20 @@ static int parse_phy_pins(struct udevice *dev) drive = SUN4I_PINCTRL_30_MA; else drive = SUN4I_PINCTRL_40_MA; - } else { - drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, - "allwinner,drive", 4); } if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL)) pull = SUN4I_PINCTRL_PULL_UP; - else if (fdt_get_property(gd->fdt_blob, offset, "bias-disable", NULL)) - pull = SUN4I_PINCTRL_NO_PULL; else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL)) pull = SUN4I_PINCTRL_PULL_DOWN; - else - pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, - "allwinner,pull", 0); + for (i = 0; ; i++) { int pin; pin_name = fdt_stringlist_get(gd->fdt_blob, offset, - "allwinner,pins", i, NULL); - if (!pin_name) { - pin_name = fdt_stringlist_get(gd->fdt_blob, offset, - "pins", i, NULL); - if (!pin_name) - break; - } + "pins", i, NULL); + if (!pin_name) + break; pin = sunxi_name_to_gpio(pin_name); if (pin < 0) @@ -798,6 +787,7 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; struct emac_eth_dev *priv = dev_get_priv(dev); const char *phy_mode; + const fdt32_t *reg; int node = dev_of_offset(dev); int offset = 0; #ifdef CONFIG_DM_GPIO @@ -805,35 +795,25 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) int ret = 0; #endif - pdata->iobase = devfdt_get_addr_name(dev, "emac"); - if (pdata->iobase == FDT_ADDR_T_NONE) - pdata->iobase = devfdt_get_addr(dev); + pdata->iobase = devfdt_get_addr(dev); if (pdata->iobase == FDT_ADDR_T_NONE) { debug("%s: Cannot find MAC base address\n", __func__); return -EINVAL; } - priv->sysctl_reg = devfdt_get_addr_name(dev, "syscon"); - if (priv->sysctl_reg == FDT_ADDR_T_NONE) { - const fdt32_t *reg; - - offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); - if (offset < 0) { - debug("%s: cannot find syscon node\n", __func__); - return -EINVAL; - } - reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL); - if (!reg) { - debug("%s: cannot find reg property in syscon node\n", - __func__); - return -EINVAL; - } - priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, - offset, reg); - } else { - priv->sysctl_reg -= 0x30; + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); + if (offset < 0) { + debug("%s: cannot find syscon node\n", __func__); + return -EINVAL; } - + reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL); + if (!reg) { + debug("%s: cannot find reg property in syscon node\n", + __func__); + return -EINVAL; + } + priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, + offset, reg); if (priv->sysctl_reg == FDT_ADDR_T_NONE) { debug("%s: Cannot find syscon base address\n", __func__); return -EINVAL; @@ -843,10 +823,7 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) priv->phyaddr = -1; priv->use_internal_phy = false; - offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy"); - if (offset < 0) - offset = fdtdec_lookup_phandle(gd->fdt_blob, node, - "phy-handle"); + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); if (offset < 0) { debug("%s: Cannot find PHY address\n", __func__); return -EINVAL; @@ -873,17 +850,12 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) } if (priv->variant == H3_EMAC) { - if (fdt_getprop(gd->fdt_blob, node, - "allwinner,use-internal-phy", NULL)) { - priv->use_internal_phy = true; - } else { - int parent = fdt_parent_offset(gd->fdt_blob, offset); + int parent = fdt_parent_offset(gd->fdt_blob, offset); - if (parent >= 0 && - !fdt_node_check_compatible(gd->fdt_blob, parent, - "allwinner,sun8i-h3-mdio-internal")) - priv->use_internal_phy = true; - } + if (parent >= 0 && + !fdt_node_check_compatible(gd->fdt_blob, parent, + "allwinner,sun8i-h3-mdio-internal")) + priv->use_internal_phy = true; } priv->interface = pdata->phy_interface; From 901fb09d01b80c0ddf923078c364a6b55ed43d1d Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 4 Apr 2018 01:31:21 +0100 Subject: [PATCH 29/31] sunxi: disable direct MMC environment Since the dawn of time for the Allwinner support in mainline U-Boot we store the environment to the SD card and write directly at 544KB from the beginning of the device. This leads to problems when the U-Boot proper image grows beyond 504KB and eventually overlaps. With one release of having the environment preferably in a FAT partition, let's now turn off the MMC variant fallback, so we get back all the space we need to implement features. Signed-off-by: Andre Przywara Reviewed-by: Jagan Teki Acked-by: Maxime Ripard --- env/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/env/Kconfig b/env/Kconfig index a3c6298..0c1e928 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -152,7 +152,6 @@ config ENV_IS_IN_MMC bool "Environment in an MMC device" depends on !CHAIN_OF_TRUST depends on MMC - default y if ARCH_SUNXI default y if ARCH_EXYNOS4 default y if MX6SX || MX7D default y if TEGRA30 || TEGRA124 From d14db11d76e154a03e3fbaedb2fe4f13da7bb65f Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 4 Apr 2018 01:31:22 +0100 Subject: [PATCH 30/31] sunxi: revert disabling of features In January some commits were introduced to mitigate the U-Boot image size issues we encountered on sunxi builds. Now with the MMC environment removed we can bring them back, as we practically don't have a size limit anymore. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- cmd/Kconfig | 5 ----- drivers/video/Kconfig | 2 -- lib/Kconfig | 1 - 3 files changed, 8 deletions(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index 136836d..27086df 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -426,7 +426,6 @@ menu "Memory commands" config CMD_CRC32 bool "crc32" select HASH - default n if ARCH_SUNXI default y help Compute CRC32. @@ -568,7 +567,6 @@ config CMD_LZMADEC config CMD_UNZIP bool "unzip" - default n if ARCH_SUNXI default y if CMD_BOOTI help Uncompress a zip-compressed memory region. @@ -780,14 +778,12 @@ config CMD_I2C config CMD_LOADB bool "loadb" - default n if ARCH_SUNXI default y help Load a binary file over serial line. config CMD_LOADS bool "loads" - default n if ARCH_SUNXI default y help Load an S-Record file over serial line @@ -1187,7 +1183,6 @@ config CMD_GETTIME # TODO: rename to CMD_SLEEP config CMD_MISC bool "sleep" - default n if ARCH_SUNXI default y help Delay execution for some time diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2fc0def..45a105d 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -38,7 +38,6 @@ config BACKLIGHT_GPIO config VIDEO_BPP8 bool "Support 8-bit-per-pixel displays" depends on DM_VIDEO - default n if ARCH_SUNXI default y if DM_VIDEO help Support drawing text and bitmaps onto a 8-bit-per-pixel display. @@ -49,7 +48,6 @@ config VIDEO_BPP8 config VIDEO_BPP16 bool "Support 16-bit-per-pixel displays" depends on DM_VIDEO - default n if ARCH_SUNXI default y if DM_VIDEO help Support drawing text and bitmaps onto a 16-bit-per-pixel display. diff --git a/lib/Kconfig b/lib/Kconfig index 4fd41c4..ab581f1 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -66,7 +66,6 @@ config PANIC_HANG config REGEX bool "Enable regular expression support" - default n if ARCH_SUNXI default y if NET help If this variable is defined, U-Boot is linked against the From f3fed05e095439b3fd24990e20dbea1d4b03c121 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 4 Apr 2018 01:31:23 +0100 Subject: [PATCH 31/31] Revert "sunxi: Pine64: temporarily remove extra Pine64 non-plus DT" Now with the MMC environment gone, we have enough space to accommodate the Pine64 "non-plus" .dtb again. This reverts commit 47952b8e42c2790150e16d3d4235b3a1ee0ba9bb. Signed-off-by: Andre Przywara Reviewed-by: Jagan Teki --- configs/pine64_plus_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index a8d4e2b..a4ca68a 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus" CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y