85xx: convert SBC8540/SBC8560/SBC8548 over to use new LAW init code

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
master
Kumar Gala 17 years ago
parent 2cfaa1aa1a
commit e2b159d007
  1. 3
      board/sbc8548/Makefile
  2. 48
      board/sbc8548/init.S
  3. 57
      board/sbc8548/law.c
  4. 3
      board/sbc8560/Makefile
  5. 45
      board/sbc8560/init.S
  6. 60
      board/sbc8560/law.c
  7. 1
      include/configs/SBC8540.h
  8. 1
      include/configs/sbc8548.h
  9. 1
      include/configs/sbc8560.h

@ -28,9 +28,8 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o
COBJS := $(BOARD).o law.o
SOBJS := init.o
#SOBJS :=
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

@ -191,51 +191,3 @@ tlb1_entry:
.long FSL_BOOKE_MAS3(CFG_EPLD_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
entry_end
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x0fff_ffff DDR 256M
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
* 0xf8b0_0000 0xf80f_ffff EEPROM 1M
* 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*
* The defines below are 1-off of the actual LAWAR0 usage.
* So LAWAR3 define uses the LAWAR4 register in the ECM.
*/
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
#else
#define LAWBAR0 0
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) & ~LAWAR_EN)
#endif
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR2 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
#define LAWBAR3 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
.section .bootpg, "ax"
.globl law_entry
law_entry:
entry_start
.long 4
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
entry_end

@ -0,0 +1,57 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x0fff_ffff DDR 256M
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
* 0xf8b0_0000 0xf80f_ffff EEPROM 1M
* 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
SET_LAW_ENTRY(4, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

@ -28,9 +28,8 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o
COBJS := $(BOARD).o law.o
SOBJS := init.o
#SOBJS :=
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

@ -40,51 +40,6 @@
mtlr r1 ; \
blr ;
/* LAW(Local Access Window) configuration:
* 0000_0000-0800_0000: DDR(512M) -or- larger
* c000_0000-cfff_ffff: PCI(256M)
* d000_0000-dfff_ffff: RapidIO(256M)
* e000_0000-ffff_ffff: localbus(512M)
* e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
* e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
* e800_0000-efff_ffff: LBC 128M, nothing here
* f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
* f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
* f800_0000-fdff_ffff: LBC 64M, nothing here
* fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
* fd00_0000-fdff_ffff: LBC 16M, nothing here
* fe00_0000-feff_ffff: LBC 16M, nothing here
* ff00_0000-ff6f_ffff: LBC 7M, nothing here
* ff70_0000-ff7f_ffff: CCSRBAR 1M
* ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
* Window.
* Note: If flash is 8M at default position(last 8M),no LAW needed.
*/
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
#else
#define LAWBAR0 0
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
#endif
#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
#define LAWBAR2 ((0xe0000000>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M))
.section .bootpg, "ax"
.globl law_entry
law_entry:
entry_start
.long 0x03
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
entry_end
/* TLB1 entries configuration: */
.section .bootpg, "ax"

@ -0,0 +1,60 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
/* LAW(Local Access Window) configuration:
* 0000_0000-0800_0000: DDR(512M) -or- larger
* c000_0000-cfff_ffff: PCI(256M)
* d000_0000-dfff_ffff: RapidIO(256M)
* e000_0000-ffff_ffff: localbus(512M)
* e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
* e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
* e800_0000-efff_ffff: LBC 128M, nothing here
* f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
* f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
* f800_0000-fdff_ffff: LBC 64M, nothing here
* fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
* fd00_0000-fdff_ffff: LBC 16M, nothing here
* fe00_0000-feff_ffff: LBC 16M, nothing here
* ff00_0000-ff6f_ffff: LBC 7M, nothing here
* ff70_0000-ff7f_ffff: CCSRBAR 1M
* ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
* Window.
* Note: If flash is 8M at default position(last 8M),no LAW needed.
*/
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
#endif
SET_LAW_ENTRY(2, CFG_PCI_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

@ -56,6 +56,7 @@
#undef CONFIG_PCI /* pci ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE

@ -56,6 +56,7 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */

@ -50,6 +50,7 @@
#undef CONFIG_PCI /* pci ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE

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