Tom Rini
10 years ago
commit
e38b15b061
@ -1,13 +0,0 @@ |
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/* |
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* Copyright 2012 Freescale Semiconductor, Inc. |
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* Copyright 2011 Linaro Ltd. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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/ { |
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model = "Freescale i.MX6 Quad SABRE Automotive Board"; |
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compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; |
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}; |
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@ -0,0 +1,23 @@ |
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if TARGET_CM_FX6 |
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|
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config SYS_CPU |
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string |
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default "armv7" |
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config SYS_BOARD |
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string |
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default "cm_fx6" |
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config SYS_VENDOR |
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string |
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default "compulab" |
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config SYS_SOC |
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string |
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default "mx6" |
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config SYS_CONFIG_NAME |
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string |
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default "cm_fx6" |
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endif |
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@ -0,0 +1,6 @@ |
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CM_FX6 BOARD |
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M: Nikita Kiryanov <nikita@compulab.co.il> |
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S: Maintained |
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F: board/compulab/cm_fx6/ |
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F: include/configs/cm_fx6.h |
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F: configs/cm_fx6_defconfig |
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@ -0,0 +1,12 @@ |
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#
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# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
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#
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# Authors: Nikita Kiryanov <nikita@compulab.co.il>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD |
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obj-y = common.o spl.o
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else |
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obj-y = common.o cm_fx6.o
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endif |
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@ -0,0 +1,483 @@ |
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/*
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* Board functions for Compulab CM-FX6 board |
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* |
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* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
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* |
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* Author: Nikita Kiryanov <nikita@compulab.co.il> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <fsl_esdhc.h> |
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#include <miiphy.h> |
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#include <netdev.h> |
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#include <fdt_support.h> |
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#include <sata.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/imx-common/mxc_i2c.h> |
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#include <asm/imx-common/sata.h> |
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#include <asm/io.h> |
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#include <asm/gpio.h> |
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#include "common.h" |
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#include "../common/eeprom.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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#ifdef CONFIG_DWC_AHSATA |
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static int cm_fx6_issd_gpios[] = { |
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/* The order of the GPIOs in the array is important! */ |
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CM_FX6_SATA_PHY_SLP, |
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CM_FX6_SATA_NRSTDLY, |
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CM_FX6_SATA_PWREN, |
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CM_FX6_SATA_NSTANDBY1, |
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CM_FX6_SATA_NSTANDBY2, |
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CM_FX6_SATA_LDO_EN, |
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}; |
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static void cm_fx6_sata_power(int on) |
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{ |
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int i; |
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if (!on) { /* tell the iSSD that the power will be removed */ |
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gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1); |
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mdelay(10); |
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} |
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for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { |
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gpio_direction_output(cm_fx6_issd_gpios[i], on); |
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udelay(100); |
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} |
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if (!on) /* for compatibility lower the power loss interrupt */ |
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gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); |
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} |
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static iomux_v3_cfg_t const sata_pads[] = { |
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/* SATA PWR */ |
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IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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/* SATA CTRL */ |
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IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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}; |
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static void cm_fx6_setup_issd(void) |
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{ |
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SETUP_IOMUX_PADS(sata_pads); |
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/* Make sure this gpio has logical 0 value */ |
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gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); |
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udelay(100); |
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cm_fx6_sata_power(0); |
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mdelay(250); |
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cm_fx6_sata_power(1); |
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} |
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#define CM_FX6_SATA_INIT_RETRIES 10 |
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int sata_initialize(void) |
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{ |
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int err, i; |
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cm_fx6_setup_issd(); |
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for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) { |
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err = setup_sata(); |
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if (err) { |
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printf("SATA setup failed: %d\n", err); |
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return err; |
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} |
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udelay(100); |
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err = __sata_initialize(); |
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if (!err) |
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break; |
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/* There is no device on the SATA port */ |
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if (sata_port_status(0, 0) == 0) |
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break; |
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/* There's a device, but link not established. Retry */ |
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} |
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return err; |
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} |
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#endif |
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#ifdef CONFIG_SYS_I2C_MXC |
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST) |
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I2C_PADS(i2c0_pads, |
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PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), |
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PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL), |
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IMX_GPIO_NR(3, 21), |
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PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), |
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PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL), |
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IMX_GPIO_NR(3, 28)); |
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I2C_PADS(i2c1_pads, |
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PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), |
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PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL), |
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IMX_GPIO_NR(4, 12), |
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PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), |
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PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL), |
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IMX_GPIO_NR(4, 13)); |
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I2C_PADS(i2c2_pads, |
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PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), |
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PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL), |
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IMX_GPIO_NR(1, 3), |
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PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), |
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PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL), |
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IMX_GPIO_NR(1, 6)); |
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static void cm_fx6_setup_i2c(void) |
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{ |
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c0_pads)); |
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setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c1_pads)); |
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setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c2_pads)); |
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} |
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#else |
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static void cm_fx6_setup_i2c(void) { } |
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#endif |
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#ifdef CONFIG_USB_EHCI_MX6 |
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#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ |
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_HYS | PAD_CTL_SRE_SLOW) |
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static int cm_fx6_usb_hub_reset(void) |
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{ |
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int err; |
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err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst"); |
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if (err) { |
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printf("USB hub rst gpio request failed: %d\n", err); |
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return -1; |
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} |
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SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)); |
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gpio_direction_output(CM_FX6_USB_HUB_RST, 0); |
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udelay(10); |
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gpio_direction_output(CM_FX6_USB_HUB_RST, 1); |
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mdelay(1); |
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return 0; |
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} |
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static int cm_fx6_init_usb_otg(void) |
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{ |
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int ret; |
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
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ret = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr"); |
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if (ret) { |
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printf("USB OTG pwr gpio request failed: %d\n", ret); |
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return ret; |
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} |
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SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL)); |
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SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID | |
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MUX_PAD_CTRL(WEAK_PULLDOWN)); |
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clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK); |
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/* disable ext. charger detect, or it'll affect signal quality at dp. */ |
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return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0); |
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} |
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#define MX6_USBNC_BASEADDR 0x2184800 |
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#define USBNC_USB_H1_PWR_POL (1 << 9) |
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int board_ehci_hcd_init(int port) |
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{ |
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u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4); |
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switch (port) { |
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case 0: |
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return cm_fx6_init_usb_otg(); |
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case 1: |
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SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | |
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MUX_PAD_CTRL(NO_PAD_CTRL)); |
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/* Set PWR polarity to match power switch's enable polarity */ |
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setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL); |
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return cm_fx6_usb_hub_reset(); |
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default: |
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break; |
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} |
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return 0; |
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} |
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int board_ehci_power(int port, int on) |
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{ |
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if (port == 0) |
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return gpio_direction_output(SB_FX6_USB_OTG_PWR, on); |
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return 0; |
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} |
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#endif |
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#ifdef CONFIG_FEC_MXC |
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
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static int mx6_rgmii_rework(struct phy_device *phydev) |
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{ |
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unsigned short val; |
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/* Ar8031 phy SmartEEE feature cause link status generates glitch,
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* which cause ethernet link down/up issue, so disable SmartEEE |
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*/ |
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); |
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); |
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); |
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); |
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val &= ~(0x1 << 8); |
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); |
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/* To enable AR8031 ouput a 125MHz clk from CLK_25M */ |
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); |
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); |
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); |
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); |
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val &= 0xffe3; |
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val |= 0x18; |
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); |
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/* introduce tx clock delay */ |
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); |
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); |
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val |= 0x0100; |
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); |
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return 0; |
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} |
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int board_phy_config(struct phy_device *phydev) |
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{ |
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mx6_rgmii_rework(phydev); |
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if (phydev->drv->config) |
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return phydev->drv->config(phydev); |
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return 0; |
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} |
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static iomux_v3_cfg_t const enet_pads[] = { |
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IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)), |
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IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | |
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MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | |
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MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | |
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MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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}; |
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static int handle_mac_address(void) |
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{ |
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unsigned char enetaddr[6]; |
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int rc; |
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rc = eth_getenv_enetaddr("ethaddr", enetaddr); |
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if (rc) |
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return 0; |
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rc = cl_eeprom_read_mac_addr(enetaddr); |
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if (rc) |
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return rc; |
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if (!is_valid_ether_addr(enetaddr)) |
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return -1; |
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return eth_setenv_enetaddr("ethaddr", enetaddr); |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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int res = handle_mac_address(); |
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if (res) |
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puts("No MAC address found\n"); |
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SETUP_IOMUX_PADS(enet_pads); |
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/* phy reset */ |
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gpio_direction_output(CM_FX6_ENET_NRST, 0); |
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udelay(500); |
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gpio_set_value(CM_FX6_ENET_NRST, 1); |
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enable_enet_clk(1); |
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return cpu_eth_init(bis); |
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} |
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#endif |
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|
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#ifdef CONFIG_NAND_MXS |
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static iomux_v3_cfg_t const nand_pads[] = { |
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IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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}; |
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static void cm_fx6_setup_gpmi_nand(void) |
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{ |
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SETUP_IOMUX_PADS(nand_pads); |
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/* Enable clock roots */ |
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enable_usdhc_clk(1, 3); |
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enable_usdhc_clk(1, 4); |
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|
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setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) | |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) | |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL(0)); |
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} |
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#else |
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static void cm_fx6_setup_gpmi_nand(void) {} |
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#endif |
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|
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#ifdef CONFIG_FSL_ESDHC |
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static struct fsl_esdhc_cfg usdhc_cfg[3] = { |
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{USDHC1_BASE_ADDR}, |
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{USDHC2_BASE_ADDR}, |
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{USDHC3_BASE_ADDR}, |
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}; |
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|
||||
static enum mxc_clock usdhc_clk[3] = { |
||||
MXC_ESDHC_CLK, |
||||
MXC_ESDHC2_CLK, |
||||
MXC_ESDHC3_CLK, |
||||
}; |
||||
|
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
int i; |
||||
|
||||
cm_fx6_set_usdhc_iomux(); |
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
||||
usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]); |
||||
usdhc_cfg[i].max_bus_width = 4; |
||||
fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
||||
enable_usdhc_clk(1, i); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP |
||||
void ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
uint8_t enetaddr[6]; |
||||
|
||||
/* MAC addr */ |
||||
if (eth_getenv_enetaddr("ethaddr", enetaddr)) { |
||||
fdt_find_and_setprop(blob, "/fec", "local-mac-address", |
||||
enetaddr, 6, 1); |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
int board_init(void) |
||||
{ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
||||
cm_fx6_setup_gpmi_nand(); |
||||
cm_fx6_setup_i2c(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: CM-FX6\n"); |
||||
return 0; |
||||
} |
||||
|
||||
void dram_init_banksize(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
||||
|
||||
switch (gd->ram_size) { |
||||
case 0x10000000: /* DDR_16BIT_256MB */ |
||||
gd->bd->bi_dram[0].size = 0x10000000; |
||||
gd->bd->bi_dram[1].size = 0; |
||||
break; |
||||
case 0x20000000: /* DDR_32BIT_512MB */ |
||||
gd->bd->bi_dram[0].size = 0x20000000; |
||||
gd->bd->bi_dram[1].size = 0; |
||||
break; |
||||
case 0x40000000: |
||||
if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */ |
||||
gd->bd->bi_dram[0].size = 0x20000000; |
||||
gd->bd->bi_dram[1].size = 0x20000000; |
||||
} else { /* DDR_64BIT_1GB */ |
||||
gd->bd->bi_dram[0].size = 0x40000000; |
||||
gd->bd->bi_dram[1].size = 0; |
||||
} |
||||
break; |
||||
case 0x80000000: /* DDR_64BIT_2GB */ |
||||
gd->bd->bi_dram[0].size = 0x40000000; |
||||
gd->bd->bi_dram[1].size = 0x40000000; |
||||
break; |
||||
case 0xEFF00000: /* DDR_64BIT_4GB */ |
||||
gd->bd->bi_dram[0].size = 0x70000000; |
||||
gd->bd->bi_dram[1].size = 0x7FF00000; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = imx_ddr_size(); |
||||
switch (gd->ram_size) { |
||||
case 0x10000000: |
||||
case 0x20000000: |
||||
case 0x40000000: |
||||
case 0x80000000: |
||||
break; |
||||
case 0xF0000000: |
||||
gd->ram_size -= 0x100000; |
||||
break; |
||||
default: |
||||
printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
u32 get_board_rev(void) |
||||
{ |
||||
return cl_eeprom_get_board_rev(); |
||||
} |
||||
|
||||
@ -0,0 +1,84 @@ |
||||
/*
|
||||
* Code used by both U-Boot and SPL for Compulab CM-FX6 |
||||
* |
||||
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
|
||||
* |
||||
* Author: Nikita Kiryanov <nikita@compulab.co.il> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/gpio.h> |
||||
#include <fsl_esdhc.h> |
||||
#include "common.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_FSL_ESDHC |
||||
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
||||
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
|
||||
PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
||||
|
||||
static iomux_v3_cfg_t const usdhc_pads[] = { |
||||
IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
|
||||
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
|
||||
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
}; |
||||
|
||||
void cm_fx6_set_usdhc_iomux(void) |
||||
{ |
||||
SETUP_IOMUX_PADS(usdhc_pads); |
||||
} |
||||
|
||||
/* CINS bit doesn't work, so always try to access the MMC card */ |
||||
int board_mmc_getcd(struct mmc *mmc) |
||||
{ |
||||
return 1; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MXC_SPI |
||||
#define ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ |
||||
PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
||||
|
||||
static iomux_v3_cfg_t const ecspi_pads[] = { |
||||
IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), |
||||
}; |
||||
|
||||
void cm_fx6_set_ecspi_iomux(void) |
||||
{ |
||||
SETUP_IOMUX_PADS(ecspi_pads); |
||||
} |
||||
|
||||
int board_spi_cs_gpio(unsigned bus, unsigned cs) |
||||
{ |
||||
return (bus == 0 && cs == 0) ? (CM_FX6_ECSPI_BUS0_CS0) : -1; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,37 @@ |
||||
/*
|
||||
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
|
||||
* |
||||
* Author: Nikita Kiryanov <nikita@compulab.co.il> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <asm/arch/mx6-pins.h> |
||||
#include <asm/arch/clock.h> |
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
||||
|
||||
#define CM_FX6_ECSPI_BUS0_CS0 IMX_GPIO_NR(2, 30) |
||||
#define CM_FX6_GREEN_LED IMX_GPIO_NR(2, 31) |
||||
#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8) |
||||
#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8) |
||||
#define CM_FX6_USB_HUB_RST IMX_GPIO_NR(7, 8) |
||||
#define SB_FX6_USB_OTG_PWR IMX_GPIO_NR(3, 22) |
||||
#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8) |
||||
#define CM_FX6_USB_HUB_RST IMX_GPIO_NR(7, 8) |
||||
#define SB_FX6_USB_OTG_PWR IMX_GPIO_NR(3, 22) |
||||
#define CM_FX6_SATA_PWREN IMX_GPIO_NR(1, 28) |
||||
#define CM_FX6_SATA_VDDC_CTRL IMX_GPIO_NR(1, 30) |
||||
#define CM_FX6_SATA_LDO_EN IMX_GPIO_NR(2, 16) |
||||
#define CM_FX6_SATA_NSTANDBY1 IMX_GPIO_NR(3, 20) |
||||
#define CM_FX6_SATA_PHY_SLP IMX_GPIO_NR(3, 23) |
||||
#define CM_FX6_SATA_STBY_REQ IMX_GPIO_NR(3, 29) |
||||
#define CM_FX6_SATA_NSTANDBY2 IMX_GPIO_NR(5, 2) |
||||
#define CM_FX6_SATA_NRSTDLY IMX_GPIO_NR(6, 6) |
||||
#define CM_FX6_SATA_PWLOSS_INT IMX_GPIO_NR(6, 31) |
||||
|
||||
|
||||
void cm_fx6_set_usdhc_iomux(void); |
||||
void cm_fx6_set_ecspi_iomux(void); |
||||
@ -0,0 +1,8 @@ |
||||
/* |
||||
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
IMAGE_VERSION 2 |
||||
BOOT_FROM sd |
||||
@ -0,0 +1,366 @@ |
||||
/*
|
||||
* SPL specific code for Compulab CM-FX6 board |
||||
* |
||||
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
|
||||
* |
||||
* Author: Nikita Kiryanov <nikita@compulab.co.il> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <spl.h> |
||||
#include <asm/io.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/arch/mx6-ddr.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <asm/imx-common/iomux-v3.h> |
||||
#include <fsl_esdhc.h> |
||||
#include "common.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
enum ddr_config { |
||||
DDR_16BIT_256MB, |
||||
DDR_32BIT_512MB, |
||||
DDR_32BIT_1GB, |
||||
DDR_64BIT_1GB, |
||||
DDR_64BIT_2GB, |
||||
DDR_64BIT_4GB, |
||||
DDR_UNKNOWN, |
||||
}; |
||||
|
||||
/*
|
||||
* Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to |
||||
* Freescale QRM, but this is exactly the value used by the automatic |
||||
* calibration script and it works also in all our tests, so we leave |
||||
* it as is at this point. |
||||
*/ |
||||
#define CM_FX6_DDR_IOMUX_CFG \ |
||||
.dram_sdqs0 = 0x00000038, \
|
||||
.dram_sdqs1 = 0x00000038, \
|
||||
.dram_sdqs2 = 0x00000038, \
|
||||
.dram_sdqs3 = 0x00000038, \
|
||||
.dram_sdqs4 = 0x00000038, \
|
||||
.dram_sdqs5 = 0x00000038, \
|
||||
.dram_sdqs6 = 0x00000038, \
|
||||
.dram_sdqs7 = 0x00000038, \
|
||||
.dram_dqm0 = 0x00000038, \
|
||||
.dram_dqm1 = 0x00000038, \
|
||||
.dram_dqm2 = 0x00000038, \
|
||||
.dram_dqm3 = 0x00000038, \
|
||||
.dram_dqm4 = 0x00000038, \
|
||||
.dram_dqm5 = 0x00000038, \
|
||||
.dram_dqm6 = 0x00000038, \
|
||||
.dram_dqm7 = 0x00000038, \
|
||||
.dram_cas = 0x00000038, \
|
||||
.dram_ras = 0x00000038, \
|
||||
.dram_sdclk_0 = 0x00000038, \
|
||||
.dram_sdclk_1 = 0x00000038, \
|
||||
.dram_sdcke0 = 0x00003000, \
|
||||
.dram_sdcke1 = 0x00003000, \
|
||||
.dram_reset = 0x00000038, \
|
||||
.dram_sdba2 = 0x00000000, \
|
||||
.dram_sdodt0 = 0x00000038, \
|
||||
.dram_sdodt1 = 0x00000038, |
||||
|
||||
#define CM_FX6_GPR_IOMUX_CFG \ |
||||
.grp_b0ds = 0x00000038, \
|
||||
.grp_b1ds = 0x00000038, \
|
||||
.grp_b2ds = 0x00000038, \
|
||||
.grp_b3ds = 0x00000038, \
|
||||
.grp_b4ds = 0x00000038, \
|
||||
.grp_b5ds = 0x00000038, \
|
||||
.grp_b6ds = 0x00000038, \
|
||||
.grp_b7ds = 0x00000038, \
|
||||
.grp_addds = 0x00000038, \
|
||||
.grp_ddrmode_ctl = 0x00020000, \
|
||||
.grp_ddrpke = 0x00000000, \
|
||||
.grp_ddrmode = 0x00020000, \
|
||||
.grp_ctlds = 0x00000038, \
|
||||
.grp_ddr_type = 0x000C0000, |
||||
|
||||
static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG }; |
||||
static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG }; |
||||
static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG }; |
||||
static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG }; |
||||
|
||||
static struct mx6_mmdc_calibration cm_fx6_calib_s = { |
||||
.p0_mpwldectrl0 = 0x005B0061, |
||||
.p0_mpwldectrl1 = 0x004F0055, |
||||
.p0_mpdgctrl0 = 0x0314030C, |
||||
.p0_mpdgctrl1 = 0x025C0268, |
||||
.p0_mprddlctl = 0x42464646, |
||||
.p0_mpwrdlctl = 0x36322C34, |
||||
}; |
||||
|
||||
static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = { |
||||
.cs1_mirror = 1, |
||||
.cs_density = 16, |
||||
.bi_on = 1, |
||||
.rtt_nom = 1, |
||||
.rtt_wr = 0, |
||||
.ralat = 5, |
||||
.walat = 1, |
||||
.mif3_mode = 3, |
||||
.rst_to_cke = 0x23, |
||||
.sde_to_rst = 0x10, |
||||
}; |
||||
|
||||
static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = { |
||||
.mem_speed = 800, |
||||
.density = 4, |
||||
.rowaddr = 14, |
||||
.coladdr = 10, |
||||
.pagesz = 2, |
||||
.trcd = 1800, |
||||
.trcmin = 5200, |
||||
.trasmin = 3600, |
||||
.SRT = 0, |
||||
}; |
||||
|
||||
static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset) |
||||
{ |
||||
if (reset) |
||||
((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; |
||||
|
||||
switch (dram_config) { |
||||
case DDR_16BIT_256MB: |
||||
cm_fx6_sysinfo_s.dsize = 0; |
||||
cm_fx6_sysinfo_s.ncs = 1; |
||||
break; |
||||
case DDR_32BIT_512MB: |
||||
cm_fx6_sysinfo_s.dsize = 1; |
||||
cm_fx6_sysinfo_s.ncs = 1; |
||||
break; |
||||
case DDR_32BIT_1GB: |
||||
cm_fx6_sysinfo_s.dsize = 1; |
||||
cm_fx6_sysinfo_s.ncs = 2; |
||||
break; |
||||
default: |
||||
puts("Tried to setup invalid DDR configuration\n"); |
||||
hang(); |
||||
} |
||||
|
||||
mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s); |
||||
udelay(100); |
||||
} |
||||
|
||||
static struct mx6_mmdc_calibration cm_fx6_calib_q = { |
||||
.p0_mpwldectrl0 = 0x00630068, |
||||
.p0_mpwldectrl1 = 0x0068005D, |
||||
.p0_mpdgctrl0 = 0x04140428, |
||||
.p0_mpdgctrl1 = 0x037C037C, |
||||
.p0_mprddlctl = 0x3C30303A, |
||||
.p0_mpwrdlctl = 0x3A344038, |
||||
.p1_mpwldectrl0 = 0x0035004C, |
||||
.p1_mpwldectrl1 = 0x00170026, |
||||
.p1_mpdgctrl0 = 0x0374037C, |
||||
.p1_mpdgctrl1 = 0x0350032C, |
||||
.p1_mprddlctl = 0x30322A3C, |
||||
.p1_mpwrdlctl = 0x48304A3E, |
||||
}; |
||||
|
||||
static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = { |
||||
.cs_density = 16, |
||||
.cs1_mirror = 1, |
||||
.bi_on = 1, |
||||
.rtt_nom = 1, |
||||
.rtt_wr = 0, |
||||
.ralat = 5, |
||||
.walat = 1, |
||||
.mif3_mode = 3, |
||||
.rst_to_cke = 0x23, |
||||
.sde_to_rst = 0x10, |
||||
}; |
||||
|
||||
static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = { |
||||
.mem_speed = 1066, |
||||
.density = 4, |
||||
.rowaddr = 14, |
||||
.coladdr = 10, |
||||
.pagesz = 2, |
||||
.trcd = 1324, |
||||
.trcmin = 59500, |
||||
.trasmin = 9750, |
||||
.SRT = 0, |
||||
}; |
||||
|
||||
static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset) |
||||
{ |
||||
if (reset) |
||||
((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; |
||||
|
||||
cm_fx6_ddr3_cfg_q.rowaddr = 14; |
||||
switch (dram_config) { |
||||
case DDR_16BIT_256MB: |
||||
cm_fx6_sysinfo_q.dsize = 0; |
||||
cm_fx6_sysinfo_q.ncs = 1; |
||||
break; |
||||
case DDR_32BIT_512MB: |
||||
cm_fx6_sysinfo_q.dsize = 1; |
||||
cm_fx6_sysinfo_q.ncs = 1; |
||||
break; |
||||
case DDR_64BIT_1GB: |
||||
cm_fx6_sysinfo_q.dsize = 2; |
||||
cm_fx6_sysinfo_q.ncs = 1; |
||||
break; |
||||
case DDR_64BIT_2GB: |
||||
cm_fx6_sysinfo_q.dsize = 2; |
||||
cm_fx6_sysinfo_q.ncs = 2; |
||||
break; |
||||
case DDR_64BIT_4GB: |
||||
cm_fx6_sysinfo_q.dsize = 2; |
||||
cm_fx6_sysinfo_q.ncs = 2; |
||||
cm_fx6_ddr3_cfg_q.rowaddr = 15; |
||||
break; |
||||
default: |
||||
puts("Tried to setup invalid DDR configuration\n"); |
||||
hang(); |
||||
} |
||||
|
||||
mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q); |
||||
udelay(100); |
||||
} |
||||
|
||||
static int cm_fx6_spl_dram_init(void) |
||||
{ |
||||
unsigned long bank1_size, bank2_size; |
||||
|
||||
switch (get_cpu_type()) { |
||||
case MXC_CPU_MX6SOLO: |
||||
mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s); |
||||
|
||||
spl_mx6s_dram_init(DDR_32BIT_1GB, false); |
||||
bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); |
||||
if (bank1_size == 0x40000000) |
||||
return 0; |
||||
|
||||
if (bank1_size == 0x20000000) { |
||||
spl_mx6s_dram_init(DDR_32BIT_512MB, true); |
||||
return 0; |
||||
} |
||||
|
||||
spl_mx6s_dram_init(DDR_16BIT_256MB, true); |
||||
bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); |
||||
if (bank1_size == 0x10000000) |
||||
return 0; |
||||
|
||||
break; |
||||
case MXC_CPU_MX6D: |
||||
case MXC_CPU_MX6Q: |
||||
mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q); |
||||
|
||||
spl_mx6q_dram_init(DDR_64BIT_4GB, false); |
||||
bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); |
||||
if (bank1_size == 0x80000000) |
||||
return 0; |
||||
|
||||
if (bank1_size == 0x40000000) { |
||||
bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, |
||||
0x80000000); |
||||
if (bank2_size == 0x40000000) { |
||||
/* Don't do a full reset here */ |
||||
spl_mx6q_dram_init(DDR_64BIT_2GB, false); |
||||
} else { |
||||
spl_mx6q_dram_init(DDR_64BIT_1GB, true); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
spl_mx6q_dram_init(DDR_32BIT_512MB, true); |
||||
bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); |
||||
if (bank1_size == 0x20000000) |
||||
return 0; |
||||
|
||||
spl_mx6q_dram_init(DDR_16BIT_256MB, true); |
||||
bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); |
||||
if (bank1_size == 0x10000000) |
||||
return 0; |
||||
|
||||
break; |
||||
} |
||||
|
||||
return -1; |
||||
} |
||||
|
||||
static iomux_v3_cfg_t const uart4_pads[] = { |
||||
IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
||||
}; |
||||
|
||||
static void cm_fx6_setup_uart(void) |
||||
{ |
||||
SETUP_IOMUX_PADS(uart4_pads); |
||||
enable_uart_clk(1); |
||||
} |
||||
|
||||
#ifdef CONFIG_SPL_SPI_SUPPORT |
||||
static void cm_fx6_setup_ecspi(void) |
||||
{ |
||||
cm_fx6_set_ecspi_iomux(); |
||||
enable_cspi_clock(1, 0); |
||||
} |
||||
#else |
||||
static void cm_fx6_setup_ecspi(void) { } |
||||
#endif |
||||
|
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
||||
|
||||
gd = &gdata; |
||||
/*
|
||||
* We don't use DMA in SPL, but we do need it in U-Boot. U-Boot |
||||
* initializes DMA very early (before all board code), so the only |
||||
* opportunity we have to initialize APBHDMA clocks is in SPL. |
||||
*/ |
||||
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); |
||||
enable_usdhc_clk(1, 2); |
||||
|
||||
arch_cpu_init(); |
||||
timer_init(); |
||||
cm_fx6_setup_ecspi(); |
||||
cm_fx6_setup_uart(); |
||||
get_clocks(); |
||||
preloader_console_init(); |
||||
gpio_direction_output(CM_FX6_GREEN_LED, 1); |
||||
if (cm_fx6_spl_dram_init()) { |
||||
puts("!!!ERROR!!! DRAM detection failed!!!\n"); |
||||
hang(); |
||||
} |
||||
|
||||
memset(__bss_start, 0, __bss_end - __bss_start); |
||||
board_init_r(NULL, 0); |
||||
} |
||||
|
||||
void spl_board_init(void) |
||||
{ |
||||
u32 boot_device = spl_boot_device(); |
||||
|
||||
if (boot_device == BOOT_DEVICE_SPI) |
||||
puts("Booting from SPI flash\n"); |
||||
else if (boot_device == BOOT_DEVICE_MMC1) |
||||
puts("Booting from MMC\n"); |
||||
else |
||||
puts("Unknown boot device\n"); |
||||
} |
||||
|
||||
#ifdef CONFIG_SPL_MMC_SUPPORT |
||||
static struct fsl_esdhc_cfg usdhc_cfg = { |
||||
.esdhc_base = USDHC3_BASE_ADDR, |
||||
.max_bus_width = 4, |
||||
}; |
||||
|
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
cm_fx6_set_usdhc_iomux(); |
||||
|
||||
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
||||
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,131 @@ |
||||
/* |
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Refer docs/README.imxmage for more details about how-to configure |
||||
* and create imximage boot image |
||||
* |
||||
* The syntax is taken as close as possible with the kwbimage |
||||
*/ |
||||
|
||||
/* image version */ |
||||
|
||||
IMAGE_VERSION 2 |
||||
|
||||
/* |
||||
* Boot Device : one of |
||||
* spi, sd (the board has no nand neither onenand) |
||||
*/ |
||||
|
||||
BOOT_FROM sd |
||||
|
||||
/* |
||||
* Device Configuration Data (DCD) |
||||
* |
||||
* Each entry must have the format: |
||||
* Addr-type Address Value |
||||
* |
||||
* where: |
||||
* Addr-type register length (1,2 or 4 bytes) |
||||
* Address absolute address of the register |
||||
* value value to be stored in the register |
||||
*/ |
||||
DATA 4 0x020e0774 0x000C0000 |
||||
DATA 4 0x020e0754 0x00000000 |
||||
DATA 4 0x020e04ac 0x00000030 |
||||
DATA 4 0x020e04b0 0x00000030 |
||||
DATA 4 0x020e0464 0x00000030 |
||||
DATA 4 0x020e0490 0x00000030 |
||||
DATA 4 0x020e074c 0x00000030 |
||||
DATA 4 0x020e0494 0x00000030 |
||||
DATA 4 0x020e04a0 0x00000000 |
||||
DATA 4 0x020e04b4 0x00000030 |
||||
DATA 4 0x020e04b8 0x00000030 |
||||
DATA 4 0x020e076c 0x00000030 |
||||
DATA 4 0x020e0750 0x00020000 |
||||
DATA 4 0x020e04bc 0x00000030 |
||||
DATA 4 0x020e04c0 0x00000030 |
||||
DATA 4 0x020e04c4 0x00000030 |
||||
DATA 4 0x020e04c8 0x00000030 |
||||
DATA 4 0x020e04cc 0x00000030 |
||||
DATA 4 0x020e04d0 0x00000030 |
||||
DATA 4 0x020e04d4 0x00000030 |
||||
DATA 4 0x020e04d8 0x00000030 |
||||
DATA 4 0x020e0760 0x00020000 |
||||
DATA 4 0x020e0764 0x00000030 |
||||
DATA 4 0x020e0770 0x00000030 |
||||
DATA 4 0x020e0778 0x00000030 |
||||
DATA 4 0x020e077c 0x00000030 |
||||
DATA 4 0x020e0780 0x00000030 |
||||
DATA 4 0x020e0784 0x00000030 |
||||
DATA 4 0x020e078c 0x00000030 |
||||
DATA 4 0x020e0748 0x00000030 |
||||
DATA 4 0x020e0470 0x00000030 |
||||
DATA 4 0x020e0474 0x00000030 |
||||
DATA 4 0x020e0478 0x00000030 |
||||
DATA 4 0x020e047c 0x00000030 |
||||
DATA 4 0x020e0480 0x00000030 |
||||
DATA 4 0x020e0484 0x00000030 |
||||
DATA 4 0x020e0488 0x00000030 |
||||
DATA 4 0x020e048c 0x00000030 |
||||
DATA 4 0x021b0800 0xa1390003 |
||||
DATA 4 0x021b080c 0x001F001F |
||||
DATA 4 0x021b0810 0x001F001F |
||||
DATA 4 0x021b480c 0x001F001F |
||||
DATA 4 0x021b4810 0x001F001F |
||||
DATA 4 0x021b083c 0x4220021F |
||||
DATA 4 0x021b0840 0x0207017E |
||||
DATA 4 0x021b483c 0x4201020C |
||||
DATA 4 0x021b4840 0x01660172 |
||||
DATA 4 0x021b0848 0x4A4D4E4D |
||||
DATA 4 0x021b4848 0x4A4F5049 |
||||
DATA 4 0x021b0850 0x3F3C3D31 |
||||
DATA 4 0x021b4850 0x3238372B |
||||
DATA 4 0x021b081c 0x33333333 |
||||
DATA 4 0x021b0820 0x33333333 |
||||
DATA 4 0x021b0824 0x33333333 |
||||
DATA 4 0x021b0828 0x33333333 |
||||
DATA 4 0x021b481c 0x33333333 |
||||
DATA 4 0x021b4820 0x33333333 |
||||
DATA 4 0x021b4824 0x33333333 |
||||
DATA 4 0x021b4828 0x33333333 |
||||
DATA 4 0x021b08b8 0x00000800 |
||||
DATA 4 0x021b48b8 0x00000800 |
||||
DATA 4 0x021b0004 0x0002002D |
||||
DATA 4 0x021b0008 0x00333030 |
||||
DATA 4 0x021b000c 0x3F435313 |
||||
DATA 4 0x021b0010 0xB66E8B63 |
||||
DATA 4 0x021b0014 0x01FF00DB |
||||
DATA 4 0x021b0018 0x00001740 |
||||
DATA 4 0x021b001c 0x00008000 |
||||
DATA 4 0x021b002c 0x000026d2 |
||||
DATA 4 0x021b0030 0x00431023 |
||||
DATA 4 0x021b0040 0x00000027 |
||||
DATA 4 0x021b0000 0x831A0000 |
||||
DATA 4 0x021b001c 0x04008032 |
||||
DATA 4 0x021b001c 0x00008033 |
||||
DATA 4 0x021b001c 0x00048031 |
||||
DATA 4 0x021b001c 0x05208030 |
||||
DATA 4 0x021b001c 0x04008040 |
||||
DATA 4 0x021b0020 0x00005800 |
||||
DATA 4 0x021b0818 0x00011117 |
||||
DATA 4 0x021b4818 0x00011117 |
||||
DATA 4 0x021b0004 0x0002556D |
||||
DATA 4 0x021b0404 0x00011006 |
||||
DATA 4 0x021b001c 0x00000000 |
||||
|
||||
/* set the default clock gate to save power */ |
||||
DATA 4 0x020c4068 0x00C03F3F |
||||
DATA 4 0x020c406c 0x0030FC03 |
||||
DATA 4 0x020c4070 0x0FFFC000 |
||||
DATA 4 0x020c4074 0x3FF00000 |
||||
DATA 4 0x020c4078 0x00FFF300 |
||||
DATA 4 0x020c407c 0x0F0000C3 |
||||
DATA 4 0x020c4080 0x000003FF |
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */ |
||||
DATA 4 0x020e0010 0xF00000CF |
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
||||
DATA 4 0x020e0018 0x007F007F |
||||
DATA 4 0x020e001c 0x007F007F |
||||
@ -0,0 +1,4 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/cm_fx6/imximage.cfg,MX6QDL,SPL" |
||||
+S:CONFIG_ARM=y |
||||
+S:CONFIG_TARGET_CM_FX6=y |
||||
@ -1,3 +1,3 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL" |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL" |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_MX6SABRESD=y |
||||
|
||||
@ -0,0 +1,290 @@ |
||||
/*
|
||||
* Config file for Compulab CM-FX6 board |
||||
* |
||||
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
|
||||
* |
||||
* Author: Nikita Kiryanov <nikita@compulab.co.il> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_CM_FX6_H |
||||
#define __CONFIG_CM_FX6_H |
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
#include <config_distro_defaults.h> |
||||
#include "mx6_common.h" |
||||
|
||||
/* Machine config */ |
||||
#define CONFIG_MX6 |
||||
#define CONFIG_SYS_LITTLE_ENDIAN |
||||
#define CONFIG_MACH_TYPE 4273 |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/* Display information on boot */ |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
#define CONFIG_TIMESTAMP |
||||
|
||||
/* CMD */ |
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_CMD_GREPENV |
||||
#undef CONFIG_CMD_FLASH |
||||
#undef CONFIG_CMD_LOADB |
||||
#undef CONFIG_CMD_LOADS |
||||
#undef CONFIG_CMD_XIMG |
||||
#undef CONFIG_CMD_FPGA |
||||
#undef CONFIG_CMD_IMLS |
||||
|
||||
/* MMC */ |
||||
#define CONFIG_MMC |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_FSL_USDHC |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 3 |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR |
||||
|
||||
/* RAM */ |
||||
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR |
||||
#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR |
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_NR_DRAM_BANKS 2 |
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x10010000 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* Serial console */ |
||||
#define CONFIG_MXC_UART |
||||
#define CONFIG_MXC_UART_BASE UART4_BASE |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} |
||||
|
||||
/* Shell */ |
||||
#define CONFIG_SYS_PROMPT "CM-FX6 # " |
||||
#define CONFIG_SYS_CBSIZE 1024 |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
|
||||
/* SPI flash */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_CMD_SF |
||||
#define CONFIG_SF_DEFAULT_BUS 0 |
||||
#define CONFIG_SF_DEFAULT_CS 0 |
||||
#define CONFIG_SF_DEFAULT_SPEED 25000000 |
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) |
||||
|
||||
/* Environment */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED |
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE |
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS |
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS |
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024) |
||||
#define CONFIG_ENV_SIZE (8 * 1024) |
||||
#define CONFIG_ENV_OFFSET (768 * 1024) |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"kernel=uImage-cm-fx6\0" \
|
||||
"autoload=no\0" \
|
||||
"loadaddr=0x10800000\0" \
|
||||
"fdtaddr=0x11000000\0" \
|
||||
"console=ttymxc3,115200\0" \
|
||||
"ethprime=FEC0\0" \
|
||||
"bootscr=boot.scr\0" \
|
||||
"bootm_low=18000000\0" \
|
||||
"video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
|
||||
"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
|
||||
"fdtfile=cm-fx6.dtb\0" \
|
||||
"doboot=bootm ${loadaddr}\0" \
|
||||
"loadfdt=false\0" \
|
||||
"setboottypez=setenv kernel zImage-cm-fx6;" \
|
||||
"setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
|
||||
"setenv loadfdt true;\0" \
|
||||
"setboottypem=setenv kernel uImage-cm-fx6;" \
|
||||
"setenv doboot bootm ${loadaddr};" \
|
||||
"setenv loadfdt false;\0"\
|
||||
"run_eboot=echo Starting EBOOT ...; "\
|
||||
"mmc dev ${mmcdev} && " \
|
||||
"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
|
||||
"mmcdev=2\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
|
||||
"loadmmcbootscript=load mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \
|
||||
"mmcbootscript=echo Running bootscript from mmc ...; "\
|
||||
"source ${loadaddr}\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"root=${mmcroot} " \
|
||||
"${video}\0" \
|
||||
"mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
|
||||
"mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"run doboot\0" \
|
||||
"satadev=0\0" \
|
||||
"sataroot=/dev/sda2 rw rootwait\0" \
|
||||
"sataargs=setenv bootargs console=${console} " \
|
||||
"root=${sataroot} " \
|
||||
"${video}\0" \
|
||||
"loadsatabootscript=load sata ${satadev} ${loadaddr} ${bootscr}\0" \
|
||||
"satabootscript=echo Running bootscript from sata ...; " \
|
||||
"source ${loadaddr}\0" \
|
||||
"sataloadkernel=load sata ${satadev} ${loadaddr} ${kernel}\0" \
|
||||
"sataloadfdt=load sata ${satadev} ${fdtaddr} ${fdtfile}\0" \
|
||||
"sataboot=echo Booting from sata ...; "\
|
||||
"run sataargs; " \
|
||||
"run doboot\0" \
|
||||
"nandroot=/dev/mtdblock4 rw\0" \
|
||||
"nandrootfstype=ubifs\0" \
|
||||
"nandargs=setenv bootargs console=${console} " \
|
||||
"root=${nandroot} " \
|
||||
"rootfstype=${nandrootfstype} " \
|
||||
"${video}\0" \
|
||||
"nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"nand read ${loadaddr} 0 780000; " \
|
||||
"if ${loadfdt}; then " \
|
||||
"run nandloadfdt;" \
|
||||
"fi; " \
|
||||
"run doboot\0" \
|
||||
"boot=mmc dev ${mmcdev}; " \
|
||||
"if mmc rescan; then " \
|
||||
"if run loadmmcbootscript; then " \
|
||||
"run mmcbootscript;" \
|
||||
"else " \
|
||||
"if run mmcloadkernel; then " \
|
||||
"if ${loadfdt}; then " \
|
||||
"run mmcloadfdt;" \
|
||||
"fi;" \
|
||||
"run mmcboot;" \
|
||||
"fi;" \
|
||||
"fi;" \
|
||||
"fi;" \
|
||||
"if sata init; then " \
|
||||
"if run loadsatabootscript; then " \
|
||||
"run satabootscript;" \
|
||||
"else "\
|
||||
"if run sataloadkernel; then " \
|
||||
"if ${loadfdt}; then " \
|
||||
"run sataloadfdt; " \
|
||||
"fi;" \
|
||||
"run sataboot;" \
|
||||
"fi;" \
|
||||
"fi;" \
|
||||
"fi;" \
|
||||
"run nandboot\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"run setboottypem; run boot" |
||||
|
||||
/* SPI */ |
||||
#define CONFIG_SPI |
||||
#define CONFIG_MXC_SPI |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_ATMEL |
||||
#define CONFIG_SPI_FLASH_EON |
||||
#define CONFIG_SPI_FLASH_GIGADEVICE |
||||
#define CONFIG_SPI_FLASH_MACRONIX |
||||
#define CONFIG_SPI_FLASH_SPANSION |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
#define CONFIG_SPI_FLASH_SST |
||||
#define CONFIG_SPI_FLASH_WINBOND |
||||
|
||||
/* NAND */ |
||||
#ifndef CONFIG_SPL_BUILD |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_SYS_NAND_BASE 0x40000000 |
||||
#define CONFIG_SYS_NAND_MAX_CHIPS 1 |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_NAND_MXS |
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION |
||||
/* APBH DMA is required for NAND support */ |
||||
#define CONFIG_APBH_DMA |
||||
#define CONFIG_APBH_DMA_BURST |
||||
#define CONFIG_APBH_DMA_BURST8 |
||||
#endif |
||||
|
||||
/* Ethernet */ |
||||
#define CONFIG_FEC_MXC |
||||
#define CONFIG_FEC_MXC_PHYADDR 0 |
||||
#define CONFIG_FEC_XCV_TYPE RGMII |
||||
#define IMX_FEC_BASE ENET_BASE_ADDR |
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_PHY_ATHEROS |
||||
#define CONFIG_MII |
||||
#define CONFIG_ETHPRIME "FEC0" |
||||
#define CONFIG_ARP_TIMEOUT 200UL |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_NET_RETRY_COUNT 5 |
||||
|
||||
/* USB */ |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_MX6 |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
||||
#define CONFIG_MXC_USB_FLAGS 0 |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_MXC |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
#define CONFIG_SYS_MXC_I2C3_SPEED 400000 |
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_I2C_EEPROM_BUS 2 |
||||
|
||||
/* SATA */ |
||||
#define CONFIG_CMD_SATA |
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1 |
||||
#define CONFIG_LIBATA |
||||
#define CONFIG_LBA48 |
||||
#define CONFIG_DWC_AHSATA |
||||
#define CONFIG_DWC_AHSATA_PORT_ID 0 |
||||
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR |
||||
|
||||
/* GPIO */ |
||||
#define CONFIG_MXC_GPIO |
||||
|
||||
/* Boot */ |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK |
||||
#define CONFIG_LOADADDR 0x10800000 |
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_REVISION_TAG |
||||
#define CONFIG_SERIAL_TAG |
||||
|
||||
/* misc */ |
||||
#define CONFIG_SYS_GENERIC_BOARD |
||||
#define CONFIG_STACKSIZE (128 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) |
||||
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ |
||||
#define CONFIG_OF_BOARD_SETUP |
||||
|
||||
/* SPL */ |
||||
#include "imx6_spl.h" |
||||
#define CONFIG_SPL_BOARD_INIT |
||||
#define CONFIG_SPL_MMC_SUPPORT |
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 /* offset 64 kb */ |
||||
#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024) |
||||
#define CONFIG_SPL_SPI_SUPPORT |
||||
#define CONFIG_SPL_SPI_FLASH_SUPPORT |
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) |
||||
#define CONFIG_SPL_SPI_LOAD |
||||
|
||||
#endif /* __CONFIG_CM_FX6_H */ |
||||
Loading…
Reference in new issue