diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 7fe77ac..218dd6b 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -27,6 +27,10 @@ unsigned int shared_uart_com_port(const void *blob);
 unsigned int uart_com_port(const void *blob);
 #endif
 
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
+void socfpga_sdram_remap_zero(void);
+#endif
+
 void do_bridge_reset(int enable);
 
 #endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 848551c..429c3d6 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -175,6 +175,22 @@ static void socfpga_nic301_slave_ns(void)
 	writel(0x1, &nic301_regs->sdrdata);
 }
 
+void socfpga_sdram_remap_zero(void)
+{
+	socfpga_nic301_slave_ns();
+
+	/*
+	 * Private components security:
+	 * U-Boot : configure private timer, global timer and cpu component
+	 * access as non secure for kernel stage (as required by Linux)
+	 */
+	setbits_le32(&scu_regs->sacr, 0xfff);
+
+	/* Configure the L2 controller to make SDRAM start at 0 */
+	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
+	writel(0x1, &pl310->pl310_addr_filter_start);
+}
+
 static u32 iswgrp_handoff[8];
 
 int arch_early_init_r(void)
@@ -195,18 +211,7 @@ int arch_early_init_r(void)
 
 	socfpga_bridges_reset(1);
 
-	socfpga_nic301_slave_ns();
-
-	/*
-	 * Private components security:
-	 * U-Boot : configure private timer, global timer and cpu component
-	 * access as non secure for kernel stage (as required by Linux)
-	 */
-	setbits_le32(&scu_regs->sacr, 0xfff);
-
-	/* Configure the L2 controller to make SDRAM start at 0 */
-	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
-	writel(0x1, &pl310->pl310_addr_filter_start);
+	socfpga_sdram_remap_zero();
 
 	/* Add device descriptor to FPGA device table */
 	socfpga_fpga_add();
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 0e685f6..be318cc 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -5,7 +5,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/pl310.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
 #include <image.h>
@@ -17,8 +16,6 @@
 #include <asm/arch/misc.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/sdram.h>
-#include <asm/arch/scu.h>
-#include <asm/arch/nic301.h>
 #include <asm/sections.h>
 #include <debug_uart.h>
 #include <fdtdec.h>
@@ -26,12 +23,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
-	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct scu_registers *scu_regs =
-	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
-static struct nic301_registers *nic301_regs =
-	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 static const struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
@@ -72,16 +63,6 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
-static void socfpga_nic301_slave_ns(void)
-{
-	writel(0x1, &nic301_regs->lwhps2fpgaregs);
-	writel(0x1, &nic301_regs->hps2fpgaregs);
-	writel(0x1, &nic301_regs->acp);
-	writel(0x1, &nic301_regs->rom);
-	writel(0x1, &nic301_regs->ocram);
-	writel(0x1, &nic301_regs->sdrdata);
-}
-
 void board_init_f(ulong dummy)
 {
 	const struct cm_config *cm_default_cfg = cm_get_default_config();
@@ -103,14 +84,7 @@ void board_init_f(ulong dummy)
 
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
-	socfpga_nic301_slave_ns();
-
-	/* Configure ARM MPU SNSAC register. */
-	setbits_le32(&scu_regs->sacr, 0xfff);
-
-	/* Remap SDRAM to 0x0 */
-	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
-	writel(0x1, &pl310->pl310_addr_filter_start);
+	socfpga_sdram_remap_zero();
 
 	debug("Freezing all I/O banks\n");
 	/* freeze all IO banks */