@ -16,16 +16,16 @@
* This needs to be defined for the OHCI code to work but it is defined as
* ATMEL_ID_UHPHS in the CPU specific header files .
*/
# define ATMEL_ID_UHP ATMEL_ID_UHPHS
# define ATMEL_ID_UHP 32
/*
* Specify the clock enable bit in the PMC_SCER register .
*/
# define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
# define ATMEL_PMC_UHP (1 << 6)
/* SDRAM */
# define CONFIG_NR_DRAM_BANKS 1
# define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
# define CONFIG_SYS_SDRAM_BASE 0x20000000
# define CONFIG_SYS_SDRAM_SIZE 0x10000000
# ifdef CONFIG_SPL_BUILD
@ -39,7 +39,7 @@
# ifdef CONFIG_CMD_NAND
# define CONFIG_NAND_ATMEL
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
# define CONFIG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */
# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
@ -62,7 +62,7 @@
# define CONFIG_USB_ATMEL_CLK_SEL_UPLL
# define CONFIG_USB_OHCI_NEW
# define CONFIG_SYS_USB_OHCI_CPU_INIT
# define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000
# define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
# endif