From 5b47f2d92ba02a5dc2b31a677fd8150ad3c68b6a Mon Sep 17 00:00:00 2001 From: Oleksandr Tyshchenko Date: Tue, 6 Aug 2013 14:03:27 +0300 Subject: [PATCH 01/26] sdp4430: Initialize board id using CONFIG_MACH_TYPE Use CONFIG_MACH_TYPE generic macro to set the machine type number in the common arm code instead of setting it in the board code. Signed-off-by: Oleksandr Tyshchenko --- board/ti/sdp4430/sdp.c | 1 - include/configs/omap4_sdp4430.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 25daaa9..b20ca9e 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -28,7 +28,6 @@ int board_init(void) { gpmc_init(); - gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP; gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ return 0; diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 3da78b6..f40e0b7 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -17,6 +17,7 @@ * High Level Configuration Options */ #define CONFIG_4430SDP 1 /* working with SDP */ +#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP #include From 696f81f9a97d352651e2ffe970dc1d643d70dd19 Mon Sep 17 00:00:00 2001 From: Taras Kondratiuk Date: Tue, 6 Aug 2013 15:18:48 +0300 Subject: [PATCH 02/26] ARM: OMAP4470: Add OMAP4470 identification Signed-off-by: Taras Kondratiuk --- arch/arm/cpu/armv7/omap4/hwinit.c | 3 +++ arch/arm/include/asm/arch-omap4/omap.h | 1 + arch/arm/include/asm/omap_common.h | 1 + 3 files changed, 5 insertions(+) diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 4da0fc0..b0598a0 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -138,6 +138,9 @@ void init_omap_revision(void) break; case MIDR_CORTEX_A9_R2P10: switch (readl(CONTROL_ID_CODE)) { + case OMAP4470_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP4470_ES1_0; + break; case OMAP4460_CONTROL_ID_CODE_ES1_1: *omap_si_rev = OMAP4460_ES1_1; break; diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 3823a37..9129c0d 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -41,6 +41,7 @@ #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F +#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F /* UART */ #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 66f416f..5e2f027 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -622,6 +622,7 @@ static inline u8 is_omap54xx(void) #define OMAP4430_ES2_3 0x44300230 #define OMAP4460_ES1_0 0x44600100 #define OMAP4460_ES1_1 0x44600110 +#define OMAP4470_ES1_0 0x44700100 /* omap5 */ #define OMAP5430_SILICON_ID_INVALID 0 From 40aadf9201b6f9ee840ce09c06c3eebd26c67386 Mon Sep 17 00:00:00 2001 From: Taras Kondratiuk Date: Tue, 6 Aug 2013 15:18:49 +0300 Subject: [PATCH 03/26] ARM: OMAP4470: Add voltage and dpll data OMAP4470 reference design uses TWL6032 PMIC with a following connection scheme: VDD_CORE = TWL6032 SMPS2 VDD_MPU = TWL6032 SMPS1 VDD_IVA = TWL6032 SMPS5 Set voltage and frequency values according to OMAP4470 Data Manual Operating Condition Addendum v0.7 Signed-off-by: Taras Kondratiuk --- arch/arm/cpu/armv7/omap4/hw_data.c | 36 +++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap4/clock.h | 7 ++++++- 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 310df5a..6a225c8 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -50,6 +50,7 @@ static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { /* * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) * OMAP4430 OPP_TURBO frequency + * OMAP4470 OPP_NOM frequency */ static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -76,6 +77,7 @@ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { }; /* OMAP4460 OPP_NOM frequency */ +/* OMAP4470 OPP_NOM (Low Power) frequency */ static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ @@ -198,6 +200,20 @@ struct dplls omap4460_dplls = { .ddr = NULL }; +struct dplls omap4470_dplls = { + .mpu = mpu_dpll_params_1600mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + struct pmic_data twl6030_4430es1 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, .step = 12660, /* 12.66 mV represented in uV */ @@ -208,6 +224,7 @@ struct pmic_data twl6030_4430es1 = { .pmic_write = omap_vc_bypass_send_value, }; +/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */ struct pmic_data twl6030 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, .step = 12660, /* 12.66 mV represented in uV */ @@ -271,6 +288,20 @@ struct vcores_data omap4460_volts = { .mm.pmic = &twl6030, }; +struct vcores_data omap4470_volts = { + .mpu.value = 1200, + .mpu.addr = SMPS_REG_ADDR_SMPS1, + .mpu.pmic = &twl6030, + + .core.value = 1126, + .core.addr = SMPS_REG_ADDR_SMPS1, + .core.pmic = &twl6030, + + .mm.value = 1137, + .mm.addr = SMPS_REG_ADDR_SMPS1, + .mm.pmic = &twl6030, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -476,6 +507,11 @@ void hw_data_init(void) *omap_vcores = &omap4460_volts; break; + case OMAP4470_ES1_0: + *dplls_data = &omap4470_dplls; + *omap_vcores = &omap4470_volts; + break; + default: printf("\n INVALID OMAP REVISION "); } diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index b2e03d6..f3a682a 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -149,11 +149,16 @@ /* PRM_VC_VAL_BYPASS */ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 -/* SMPS */ +/* PMIC */ #define SMPS_I2C_SLAVE_ADDR 0x12 +/* TWL6030 SMPS */ #define SMPS_REG_ADDR_VCORE1 0x55 #define SMPS_REG_ADDR_VCORE2 0x5B #define SMPS_REG_ADDR_VCORE3 0x61 +/* TWL6032 SMPS */ +#define SMPS_REG_ADDR_SMPS1 0x55 +#define SMPS_REG_ADDR_SMPS2 0x5B +#define SMPS_REG_ADDR_SMPS5 0x49 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 From 81aee9723d03846736635d43507cbf0be5cd21d8 Mon Sep 17 00:00:00 2001 From: Lubomir Popov Date: Tue, 6 Aug 2013 15:18:50 +0300 Subject: [PATCH 04/26] ARM: OMAP4470: Add Elpida EDB8164B3PF memory configuration OMAP4470 SDP SoM has EDB8164B3PF PoP memory on board. This memory has 4Gb x 2CS = 8Gb configuration. Add configuration for runtime calculation and precalculated cases. Patch is based on a draft Lubomir's patch [1]. [1] http://lists.denx.de/pipermail/u-boot/2013-April/150851.html Signed-off-by: Lubomir Popov [taras@ti.com: cleaned up patch and fixed precalculated values] Signed-off-by: Taras Kondratiuk --- arch/arm/cpu/armv7/omap4/sdram_elpida.c | 41 +++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index d76dde7..67a7926 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -60,6 +60,20 @@ static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { .emif_ddr_phy_ctlr_1 = 0x049ff418 }; +const struct emif_regs emif_regs_elpida_400_mhz_1cs = { + .sdram_config_init = 0x80800eb2, + .sdram_config = 0x80801ab2, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3215, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + const struct emif_regs emif_regs_elpida_400_mhz_2cs = { .sdram_config_init = 0x80000eb9, .sdram_config = 0x80001ab9, @@ -107,8 +121,10 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_elpida_380_mhz_1cs; else if (omap4_rev == OMAP4430_ES2_0) *regs = &emif_regs_elpida_200_mhz_2cs; - else + else if (omap4_rev < OMAP4470_ES1_0) *regs = &emif_regs_elpida_400_mhz_2cs; + else + *regs = &emif_regs_elpida_400_mhz_1cs; } void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) __attribute__((weak, alias("emif_get_reg_dump_sdp"))); @@ -138,20 +154,31 @@ static const struct lpddr2_device_details elpida_2G_S4_details = { .manufacturer = LPDDR2_MANUFACTURER_ELPIDA }; +static const struct lpddr2_device_details elpida_4G_S4_details = { + .type = LPDDR2_TYPE_S4, + .density = LPDDR2_DENSITY_4Gb, + .io_width = LPDDR2_IO_WIDTH_32, + .manufacturer = LPDDR2_MANUFACTURER_ELPIDA +}; + struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs, struct lpddr2_device_details *lpddr2_dev_details) { u32 omap_rev = omap_revision(); /* EMIF1 & EMIF2 have identical configuration */ - if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) { - /* Nothing connected on CS1 for ES1.0 */ + if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) + && (cs == CS1)) { + /* Nothing connected on CS1 for 4430/4470 ES1.0 */ return NULL; - } else { - /* In all other cases Elpida 2G device */ + } else if (omap_rev < OMAP4470_ES1_0) { + /* In all other 4430/4460 cases Elpida 2G device */ *lpddr2_dev_details = elpida_2G_S4_details; - return lpddr2_dev_details; + } else { + /* 4470: 4G device */ + *lpddr2_dev_details = elpida_4G_S4_details; } + return lpddr2_dev_details; } struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, @@ -265,7 +292,7 @@ void emif_get_device_timings_sdp(u32 emif_nr, /* Identical devices on EMIF1 & EMIF2 */ *cs0_device_timings = &elpida_2G_S4_timings; - if (omap_rev == OMAP4430_ES1_0) + if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) *cs1_device_timings = NULL; else *cs1_device_timings = &elpida_2G_S4_timings; From e633ac019642689e3a2dd95bd644b3a10c7bbbb4 Mon Sep 17 00:00:00 2001 From: Taras Kondratiuk Date: Tue, 6 Aug 2013 15:18:51 +0300 Subject: [PATCH 05/26] ARM: OMAP4460: sdp: Limit TPS mux config to 4460 TPS mux config is 4460 specific, so it should be limited to 4460 only. Signed-off-by: Taras Kondratiuk --- board/ti/sdp4430/sdp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index b20ca9e..79270a9 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -65,7 +65,8 @@ void set_muxconf_regs_essential(void) sizeof(wkup_padconf_array_essential) / sizeof(struct pad_conf_entry)); - if (omap_revision() >= OMAP4460_ES1_0) + if ((omap_revision() >= OMAP4460_ES1_0) && + (omap_revision() < OMAP4470_ES1_0)) do_set_mux((*ctrl)->control_padconf_wkup_base, wkup_padconf_array_essential_4460, sizeof(wkup_padconf_array_essential_4460) / From 8d20836615eb7fa6330935a5f63e5cdd05cac7e5 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Sat, 10 Aug 2013 19:03:59 +0200 Subject: [PATCH 06/26] arm: omap3: fix SRAM copy and execution sequence Fix size calculation in copy of go_to_speed into SRAM. Use SRAM_CLK_CODE in call to SRAM-based go_to_speed. Signed-off-by: Albert ARIBAUD --- arch/arm/cpu/armv7/omap3/clock.c | 6 ++---- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 8 +++----- arch/arm/include/asm/arch-omap3/clock.h | 2 -- 3 files changed, 5 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index e903ed9..9f989ff 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -183,8 +183,7 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index) * if running from flash, jump to small relocated code * area in SRAM. */ - f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + - SRAM_VECT_CODE); + f_lock_pll = (void *) (SRAM_CLK_CODE); p0 = readl(&prcm_base->clken_pll); sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); @@ -401,8 +400,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index) * if running from flash, jump to small relocated code * area in SRAM. */ - f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + - SRAM_VECT_CODE); + f_lock_pll = (void *) (SRAM_CLK_CODE); p0 = readl(&prcm_base->clken_pll); sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 98c3c03..6f7261b 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -69,15 +69,13 @@ ENDPROC(do_omap3_emu_romcode_call) *************************************************************************/ ENTRY(cpy_clk_code) /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ + adr r0, go_to_speed /* copy from start of go_to_speed... */ + adr r2, lowlevel_init /* ... up to start of low_level_init */ next2: ldmia r0!, {r3 - r10} /* copy from source address [r0] */ stmia r1!, {r3 - r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ - bne next2 + blo next2 mov pc, lr /* back to caller */ ENDPROC(cpy_clk_code) diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h index 514839c..be669c1 100644 --- a/arch/arm/include/asm/arch-omap3/clock.h +++ b/arch/arm/include/asm/arch-omap3/clock.h @@ -63,6 +63,4 @@ extern dpll_param *get_36x_core_dpll_param(void); extern dpll_param *get_36x_per_dpll_param(void); extern dpll_param *get_36x_per2_dpll_param(void); -extern void *_end_vect, *_start; - #endif From 372d7fa1bf23a33066a8a88b6fb01ea931ae1b91 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sun, 11 Aug 2013 18:20:00 +0200 Subject: [PATCH 07/26] ARM: igep00x0.h: Enable raw initrd support Now that IGEP base boards default environment use the bootz command to boot a zImage instead of a uImage, it makes sense to add support to supply a raw initrd image to the kernel if needed. Signed-off-by: Javier Martinez Canillas --- include/configs/igep00x0.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 722c566..9982cf6 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -45,6 +45,7 @@ #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD /* * NS16550 Configuration From c27efde68dfd7fd2da364d556d586495e78d3396 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:43 -0400 Subject: [PATCH 08/26] am33xx: Correct and expand comments on CONFIG_SPL_MAX_SIZE We had been allowing the max size to be larger than actually allowed by the ROM. Expand the commentary here to explain why we set these locations. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/omap.h | 2 +- include/configs/ti_am335x_common.h | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 1f84311..2250721 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -18,7 +18,7 @@ #ifdef CONFIG_AM33XX #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 -#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 +#define SRAM_SCRATCH_SPACE_ADDR 0x4030B800 #elif defined(CONFIG_TI81XX) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index fd3ffab..0eae9c8 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -41,9 +41,15 @@ #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_NET_RETRY_COUNT 10 -/* SPL defines. */ +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x402F0400 and 0x4030B800 as a download area and + * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also + * supports X-MODEM loading via UART, and we leverage this and then use + * Y-MODEM to load u-boot.img, when booted over UART. + */ #define CONFIG_SPL_TEXT_BASE 0x402F0400 -#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_YMODEM_SUPPORT /* From a7142dd0963d44d446cf4be5ba710a04c2223e86 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:44 -0400 Subject: [PATCH 09/26] TI:armv7: Move CONFIG_SPL_LIBDISK_SUPPORT to MMC section We only need this library when we're doing "disk" access to MMC/SD. Update comment around the rest of CONFIG_SPL_LIB* to note that the others are always required. Signed-off-by: Tom Rini --- include/configs/ti_armv7_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index e0ab691..1e4bca5 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -223,14 +223,14 @@ #endif #ifdef CONFIG_MMC +#define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT #endif -/* General parts of the framework. */ +/* General parts of the framework, required. */ #define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT From c3799fceda6c37ad04bd62b6dd0db6225c11626b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:45 -0400 Subject: [PATCH 10/26] omap5: Expand CONFIG_SPL_MAX_SIZE and comment upon SRAM_SCRATCH_SPACE_ADDR After examining both TRMs and doing some experimentation, we can rely on using the start of the download area for CONFIG_SPL_TEXT_BASE and then move SRAM_SCRATCH_SPACE_ADDR up, just like am335x. This is required for peripheral boot modes such as UART. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap5/omap.h | 11 ++++++++++- include/configs/omap5_common.h | 4 ++-- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 597c692..e9a51d3 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -153,6 +153,15 @@ struct s32ktimer { #define EFUSE_4 0x45145100 #endif /* __ASSEMBLY__ */ +/* + * In all cases, the TRM defines the RAM Memory Map for the processor + * and indicates the area for the downloaded image. We use all of that + * space for download and once up and running may use other parts of the + * map for our needs. We set a scratch space that is at the end of the + * OMAP5 download area, but within the DRA7xx download area (as it is + * much larger) and do not, at this time, make use of the additional + * space. + */ #ifdef CONFIG_DRA7XX #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ @@ -160,7 +169,7 @@ struct s32ktimer { #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ #endif -#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START +#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000 /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 8e82fed..0345c57 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -128,8 +128,8 @@ /* Defines for SPL */ -#define CONFIG_SPL_TEXT_BASE 0x40300350 -#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */ +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" From a7a0640085ac7a47091471034553f9b619053654 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:46 -0400 Subject: [PATCH 11/26] TI:am335x: Better comment and organize the networking related options While in here, drop CONFIG_BOOTP_DEFAULT as it is unused in the code. Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 11 +++++++++-- include/configs/ti_am335x_common.h | 11 +++++------ 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index e0a87f8..5ed1dca 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -228,17 +228,24 @@ /* SPL */ #ifndef CONFIG_NOR_BOOT #define CONFIG_SPL_YMODEM_SUPPORT + +/* CPSW support */ +#define CONFIG_SPL_ETH_SUPPORT + +/* USB gadget RNDIS */ +#define CONFIG_SPL_MUSB_NEW_SUPPORT + +/* General network SPL, both CPSW and USB gadget RNDIS */ #define CONFIG_SPL_NET_SUPPORT #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" -#define CONFIG_SPL_ETH_SUPPORT + #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_BUS 0 #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 -#define CONFIG_SPL_MUSB_NEW_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" #ifdef CONFIG_NAND diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 0eae9c8..837c02c 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -28,18 +28,17 @@ #define CONFIG_SYS_NS16550_CLK 48000000 /* Network defines. */ -#define CONFIG_CMD_NET +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_DRIVER_TI_CPSW -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ /* * SPL related defines. The Public RAM memory map the ROM defines the From 610af383f13934f039e401e6adbee527ae645b06 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:47 -0400 Subject: [PATCH 12/26] am335x_evm: Add comment by SPL SPI support Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 5ed1dca..4e6429c 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -240,12 +240,14 @@ #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" +/* SPI flash. */ #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_BUS 0 #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" #ifdef CONFIG_NAND From 85a02aa9ccf3757c09e56e06926024cec6d9cfa0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:48 -0400 Subject: [PATCH 13/26] am335x_evm: Regroup USB options Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 80 +++++++++++++++++++++++--------------------- 1 file changed, 41 insertions(+), 39 deletions(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 4e6429c..eae5a19 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -171,44 +171,6 @@ "run mmcboot;" \ "run nandboot;" -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USB_GADGET -#define CONFIG_USBDOWNLOAD_GADGET - -/* USB TI's IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x0403 -#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 -#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" - -/* USB Device Firmware Update support */ -#define CONFIG_DFU_FUNCTION -#define CONFIG_DFU_MMC -#define CONFIG_CMD_DFU -#define DFU_ALT_INFO_MMC \ - "boot part 0 1;" \ - "rootfs part 0 2;" \ - "MLO fat 0 1;" \ - "MLO.raw mmc 100 100;" \ - "u-boot.img.raw mmc 300 400;" \ - "spl-os-args.raw mmc 80 80;" \ - "spl-os-image.raw mmc 900 2000;" \ - "spl-os-args fat 0 1;" \ - "spl-os-image fat 0 1;" \ - "u-boot.img fat 0 1;" \ - "uEnv.txt fat 0 1" -#ifdef CONFIG_NAND -#define CONFIG_DFU_NAND -#define DFU_ALT_INFO_NAND \ - "SPL part 0 1;" \ - "SPL.backup1 part 0 2;" \ - "SPL.backup2 part 0 3;" \ - "SPL.backup3 part 0 4;" \ - "u-boot part 0 5;" \ - "u-boot-spl-os part 0 6;" \ - "kernel part 0 8;" \ - "rootfs part 0 9" -#endif - /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ @@ -283,13 +245,19 @@ #endif /* - * USB configuration + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support and for gadget we add both RNDIS ethernet + * and DFU. */ #define CONFIG_USB_MUSB_DSPS #define CONFIG_ARCH_MISC_INIT #define CONFIG_MUSB_GADGET #define CONFIG_MUSB_PIO_ONLY #define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET +#define CONFIG_USBDOWNLOAD_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_MUSB_HOST @@ -307,6 +275,11 @@ #define CONFIG_USB_ETHER #define CONFIG_USB_ETH_RNDIS #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" + +/* USB TI's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0403 +#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 +#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" #endif /* CONFIG_MUSB_GADGET */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) @@ -318,6 +291,35 @@ #undef CONFIG_SPL_ETH_SUPPORT #endif +/* USB Device Firmware Update support */ +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_CMD_DFU +#define DFU_ALT_INFO_MMC \ + "boot part 0 1;" \ + "rootfs part 0 2;" \ + "MLO fat 0 1;" \ + "MLO.raw mmc 100 100;" \ + "u-boot.img.raw mmc 300 400;" \ + "spl-os-args.raw mmc 80 80;" \ + "spl-os-image.raw mmc 900 2000;" \ + "spl-os-args fat 0 1;" \ + "spl-os-image fat 0 1;" \ + "u-boot.img fat 0 1;" \ + "uEnv.txt fat 0 1" +#ifdef CONFIG_NAND +#define CONFIG_DFU_NAND +#define DFU_ALT_INFO_NAND \ + "SPL part 0 1;" \ + "SPL.backup1 part 0 2;" \ + "SPL.backup2 part 0 3;" \ + "SPL.backup3 part 0 4;" \ + "u-boot part 0 5;" \ + "u-boot-spl-os part 0 6;" \ + "kernel part 0 8;" \ + "rootfs part 0 9" +#endif + /* * Default to using SPI for environment, etc. * 0x000000 - 0x020000 : SPL (128KiB) From 1dd44e5a4a7ed4b723f2907eb832e65047107255 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:49 -0400 Subject: [PATCH 14/26] TI:armv7: Re-order slightly the generic CONFIG options, expand related comments Re-group the general options to note things that can be removed safely to reduce binary size when not required, and expand the comment about what commands we do include to note it could be replaced with a specific list of required one. While at it, move the CMD parts of various blocks IP to the end of the list for consistency. Signed-off-by: Tom Rini --- include/configs/ti_armv7_common.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 1e4bca5..e89e874 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -60,12 +60,12 @@ /* I2C IP block */ #define CONFIG_I2C -#define CONFIG_CMD_I2C #define CONFIG_HARD_I2C #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_I2C_MULTI_BUS #define CONFIG_DRIVER_OMAP24XX_I2C +#define CONFIG_CMD_I2C /* MMC/SD IP block */ #define CONFIG_MMC @@ -87,10 +87,10 @@ * access CS0 at is 0x8000000. */ #ifdef CONFIG_NAND -#define CONFIG_CMD_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_BASE 0x8000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_CMD_NAND #endif /* @@ -103,14 +103,18 @@ * console baudrate of 115200 and use the default baud rate table. */ #define CONFIG_SYS_MALLOC_LEN (1024 << 10) -#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_BAUDRATE 115200 +#define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */ +#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ + +/* As stated above, the following choices are optional. */ +#define CONFIG_SYS_LONGHELP #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_PROMPT "U-Boot# " #define CONFIG_VERSION_VARIABLE -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_BAUDRATE 115200 /* We set the max number of command args high to avoid HUSH bugs. */ #define CONFIG_SYS_MAXARGS 64 @@ -123,9 +127,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_CONSOLE_INFO_QUIET - /* * When we have SPI, NOR or NAND flash we expect to be making use of * mtdparts, both for ease of use in U-Boot and for passing information @@ -141,7 +142,8 @@ * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH * prior to this include, in order to skip a few commands. When we do * have flash, if we expect these commands they must be enabled in that - * config. + * config. If desired, a specific list of desired commands can be used + * instead. */ #include #define CONFIG_CMD_ASKENV From d7ccfc5bd66c6f873d292592bea7a8342b12016e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:50 -0400 Subject: [PATCH 15/26] am335x_evm: Update README for customization As this is a reference platform, update the README to note which IP blocks are required for use due to design choices of the reference rather than required by the SoC itself. Signed-off-by: Tom Rini --- board/ti/am335x/README | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/board/ti/am335x/README b/board/ti/am335x/README index 67b5246..2a30ab8 100644 --- a/board/ti/am335x/README +++ b/board/ti/am335x/README @@ -13,7 +13,33 @@ documented in TI's reference designs: - AM335x EVM SK - Beaglebone White - Beaglebone Black -' + +Customization +============= + +Given that all of the above boards are reference platforms (and the +Beaglebone platforms are OSHA), it is likely that this platform code and +configuration will be used as the basis of a custom platform. It is +worth noting that aside from things such as NAND or MMC only being +required if a custom platform makes use of these blocks, the following +are required, depending on design: + +- GPIO is only required if DDR3 power is controlled in a way similar to + EVM SK +- SPI is only required for SPI flash, or exposing the SPI bus. + +The following blocks are required: +- I2C, to talk with the PMIC and ensure that we do not run afoul of + errata 1.0.24. + +When removing options as part of customization, +CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your +needs and to remove no longer relevant options as in some cases we +define additional text blocks (such as for NAND or DFU strings). Also +note that all of the SPL options are grouped together, rather than with +the IP blocks, so both areas will need their choices updated to reflect +the custom design. + NAND ==== From 78c392f143260a5ea2a4cb1051eae13611858036 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:51 -0400 Subject: [PATCH 16/26] TI:am33xx: Move SPL YMODEM support to the per-board config Signed-off-by: Tom Rini --- include/configs/ti_am335x_common.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 837c02c..d2e34ae 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -49,7 +49,6 @@ */ #define CONFIG_SPL_TEXT_BASE 0x402F0400 #define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_YMODEM_SUPPORT /* * Since SPL did pll and ddr initialization for us, From 078aa4f1310f88aaf9727fc5eb0b493d4fe232a9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:52 -0400 Subject: [PATCH 17/26] TI:omap5: Clarify comments about SPL and DDR timings in common config Signed-off-by: Tom Rini --- include/configs/omap5_common.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 0345c57..98ba559 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -28,9 +28,12 @@ /* Use General purpose timer 1 */ #define CONFIG_SYS_TIMERBASE GPT2_BASE +/* + * For the DDR timing information we can either dynamically determine + * the timings to use or use pre-determined timings (based on using the + * dynamic method. Default to the static timing infomation. + */ #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - -/* Defines for SDRAM init */ #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS @@ -127,7 +130,13 @@ "fi" -/* Defines for SPL */ +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x40300000 and 0x4031E000 as a download area for OMAP5 + * (dra7xx is larger, but we do not need to be larger at this time). We + * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and + * print some information. + */ #define CONFIG_SPL_TEXT_BASE 0x40300000 #define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_DISPLAY_PRINT From 318aeb46493bb7f8b139aba6e084cb4bc2f70533 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:53 -0400 Subject: [PATCH 18/26] omap5_uevm: Better comment why we have TCA642X and the reset time Signed-off-by: Tom Rini --- include/configs/omap5_uevm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index d10c2b5..3948709 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -35,12 +35,15 @@ #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART +/* Required support for the TCA642X GPIO we have on the uEVM */ #define CONFIG_TCA642X #define CONFIG_CMD_TCA642X #define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 #define CONSOLEDEV "ttyO2" + +/* Max time to hold reset on this board, see doc/README.omap-reset-time */ #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 #include From 457bb50560c983fc69090dad1fb16b128e88a520 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:54 -0400 Subject: [PATCH 19/26] dra7xx_evm: Re-order and comment the networking related config options Signed-off-by: Tom Rini --- include/configs/dra7xx_evm.h | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 58786ff..4fbe768 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -26,21 +26,19 @@ #include /* CPSW Ethernet */ -#define CONFIG_CMD_NET +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII -#define CONFIG_DRIVER_TI_CPSW -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_NET_MULTI -#define CONFIG_PHY_GIGE +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_PHY_GIGE /* per-board part of CPSW */ #define CONFIG_PHYLIB #define CONFIG_PHY_ADDR 2 From dafd4db33a99f05616f02283f6fd3ba065278dcb Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 19 Aug 2013 16:38:56 +0200 Subject: [PATCH 20/26] arm, am33xx: add defines for gmii_sel_register bits Signed-off-by: Heiko Schocher Acked-by: Mugunthan V N --- arch/arm/include/asm/arch-am33xx/cpu.h | 19 +++++++++++++++++++ board/isee/igep0033/board.c | 6 ++---- board/phytec/pcm051/board.c | 2 -- board/ti/am335x/board.c | 6 +----- 4 files changed, 22 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 10b56e0..f77ac1e 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -486,6 +486,25 @@ struct ctrl_dev { unsigned int resv4[4]; unsigned int miisel; /* offset 0x50 */ }; + +/* gmii_sel register defines */ +#define GMII1_SEL_MII 0x0 +#define GMII1_SEL_RMII 0x1 +#define GMII1_SEL_RGMII 0x2 +#define GMII2_SEL_MII 0x0 +#define GMII2_SEL_RMII 0x4 +#define GMII2_SEL_RGMII 0x8 +#define RGMII1_IDMODE BIT(4) +#define RGMII2_IDMODE BIT(5) +#define RMII1_IO_CLK_EN BIT(6) +#define RMII2_IO_CLK_EN BIT(7) + +#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) +#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) +#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) +#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) +#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index a24c22b..9e91f68 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -27,9 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* MII mode defines */ -#define RMII_MODE_ENABLE 0x4D - static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; #ifdef CONFIG_SPL_BUILD @@ -158,7 +155,8 @@ int board_eth_init(bd_t *bis) eth_setenv_enetaddr("ethaddr", mac_addr); } - writel(RMII_MODE_ENABLE, &cdev->miisel); + writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN), + &cdev->miisel); rv = cpsw_register(&cpsw_data); if (rv < 0) diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index f53c5bb..e40b0bd 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -31,8 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; /* MII mode defines */ -#define MII_MODE_ENABLE 0x0 -#define RGMII_MODE_ENABLE 0xA #define RMII_RGMII2_MODE_ENABLE 0x49 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 04c37e2..cc04426 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -30,10 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* MII mode defines */ -#define MII_MODE_ENABLE 0x0 -#define RGMII_MODE_ENABLE 0x3A - /* GPIO that controls power to DDR on EVM-SK */ #define GPIO_DDR_VTT_EN 7 @@ -460,7 +456,7 @@ int board_eth_init(bd_t *bis) cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; } else { - writel(RGMII_MODE_ENABLE, &cdev->miisel); + writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; } From 14c0158b180c78b2e5482ae5c419862cfcf3226d Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 19 Aug 2013 16:38:57 +0200 Subject: [PATCH 21/26] arm, am335x: add some missing registers and defines for lcd and epwm support - add missing register defines in struct cm_perpl epwmss0clkctrl epwmss2clkctrl lcdcclkstctrl - add missing register defines in struct cm_dpll clklcdcpixelclk - add struct pwmss_regs - add struct pwmss_ecap_regs - add LCD Controller base LCD_CNTL_BASE - add PWM0 controller base PWMSS0_BASE Signed-off-by: Heiko Schocher Cc: Tom Rini --- arch/arm/include/asm/arch-am33xx/cpu.h | 35 +++++++++++++++++++++- arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 7 +++++ 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index f77ac1e..1835c89 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -193,7 +193,8 @@ struct cm_perpll { unsigned int dcan1clkctrl; /* offset 0xC4 */ unsigned int resv6[2]; unsigned int emiffwclkctrl; /* offset 0xD0 */ - unsigned int resv7[2]; + unsigned int epwmss0clkctrl; /* offset 0xD4 */ + unsigned int epwmss2clkctrl; /* offset 0xD8 */ unsigned int l3instrclkctrl; /* offset 0xDC */ unsigned int l3clkctrl; /* Offset 0xE0 */ unsigned int resv8[4]; @@ -204,6 +205,7 @@ struct cm_perpll { unsigned int l4hsclkctrl; /* offset 0x120 */ unsigned int resv10[8]; unsigned int cpswclkstctrl; /* offset 0x144 */ + unsigned int lcdcclkstctrl; /* offset 0x148 */ }; #else /* Encapsulating core pll registers */ @@ -366,6 +368,8 @@ struct cm_perpll { struct cm_dpll { unsigned int resv1[2]; unsigned int clktimer2clk; /* offset 0x08 */ + unsigned int resv2[10]; + unsigned int clklcdcpixelclk; /* offset 0x34 */ }; /* Control Module RTC registers */ @@ -505,6 +509,35 @@ struct ctrl_dev { #define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) #define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) +/* PWMSS */ +struct pwmss_regs { + unsigned int idver; + unsigned int sysconfig; + unsigned int clkconfig; + unsigned int clkstatus; +}; +#define ECAP_CLK_EN BIT(0) +#define ECAP_CLK_STOP_REQ BIT(1) + +struct pwmss_ecap_regs { + unsigned int tsctr; + unsigned int ctrphs; + unsigned int cap1; + unsigned int cap2; + unsigned int cap3; + unsigned int cap4; + unsigned int resv1[4]; + unsigned short ecctl1; + unsigned short ecctl2; +}; + +/* Capture Control register 2 */ +#define ECTRL2_SYNCOSEL_MASK (0x03 << 6) +#define ECTRL2_MDSL_ECAP BIT(9) +#define ECTRL2_CTRSTP_FREERUN BIT(4) +#define ECTRL2_PLSL_LOW BIT(10) +#define ECTRL2_SYNC_EN BIT(5) + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index 8973fd8..e4231c8 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -58,4 +58,11 @@ #define USB0_OTG_BASE 0x47401000 #define USB1_OTG_BASE 0x47401800 +/* LCD Controller */ +#define LCD_CNTL_BASE 0x4830E000 + +/* PWMSS */ +#define PWMSS0_BASE 0x48300000 +#define AM33XX_ECAP0_BASE 0x48300100 + #endif /* __AM33XX_HARDWARE_AM33XX_H */ From a09f96498bb2a31bb78388b5f094dc0e9295f86e Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 19 Aug 2013 16:38:58 +0200 Subject: [PATCH 22/26] arm, spl: add watchdog library to SPL Signed-off-by: Heiko Schocher Cc: Tom Rini --- doc/README.SPL | 2 +- spl/Makefile | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/doc/README.SPL b/doc/README.SPL index ac9a213..312a6a6 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -67,7 +67,7 @@ CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o) CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o) CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o) CONFIG_SPL_RAM_DEVICE (common/spl/spl.c) - +CONFIG_SPL_WATCHDOG_SUPPORT (drivers/watchdog/libwatchdog.o) Normally CPU is assumed to be the same between the SPL and normal u-boot build. However it is possible to specify a different CPU for diff --git a/spl/Makefile b/spl/Makefile index 28ebc96..003558c 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -82,6 +82,7 @@ LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o +LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/libwatchdog.o ifneq ($(CONFIG_OMAP_COMMON),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o From 988ea355018a7060768b8e6ddcee1ffa7cf6351b Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 19 Aug 2013 16:38:59 +0200 Subject: [PATCH 23/26] arm, am335x: add watchdog support Add TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog support. Signed-off-by: Heiko Schocher Reviewed-by: Tom Rini Cc: Albert Aribaud --- arch/arm/include/asm/arch-am33xx/cpu.h | 20 ++++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/omap_wdt.c | 121 +++++++++++++++++++++++++++++++++ 3 files changed, 142 insertions(+) create mode 100644 drivers/watchdog/omap_wdt.c diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 1835c89..73e6db8 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -46,6 +46,26 @@ #define PRM_RSTCTRL_RESET 0x01 #define PRM_RSTST_WARM_RESET_MASK 0x232 +/* + * Watchdog: + * Using the prescaler, the OMAP watchdog could go for many + * months before firing. These limits work without scaling, + * with the 60 second default assumed by most tools and docs. + */ +#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */ +#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */ +#define TIMER_MARGIN_MIN 1 + +#define PTV 0 /* prescale */ +#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1< + * Date: Mon Nov 19 13:21:41 2012 -0500 + * + * watchdog: remove use of __devinit + * + * CONFIG_HOTPLUG is going away as an option so __devinit is no longer + * needed. + * + * Author: MontaVista Software, Inc. + * or + * + * History: + * + * 20030527: George G. Davis + * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c + * (c) Copyright 2000 Oleg Drokin + * Based on SoftDog driver by Alan Cox + * + * Copyright (c) 2004 Texas Instruments. + * 1. Modified to support OMAP1610 32-KHz watchdog timer + * 2. Ported to 2.6 kernel + * + * Copyright (c) 2005 David Brownell + * Use the driver model and standard identifiers; handle bigger timeouts. + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware timeout in seconds */ +#define WDT_HW_TIMEOUT 60 + +static unsigned int wdt_trgr_pattern = 0x1234; + +void hw_watchdog_reset(void) +{ + struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; + + /* wait for posted write to complete */ + while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR) + ; + + wdt_trgr_pattern = ~wdt_trgr_pattern; + writel(wdt_trgr_pattern, &wdt->wdtwtgr); + + /* wait for posted write to complete */ + while ((readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WTGR)) + ; +} + +static int omap_wdt_set_timeout(unsigned int timeout) +{ + struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; + u32 pre_margin = GET_WLDR_VAL(timeout); + + /* just count up at 32 KHz */ + while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) + ; + + writel(pre_margin, &wdt->wdtwldr); + while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) + ; + + return 0; +} + +void hw_watchdog_init(void) +{ + struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; + + /* initialize prescaler */ + while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) + ; + + writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &wdt->wdtwclr); + while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) + ; + + omap_wdt_set_timeout(WDT_HW_TIMEOUT); + + /* Sequence to enable the watchdog */ + writel(0xBBBB, &wdt->wdtwspr); + while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) + ; + + writel(0x4444, &wdt->wdtwspr); + while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) + ; +} + +void hw_watchdog_disable(void) +{ + struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; + + /* + * Disable watchdog + */ + writel(0xAAAA, &wdt->wdtwspr); + while (readl(&wdt->wdtwwps) != 0x0) + ; + writel(0x5555, &wdt->wdtwspr); + while (readl(&wdt->wdtwwps) != 0x0) + ; +} From b26354cfd5371759f93224b8b69335e160bcc686 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 19 Aug 2013 16:39:00 +0200 Subject: [PATCH 24/26] video: add formike lcd panel init Signed-off-by: Heiko Schocher Cc: Anatolij Gustschin Cc: Tom Rini Acked-by: Anatolij Gustschin --- drivers/video/Makefile | 1 + drivers/video/formike.c | 511 ++++++++++++++++++++++++++++++++++++++++++++++++ include/video.h | 4 + 3 files changed, 516 insertions(+) create mode 100644 drivers/video/formike.c diff --git a/drivers/video/Makefile b/drivers/video/Makefile index f1fb26c..ede1d1a 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_VIDEO_SM501) += sm501.o COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o COBJS-$(CONFIG_VIDEO_TEGRA) += tegra.o COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o +COBJS-$(CONFIG_FORMIKE) += formike.o COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) diff --git a/drivers/video/formike.c b/drivers/video/formike.c new file mode 100644 index 0000000..b9b6822 --- /dev/null +++ b/drivers/video/formike.c @@ -0,0 +1,511 @@ +/* + * LCD: Formike, TFT 4.3", 480x800, RGB24, KWH043ST20-F01, DriverIC NT35510-16 + * LCD initialization via SPI + * + * SPDX-License-Identifier: GPL-2.0 + * Based on: + * + */ +#include +#include +#include + +#define TAG_READ 0x80 +#define TAG_WRITE 0x00 + +#define TAG_DATA 0x40 +#define TAG_COMMAND 0x00 + +#define TAG_ADDR_H 0x20 +#define TAG_ADDR_L 0x00 + +static int spi_write_tag_val(struct spi_slave *spi, unsigned char tag, + unsigned char val) +{ + unsigned long flags = SPI_XFER_BEGIN; + u8 buf[2]; + int ret; + + buf[0] = tag; + buf[1] = val; + flags |= SPI_XFER_END; + + ret = spi_xfer(spi, 16, buf, NULL, flags); +#ifdef KWH043ST20_F01_SPI_DEBUG + printf("spi_write_tag_val: tag=%02X, val=%02X ret: %d\n", + tag, val, ret); +#endif /* KWH043ST20_F01_SPI_DEBUG */ + if (ret) + debug("%s: Failed to send: %d\n", __func__, ret); + + return ret; +} + +static void spi_write_dat(struct spi_slave *spi, unsigned int val) +{ + spi_write_tag_val(spi, TAG_WRITE|TAG_DATA, val); +} + +static void spi_write_com(struct spi_slave *spi, unsigned int addr) +{ + spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_H, + (addr & 0xff00) >> 8); + spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_L, + (addr & 0x00ff) >> 0); +} + +int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *spi; + int ret; + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + debug("%s: Failed to set up slave\n", __func__); + return -1; + } + + ret = spi_claim_bus(spi); + if (ret) { + debug("%s: Failed to claim SPI bus: %d\n", __func__, ret); + goto err_claim_bus; + } + + + /* LV2 Page 1 enable */ + spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55); + spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA); + spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52); + spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x01); + + /* AVDD Set AVDD 5.2V */ + spi_write_com(spi, 0xB000); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB001); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB002); spi_write_dat(spi, 0x0D); + + /* AVDD ratio */ + spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB601); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB602); spi_write_dat(spi, 0x34); + + /* AVEE -5.2V */ + spi_write_com(spi, 0xB100); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB102); spi_write_dat(spi, 0x0D); + + /* AVEE ratio */ + spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x35); + spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x35); + spi_write_com(spi, 0xB702); spi_write_dat(spi, 0x35); + + /* VCL -2.5V */ + spi_write_com(spi, 0xB200); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xB201); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xB202); spi_write_dat(spi, 0x00); + + /* VCL ratio */ + spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x24); + + /* VGH 15V */ + spi_write_com(spi, 0xBF00); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xB300); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xB301); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xB302); spi_write_dat(spi, 0x08); + + /* VGH ratio */ + spi_write_com(spi, 0xB900); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB901); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB902); spi_write_dat(spi, 0x34); + + /* VGLX ratio */ + spi_write_com(spi, 0xBA00); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xBA01); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xBA02); spi_write_dat(spi, 0x24); + + /* VGMP/VGSP 4.7V/0V */ + spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x88); + spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00); + + /* VGMN/VGSN -4.7V/0V */ + spi_write_com(spi, 0xBD00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBD01); spi_write_dat(spi, 0x88); + spi_write_com(spi, 0xBD02); spi_write_dat(spi, 0x00); + + /* VCOM 1.525V */ + spi_write_com(spi, 0xBE00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBE01); spi_write_dat(spi, 0x7A); + + /* Gamma Setting */ + spi_write_com(spi, 0xD100); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD101); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD102); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD103); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD104); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD105); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD106); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD107); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD108); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD109); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD10A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD10B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD10C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD10D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD10E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD10F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD110); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD111); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD112); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD113); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD114); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD115); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD116); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD117); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD118); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD119); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD11A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD11B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD11C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD11D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD11E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD11F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD120); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD121); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD122); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD123); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD124); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD125); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD126); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD127); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD128); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD129); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD12A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD12B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD12C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD12D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD12E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD12F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD130); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD131); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD132); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD133); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD200); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD201); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD202); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD203); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD204); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD205); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD206); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD207); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD208); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD209); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD20A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD20B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD20C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD20D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD20E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD20F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD210); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD211); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD212); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD213); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD214); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD215); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD216); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD217); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD218); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD219); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD21A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD21B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD21C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD21D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD21E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD21F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD220); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD221); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD222); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD223); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD224); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD225); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD226); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD227); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD228); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD229); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD22A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD22B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD22C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD22D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD22E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD22F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD230); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD231); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD232); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD233); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD300); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD301); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD302); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD303); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD304); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD305); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD306); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD307); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD308); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD309); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD30A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD30B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD30C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD30D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD30E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD30F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD310); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD311); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD312); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD313); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD314); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD315); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD316); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD317); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD318); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD319); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD31A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD31B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD31C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD31D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD31E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD31F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD320); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD321); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD322); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD323); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD324); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD325); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD326); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD327); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD328); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD329); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD32A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD32B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD32C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD32D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD32E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD32F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD330); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD331); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD332); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD333); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD400); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD401); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD402); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD403); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD404); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD405); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD406); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD407); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD408); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD409); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD40A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD40B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD40C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD40D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD40E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD40F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD410); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD411); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD412); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD413); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD414); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD415); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD416); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD417); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD418); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD419); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD41A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD41B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD41C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD41D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD41E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD41F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD420); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD421); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD422); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD423); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD424); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD425); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD426); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD427); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD428); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD429); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD42A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD42B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD42C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD42D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD42E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD42F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD430); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD431); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD432); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD433); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD500); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD501); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD502); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD503); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD504); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD505); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD506); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD507); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD508); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD509); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD50A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD50B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD50C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD50D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD50E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD50F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD510); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD511); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD512); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD513); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD514); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD515); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD516); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD517); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD518); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD519); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD51A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD51B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD51C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD51D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD51E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD51F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD520); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD521); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD522); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD523); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD524); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD525); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD526); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD527); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD528); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD529); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD52A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD52B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD52C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD52D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD52E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD52F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD530); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD531); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD532); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD533); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD600); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD601); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD602); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD603); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD604); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD605); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD606); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD607); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD608); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD609); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD60A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD60B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD60C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD60D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD60E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD60F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD610); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD611); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD612); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD613); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD614); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD615); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD616); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD617); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD618); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD619); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD61A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD61B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD61C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD61D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD61E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD61F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD620); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD621); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD622); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD623); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD624); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD625); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD626); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD627); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD628); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD629); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD62A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD62B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD62C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD62D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD62E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD62F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD630); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD631); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD632); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD633); spi_write_dat(spi, 0xFF); + + /* LV2 Page 0 enable */ + spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55); + spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA); + spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52); + spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x00); + + /* Display control */ + spi_write_com(spi, 0xB100); spi_write_dat(spi, 0xFC); + spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x00); + + /* Source hold time */ + spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x05); + + /* Gate EQ control */ + spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x70); + spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x70); + + /* Source EQ control (Mode 2) */ + spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xB803); spi_write_dat(spi, 0x05); + + /* Inversion mode (Column) */ + spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00); + + /* Timing control 8phase dual side/4H/4delay/RST_EN */ + spi_write_com(spi, 0xC900); spi_write_dat(spi, 0xD0); + spi_write_com(spi, 0xC901); spi_write_dat(spi, 0x82); + spi_write_com(spi, 0xC902); spi_write_dat(spi, 0x50); + spi_write_com(spi, 0xC903); spi_write_dat(spi, 0x50); + spi_write_com(spi, 0xC904); spi_write_dat(spi, 0x50); + + spi_write_com(spi, 0x3A00); spi_write_dat(spi, 0x55); + mdelay(120); + spi_write_com(spi, 0x1100); + mdelay(120); + spi_write_com(spi, 0x2900); + mdelay(120); + /* spi_write_com(spi, 0x2100); spi_write_dat(spi, 0x00); */ + spi_write_com(spi, 0x2C00); + + return 0; +err_claim_bus: + spi_free_slave(spi); + return -1; +} diff --git a/include/video.h b/include/video.h index f7e27f8..0ff857b 100644 --- a/include/video.h +++ b/include/video.h @@ -63,4 +63,8 @@ void video_position_cursor(unsigned col, unsigned row); /* Clear the display */ void video_clear(void); +#if defined(CONFIG_FORMIKE) +int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); +#endif #endif From c0dcece7d9925506a950e45028cbd25614aad791 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 19 Aug 2013 16:39:01 +0200 Subject: [PATCH 25/26] arm, am335x: add support for 3 siemens boards add support for the am335x based boards from siemens: dxr2: - DDR3 128MiB - NAND 256MiB - Ethernet with external Switch SMSC LAN9303 - no PMIC - internal Watchdog - DFU support pxm2: - DDR2 512 MiB - NAND 1024 MiB - PMIC - PHY atheros ar803x - USB Host - internal Watchdog - DFU support rut: - DDR3 256 MiB - NAND 256 MiB - PMIC - PHY natsemi dp83630 - external Watchdog - DFU support Signed-off-by: Heiko Schocher Signed-off-by: Roger Meier Signed-off-by: Samuel Egli Cc: Pascal Bach Cc: Tom Rini --- MAINTAINERS | 5 + board/siemens/common/board.c | 171 ++++++++++++ board/siemens/common/factoryset.c | 284 ++++++++++++++++++++ board/siemens/common/factoryset.h | 27 ++ board/siemens/dxr2/Makefile | 49 ++++ board/siemens/dxr2/board.c | 241 +++++++++++++++++ board/siemens/dxr2/board.h | 69 +++++ board/siemens/dxr2/mux.c | 112 ++++++++ board/siemens/pxm2/Makefile | 49 ++++ board/siemens/pxm2/board.c | 429 ++++++++++++++++++++++++++++++ board/siemens/pxm2/board.h | 22 ++ board/siemens/pxm2/mux.c | 186 +++++++++++++ board/siemens/pxm2/pmic.h | 71 +++++ board/siemens/rut/Makefile | 49 ++++ board/siemens/rut/board.c | 432 ++++++++++++++++++++++++++++++ board/siemens/rut/board.h | 22 ++ board/siemens/rut/mux.c | 347 ++++++++++++++++++++++++ boards.cfg | 3 + include/configs/dxr2.h | 94 +++++++ include/configs/pxm2.h | 153 +++++++++++ include/configs/rut.h | 156 +++++++++++ include/configs/siemens-am33x-common.h | 463 +++++++++++++++++++++++++++++++++ tools/logos/siemens.bmp | Bin 0 -> 25766 bytes 23 files changed, 3434 insertions(+) create mode 100644 board/siemens/common/board.c create mode 100644 board/siemens/common/factoryset.c create mode 100644 board/siemens/common/factoryset.h create mode 100644 board/siemens/dxr2/Makefile create mode 100644 board/siemens/dxr2/board.c create mode 100644 board/siemens/dxr2/board.h create mode 100644 board/siemens/dxr2/mux.c create mode 100644 board/siemens/pxm2/Makefile create mode 100644 board/siemens/pxm2/board.c create mode 100644 board/siemens/pxm2/board.h create mode 100644 board/siemens/pxm2/mux.c create mode 100644 board/siemens/pxm2/pmic.h create mode 100644 board/siemens/rut/Makefile create mode 100644 board/siemens/rut/board.c create mode 100644 board/siemens/rut/board.h create mode 100644 board/siemens/rut/mux.c create mode 100644 include/configs/dxr2.h create mode 100644 include/configs/pxm2.h create mode 100644 include/configs/rut.h create mode 100644 include/configs/siemens-am33x-common.h create mode 100644 tools/logos/siemens.bmp diff --git a/MAINTAINERS b/MAINTAINERS index 23965a8..d4af7bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1087,6 +1087,11 @@ Sergey Yanovich lp8x4x xscale/pxa +Roger Meier + dxr2 ARM ARMV7 (AM335x SoC) + pxm2 ARM ARMV7 (AM335x SoC) + rut ARM ARMV7 (AM335x SoC) + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c new file mode 100644 index 0000000..6279c32 --- /dev/null +++ b/board/siemens/common/board.c @@ -0,0 +1,171 @@ +/* + * Common board functions for siemens AM335X based boards + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/board/ti/am335x/board.c + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/factoryset.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + /* Initalize the board header */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + enable_board_pin_mux(); +} + +void sdram_init(void) +{ + spl_siemens_board_init(); + board_init_ddr(); + + return; +} +#endif /* #ifdef CONFIG_SPL_BUILD */ + +#ifndef CONFIG_SPL_BUILD +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif /* defined(CONFIG_HW_WATCHDOG) */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_FACTORYSET + factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR); +#endif + gpmc_init(); + +#ifdef CONFIG_VIDEO + board_video_init(); +#endif + + return 0; +} +#endif /* #ifndef CONFIG_SPL_BUILD */ + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + DDR_PLL_FREQ, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + omap_nand_switch_ecc(1, 8); + + return 0; +} +#endif + +#ifndef CONFIG_SPL_BUILD +#if defined(BOARD_DFU_BUTTON_GPIO) +/* + * This command returns the status of the user button on + * Input - none + * Returns - 1 if button is held down + * 0 if button is not held down + */ +static int +do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int button = 0; + int gpio; + + gpio = BOARD_DFU_BUTTON_GPIO; + gpio_request(gpio, "DFU"); + gpio_direction_input(gpio); + if (gpio_get_value(gpio)) + button = 1; + else + button = 0; + + gpio_free(gpio); + if (!button) { + /* LED0 - RED=1: GPIO2_0 2*32 = 64 */ + gpio_request(BOARD_DFU_BUTTON_LED, ""); + gpio_direction_output(BOARD_DFU_BUTTON_LED, 1); + gpio_set_value(BOARD_DFU_BUTTON_LED, 1); + } + + return button; +} + +U_BOOT_CMD( + dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton, + "Return the status of the DFU button", + "" +); +#endif + +static int +do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + printf("\n\n\n Go into infinite loop\n\n\n"); + while (1) + ; + return 0; +}; + +U_BOOT_CMD( + testwdt, CONFIG_SYS_MAXARGS, 1, do_usertestwdt, + "Sends U-Boot into infinite loop", + "" +); + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + printf("Enable d-cache\n"); + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif /* CONFIG_SYS_DCACHE_OFF */ +#endif /* !CONFIG_SPL_BUILD */ diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c new file mode 100644 index 0000000..eda9141 --- /dev/null +++ b/board/siemens/common/factoryset.c @@ -0,0 +1,284 @@ +/* + * + * Read FactorySet information from EEPROM into global structure. + * (C) Copyright 2013 Siemens Schweiz AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#if !defined(CONFIG_SPL_BUILD) + +#include +#include +#include +#include +#include +#include +#include +#include +#include "factoryset.h" + +#define EEPR_PG_SZ 0x80 +#define EEPROM_FATORYSET_OFFSET 0x400 +#define OFF_PG EEPROM_FATORYSET_OFFSET/EEPR_PG_SZ + +/* Global variable that contains necessary information from FactorySet */ +struct factorysetcontainer factory_dat; + +#define fact_get_char(i) *((char *)&eeprom_buf[i]) + +static int fact_match(unsigned char *eeprom_buf, uchar *s1, int i2) +{ + if (s1 == NULL) + return -1; + + while (*s1 == fact_get_char(i2++)) + if (*s1++ == '=') + return i2; + + if (*s1 == '\0' && fact_get_char(i2-1) == '=') + return i2; + + return -1; +} + +static int get_factory_val(unsigned char *eeprom_buf, int size, uchar *name, + uchar *buf, int len) +{ + int i, nxt = 0; + + for (i = 0; fact_get_char(i) != '\0'; i = nxt + 1) { + int val, n; + + for (nxt = i; fact_get_char(nxt) != '\0'; ++nxt) { + if (nxt >= size) + return -1; + } + + val = fact_match(eeprom_buf, (uchar *)name, i); + if (val < 0) + continue; + + /* found; copy out */ + for (n = 0; n < len; ++n, ++buf) { + *buf = fact_get_char(val++); + if (*buf == '\0') + return n; + } + + if (n) + *--buf = '\0'; + + printf("env_buf [%d bytes] too small for value of \"%s\"\n", + len, name); + + return n; + } + return -1; +} + +static +int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record, + uchar *name, uchar *buf, int len) +{ + int ret = -1; + int i, nxt = 0; + int c; + unsigned char end = 0xff; + + for (i = 0; fact_get_char(i) != end; i = nxt) { + nxt = i + 1; + if (fact_get_char(i) == '>') { + int pos; + int endpos; + int z; + + c = strncmp((char *)&eeprom_buf[i + 1], (char *)record, + strlen((char *)record)); + if (c == 0) { + /* record found */ + pos = i + strlen((char *)record) + 2; + nxt = pos; + /* search for "<" */ + c = -1; + for (z = pos; fact_get_char(z) != end; z++) { + if ((fact_get_char(z) == '<') || + (fact_get_char(z) == '>')) { + endpos = z; + nxt = endpos; + c = 0; + break; + } + } + } + if (c == 0) { + /* end found -> call get_factory_val */ + eeprom_buf[endpos] = end; + ret = get_factory_val(&eeprom_buf[pos], + size - pos, name, buf, len); + /* fix buffer */ + eeprom_buf[endpos] = '<'; + debug("%s: %s.%s = %s\n", + __func__, record, name, buf); + return ret; + } + } + } + return ret; +} + +int factoryset_read_eeprom(int i2c_addr) +{ + int i, pages = 0, size = 0; + unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH]; + unsigned char *cp, *cp1; + +#if defined(CONFIG_DFU_FUNCTION) + factory_dat.usb_vendor_id = CONFIG_G_DNL_VENDOR_NUM; + factory_dat.usb_product_id = CONFIG_G_DNL_PRODUCT_NUM; +#endif + if (i2c_probe(i2c_addr)) + goto err; + + if (i2c_read(i2c_addr, EEPROM_FATORYSET_OFFSET, 2, hdr, sizeof(hdr))) + goto err; + + if ((hdr[0] != 0x99) || (hdr[1] != 0x80)) { + printf("FactorySet is not right in eeprom.\n"); + return 1; + } + + /* get FactorySet size */ + size = (hdr[2] << 8) + hdr[3] + sizeof(hdr); + if (size > 0x3bfa) + size = 0x3bfa; + + pages = size / EEPR_PG_SZ; + + /* + * read the eeprom using i2c + * I can not read entire eeprom in once, so separate into several + * times. Furthermore, fetch eeprom take longer time, so we fetch + * data after every time we got a record from eeprom + */ + debug("Read eeprom page :\n"); + for (i = 0; i < pages; i++) + if (i2c_read(i2c_addr, (OFF_PG + i) * EEPR_PG_SZ, 2, + eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ)) + goto err; + + if (size % EEPR_PG_SZ) + if (i2c_read(i2c_addr, (OFF_PG + pages) * EEPR_PG_SZ, 2, + eeprom_buf + (pages * EEPR_PG_SZ), + (size % EEPR_PG_SZ))) + goto err; + + /* we do below just for eeprom align */ + for (i = 0; i < size; i++) + if (eeprom_buf[i] == '\n') + eeprom_buf[i] = 0; + + /* skip header */ + size -= sizeof(hdr); + cp = (uchar *)eeprom_buf + sizeof(hdr); + + /* get mac address */ + get_factory_record_val(cp, size, (uchar *)"ETH1", (uchar *)"mac", + buf, MAX_STRING_LENGTH); + cp1 = buf; + for (i = 0; i < 6; i++) { + factory_dat.mac[i] = simple_strtoul((char *)cp1, NULL, 16); + cp1 += 3; + } + +#if defined(CONFIG_DFU_FUNCTION) + /* read vid and pid for dfu mode */ + if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1", + (uchar *)"vid", buf, + MAX_STRING_LENGTH)) { + factory_dat.usb_vendor_id = simple_strtoul((char *)buf, + NULL, 16); + } + + if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1", + (uchar *)"pid", buf, + MAX_STRING_LENGTH)) { + factory_dat.usb_product_id = simple_strtoul((char *)buf, + NULL, 16); + } + printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id, + factory_dat.usb_product_id); +#endif + if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV", + (uchar *)"id", buf, + MAX_STRING_LENGTH)) { + if (strncmp((const char *)buf, "PXM50", 5) == 0) + factory_dat.pxm50 = 1; + else + factory_dat.pxm50 = 0; + } + debug("PXM50: %d\n", factory_dat.pxm50); +#if defined(CONFIG_VIDEO) + if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1", + (uchar *)"name", factory_dat.disp_name, + MAX_STRING_LENGTH)) { + debug("display name: %s\n", factory_dat.disp_name); + } + +#endif + return 0; + +err: + printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return 1; +} + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static int factoryset_mac_setenv(void) +{ + uint8_t mac_addr[6]; + + debug("FactorySet: Set mac address\n"); + if (is_valid_ether_addr(factory_dat.mac)) { + memcpy(mac_addr, factory_dat.mac, 6); + } else { + uint32_t mac_hi, mac_lo; + + debug("Warning: FactorySet: not set. Fallback to E-fuse\n"); + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + if (!is_valid_ether_addr(mac_addr)) { + printf("Warning: ethaddr not set by FactorySet or E-fuse. Set variable to overcome this.\n"); + return -1; + } + } + + eth_setenv_enetaddr("ethaddr", mac_addr); + return 0; +} + +int factoryset_setenv(void) +{ + int ret = 0; + + if (factoryset_mac_setenv() < 0) + ret = -1; + + return ret; +} + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev) +{ + put_unaligned(factory_dat.usb_vendor_id, &dev->idVendor); + put_unaligned(factory_dat.usb_product_id, &dev->idProduct); + return 0; +} +#endif /* defined(CONFIG_SPL_BUILD) */ diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h new file mode 100644 index 0000000..445f384 --- /dev/null +++ b/board/siemens/common/factoryset.h @@ -0,0 +1,27 @@ +/* + * Common board functions for siemens AM335X based boards + * (C) Copyright 2013 Siemens Schweiz AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FACTORYSET_H +#define __FACTORYSET_H + +#define MAX_STRING_LENGTH 32 + +struct factorysetcontainer { + uchar mac[6]; + int usb_vendor_id; + int usb_product_id; + int pxm50; +#if defined(CONFIG_VIDEO) + unsigned char disp_name[MAX_STRING_LENGTH]; +#endif +}; + +int factoryset_read_eeprom(int i2c_addr); +int factoryset_setenv(void); +extern struct factorysetcontainer factory_dat; + +#endif /* __FACTORYSET_H */ diff --git a/board/siemens/dxr2/Makefile b/board/siemens/dxr2/Makefile new file mode 100644 index 0000000..a09b467 --- /dev/null +++ b/board/siemens/dxr2/Makefile @@ -0,0 +1,49 @@ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif + +COBJS += board.o +ifndef CONFIG_SPL_BUILD +COBJS += ../common/factoryset.o +endif +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c new file mode 100644 index 0000000..af9d84f --- /dev/null +++ b/board/siemens/dxr2/board.c @@ -0,0 +1,241 @@ +/* + * Board functions for TI AM335X based dxr2 board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * + * Board functions for TI AM335X based boards + * u-boot:/board/ti/am335x/board.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" +#include "../common/factoryset.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +static struct dxr2_baseboard_id __attribute__((section(".data"))) settings; + +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e33, 0x0100, 0x0001, 0x003A, 0x008A, 0x010B, + 0x00C4, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x0006, 0x61C04AB2, + 0x00000618, +}; + +static void set_default_ddr3_timings(void) +{ + printf("Set default DDR3 settings\n"); + settings.ddr3 = ddr3_default; +} + +static void print_ddr3_timings(void) +{ + printf("\n\nDDR3 Timing parameters:\n"); + printf("Diff Eeprom Default\n"); + PRINTARGS(magic); + PRINTARGS(version); + PRINTARGS(ddr3_sratio); + PRINTARGS(iclkout); + + PRINTARGS(dt0rdsratio0); + PRINTARGS(dt0wdsratio0); + PRINTARGS(dt0fwsratio0); + PRINTARGS(dt0wrsratio0); + + PRINTARGS(sdram_tim1); + PRINTARGS(sdram_tim2); + PRINTARGS(sdram_tim3); + + PRINTARGS(emif_ddr_phy_ctlr_1); + + PRINTARGS(sdram_config); + PRINTARGS(ref_ctrl); +} + +static void print_chip_data(void) +{ + printf("\n"); + printf("Device: '%s'\n", settings.chip.sdevname); + printf("HW version: '%s'\n", settings.chip.shwver); +} +#endif /* CONFIG_SPL_BUILD */ + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return 1; + } + +#ifdef CONFIG_SPL_BUILD + /* Read Siemens eeprom data (DDR3) */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2, + (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) { + printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n"); + set_default_ddr3_timings(); + } + /* Read Siemens eeprom data (CHIP) */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2, + (uchar *)&settings.chip, sizeof(settings.chip))) + printf("Could not read chip settings\n"); + + if (ddr3_default.magic == settings.ddr3.magic && + ddr3_default.version == settings.ddr3.version) { + printf("Using DDR3 settings from EEPROM\n"); + } else { + if (ddr3_default.magic != settings.ddr3.magic) + printf("Error: No valid DDR3 data in eeprom.\n"); + if (ddr3_default.version != settings.ddr3.version) + printf("Error: DDR3 data version does not match.\n"); + + printf("Using default settings\n"); + set_default_ddr3_timings(); + } + + if (MAGIC_CHIP == settings.chip.magic) { + printf("Valid chip data in eeprom\n"); + print_chip_data(); + } else { + printf("Error: No chip data in eeprom\n"); + } + + print_ddr3_timings(); +#endif + return 0; +} + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs dxr2_ddr3_emif_reg_data = { + .zq_config = 0x50074BE4, +}; + +struct ddr_data dxr2_ddr3_data = { + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +struct cmd_control dxr2_ddr3_cmd_ctrl_data = { + .cmd0dldiff = 0, + .cmd1dldiff = 0, + .cmd2dldiff = 0, +}; + /* pass values from eeprom */ + dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; + dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; + dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3; + dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 = + settings.ddr3.emif_ddr_phy_ctlr_1; + dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config; + dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl; + + dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0; + dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0; + dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0; + dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0; + + dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio; + dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout; + dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio; + dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout; + dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; + dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; + + config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &dxr2_ddr3_data, + &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0); +} + +static void spl_siemens_board_init(void) +{ + return; +} +#endif /* if def CONFIG_SPL_BUILD */ + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_MII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 4, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + int n = 0; + int rv; + + factoryset_setenv(); + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#include "../common/board.c" diff --git a/board/siemens/dxr2/board.h b/board/siemens/dxr2/board.h new file mode 100644 index 0000000..2be78fb --- /dev/null +++ b/board/siemens/dxr2/board.h @@ -0,0 +1,69 @@ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \ + settings.ddr3.x, ddr3_default.x +#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y)) +#define MAGIC_CHIP 0x50494843 + +/* Automatic generated definition */ +/* Wed, 19 Jun 2013 10:57:48 +0200 */ +/* From file: draco/ddr3-data-micron.txt */ +struct ddr3_data { + unsigned int magic; /* 0x33524444 */ + unsigned int version; /* 0x56312e33 */ + unsigned short int ddr3_sratio; /* 0x0100 */ + unsigned short int iclkout; /* 0x0001 */ + unsigned short int dt0rdsratio0; /* 0x003A */ + unsigned short int dt0wdsratio0; /* 0x008A */ + unsigned short int dt0fwsratio0; /* 0x010B */ + unsigned short int dt0wrsratio0; /* 0x00C4 */ + unsigned int sdram_tim1; /* 0x0888A39B */ + unsigned int sdram_tim2; /* 0x26247FDA */ + unsigned int sdram_tim3; /* 0x501F821F */ + unsigned short int emif_ddr_phy_ctlr_1; /* 0x0006 */ + unsigned int sdram_config; /* 0x61C04AB2 */ + unsigned int ref_ctrl; /* 0x00000618 */ +}; + +struct chip_data { + unsigned int magic; + char sdevname[16]; + char shwver[7]; +}; + +struct dxr2_baseboard_id { + struct ddr3_data ddr3; + struct chip_data chip; +}; + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/siemens/dxr2/mux.c b/board/siemens/dxr2/mux.c new file mode 100644 index 0000000..bc80b79 --- /dev/null +++ b/board/siemens/dxr2/mux.c @@ -0,0 +1,112 @@ +/* + * pinmux setup for siemens dxr2 board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +static struct module_pin_mux gpios_pin_mux[] = { + /* DFU button GPIO0_27*/ + {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)}, + {OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */ + {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */ + {-1}, +}; + +static struct module_pin_mux ethernet_pin_mux[] = { + {OFFSET(mii1_col), (MODE(3) | RXACTIVE)}, + {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_txen), (MODE(1))}, + {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)}, + {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd1), (MODE(1))}, + {OFFSET(mii1_txd0), (MODE(1))}, + {OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd2), (MODE(1))}, + {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, + {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, + {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + enable_uart3_pin_mux(); + configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(ethernet_pin_mux); + configure_module_pin_mux(gpios_pin_mux); +} diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile new file mode 100644 index 0000000..a09b467 --- /dev/null +++ b/board/siemens/pxm2/Makefile @@ -0,0 +1,49 @@ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif + +COBJS += board.o +ifndef CONFIG_SPL_BUILD +COBJS += ../common/factoryset.o +endif +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c new file mode 100644 index 0000000..2c1841f --- /dev/null +++ b/board/siemens/pxm2/board.c @@ -0,0 +1,429 @@ +/* + * Board functions for TI AM335X based pxm2 board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/board.c + * + * Board functions for TI AM335X based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../drivers/video/da8xx-fb.h" +#include +#include +#include +#include +#include +#include +#include +#include "board.h" +#include "../common/factoryset.h" +#include "pmic.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs pxm2_ddr3_emif_reg_data = { + .sdram_config = 0x41805332, + .sdram_tim1 = 0x666b3c9, + .sdram_tim2 = 0x243631ca, + .sdram_tim3 = 0x33f, + .emif_ddr_phy_ctlr_1 = 0x100005, + .zq_config = 0, + .ref_ctrl = 0x81a, +}; + +struct ddr_data pxm2_ddr3_data = { + .datardsratio0 = 0x81204812, + .datawdsratio0 = 0, + .datafwsratio0 = 0x8020080, + .datawrsratio0 = 0x4010040, + .datauserank0delay = 1, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +struct cmd_control pxm2_ddr3_cmd_ctrl_data = { + .cmd0csratio = 0x80, + .cmd0dldiff = 0, + .cmd0iclkout = 0, + .cmd1csratio = 0x80, + .cmd1dldiff = 0, + .cmd1iclkout = 0, + .cmd2csratio = 0x80, + .cmd2dldiff = 0, + .cmd2iclkout = 0, +}; + + config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data, + &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0); +} + +/* + * voltage switching for MPU frequency switching. + * @module = mpu - 0, core - 1 + * @vddx_op_vol_sel = vdd voltage to set + */ + +#define MPU 0 +#define CORE 1 + +int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel) +{ + uchar buf[4]; + unsigned int reg_offset; + + if (module == MPU) + reg_offset = PMIC_VDD1_OP_REG; + else + reg_offset = PMIC_VDD2_OP_REG; + + /* Select VDDx OP */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + buf[0] &= ~PMIC_OP_REG_CMD_MASK; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + /* Configure VDDx OP Voltage */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + buf[0] &= ~PMIC_OP_REG_SEL_MASK; + buf[0] |= vddx_op_vol_sel; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel) + return 1; + + return 0; +} + +#define OSC (V_OSCK/1000000) + +const struct dpll_params dpll_mpu_pxm2 = { + 720, OSC-1, 1, -1, -1, -1, -1}; + +void spl_siemens_board_init(void) +{ + uchar buf[4]; + /* + * pxm2 PMIC code. All boards currently want an MPU voltage + * of 1.2625V and CORE voltage of 1.1375V to operate at + * 720MHz. + */ + if (i2c_probe(PMIC_CTRL_I2C_ADDR)) + return; + + /* VDD1/2 voltage selection register access by control i/f */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) + return; + + buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) + return; + + /* Frequency switching for OPP 120 */ + if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) || + voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) { + printf("voltage update failed\n"); + } +} +#endif /* if def CONFIG_SPL_BUILD */ + +int read_eeprom(void) +{ + /* nothing ToDo here for this board */ + + return 0; +} + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 4, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + int n = 0; +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; +#ifdef CONFIG_FACTORYSET + int rv; + if (!is_valid_ether_addr(factory_dat.mac)) + printf("Error: no valid mac address\n"); + else + eth_setenv_enetaddr("ethaddr", factory_dat.mac); +#endif /* #ifdef CONFIG_FACTORYSET */ + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel(RGMII_MODE_ENABLE , &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + return n; +} +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +static struct da8xx_panel lcd_panels[] = { + /* AUO G156XW01 V1 */ + [0] = { + .name = "AUO_G156XW01_V1", + .width = 1376, + .height = 768, + .hfp = 14, + .hbp = 64, + .hsw = 56, + .vfp = 1, + .vbp = 28, + .vsw = 3, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, + /* AUO B101EVN06 V0 */ + [1] = { + .name = "AUO_B101EVN06_V0", + .width = 1280, + .height = 800, + .hfp = 52, + .hbp = 84, + .hsw = 36, + .vfp = 3, + .vbp = 14, + .vsw = 6, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, + /* + * Settings from factoryset + * stored in EEPROM + */ + [2] = { + .name = "factoryset", + .width = 0, + .height = 0, + .hfp = 0, + .hbp = 0, + .hsw = 0, + .vfp = 0, + .vbp = 0, + .vsw = 0, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, +}; + +static const struct display_panel disp_panel = { + WVGA, + 32, + 16, + COLOR_ACTIVE, +}; + +static const struct lcd_ctrl_config lcd_cfg = { + &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 32, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + +static int set_gpio(int gpio, int state) +{ + gpio_request(gpio, "temp"); + gpio_direction_output(gpio, state); + gpio_set_value(gpio, state); + gpio_free(gpio); + return 0; +} + +static int enable_backlight(void) +{ + set_gpio(BOARD_LCD_POWER, 1); + set_gpio(BOARD_BACK_LIGHT, 1); + set_gpio(BOARD_TOUCH_POWER, 1); + return 0; +} + +static int enable_pwm(void) +{ + struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE; + struct pwmss_ecap_regs *ecap; + int ticks = PWM_TICKS; + int duty = PWM_DUTY; + + ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE; + /* enable clock */ + setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN); + /* TimeStam Counter register */ + writel(0xdb9, &ecap->tsctr); + /* config period */ + writel(ticks - 1, &ecap->cap3); + writel(ticks - 1, &ecap->cap1); + setbits_le16(&ecap->ecctl2, + (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0)); + /* config duty */ + writel(duty, &ecap->cap2); + writel(duty, &ecap->cap4); + /* start */ + setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN); + return 0; +} + +static struct dpll_regs dpll_lcd_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x98, + .cm_idlest_dpll = CM_WKUP + 0x48, + .cm_clksel_dpll = CM_WKUP + 0x54, +}; + +/* no console on this board */ +int board_cfb_skip(void) +{ + return 1; +} + +#define PLL_GET_M(v) ((v >> 8) & 0x7ff) +#define PLL_GET_N(v) (v & 0x7f) + +static int get_clk(struct dpll_regs *dpll_regs) +{ + unsigned int val; + unsigned int m, n; + int f = 0; + + val = readl(dpll_regs->cm_clksel_dpll); + m = PLL_GET_M(val); + n = PLL_GET_N(val); + f = (m * V_OSCK) / n; + + return f; +}; + +int clk_get(int clk) +{ + return get_clk(&dpll_lcd_regs); +}; + +static int conf_disp_pll(int m, int n) +{ + struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; + struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; + struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1}; + + u32 *const clk_domains[] = { + &cmper->lcdclkctrl, + 0 + }; + u32 *const clk_modules_explicit_en[] = { + &cmper->lcdclkctrl, + &cmper->lcdcclkstctrl, + &cmper->epwmss0clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + writel(0x0, &cmdpll->clklcdcpixelclk); + + do_setup_dpll(&dpll_lcd_regs, &dpll_lcd); + + return 0; +} + +static int board_video_init(void) +{ + /* set 300 MHz */ + conf_disp_pll(25, 2); + if (factory_dat.pxm50) + da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp); + else + da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp); + + enable_pwm(); + enable_backlight(); + + return 0; +} +#endif +#include "../common/board.c" diff --git a/board/siemens/pxm2/board.h b/board/siemens/pxm2/board.h new file mode 100644 index 0000000..0362612 --- /dev/null +++ b/board/siemens/pxm2/board.h @@ -0,0 +1,22 @@ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/siemens/pxm2/mux.c b/board/siemens/pxm2/mux.c new file mode 100644 index 0000000..c64b0d2 --- /dev/null +++ b/board/siemens/pxm2/mux.c @@ -0,0 +1,186 @@ +/* + * pinmux setup for siemens pxm2 board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */ + {-1}, +}; + +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUP_EN}, /* RGMII2_RD0 */ + {OFFSET(mcasp0_ahclkx), MODE(7) | PULLUDEN}, /* MCASP0_AHCLKX */ + {-1}, +}; +#endif + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +#ifndef CONFIG_NO_ETH +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux rgmii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */ + {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */ + {OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */ + {OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */ + {OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */ + {OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */ + {OFFSET(gpmc_a6), MODE(7)}, /* RGMII2_TCLK */ + {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */ + {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */ + {OFFSET(gpmc_a9), MODE(7)}, /* RGMII2_RD2 */ + {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; +#endif + +#ifdef CONFIG_MMC +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDEN)}, /* MMC0_CD */ + {-1}, +}; +#endif + +static struct module_pin_mux lcdc_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD_DAT0 */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD_DAT1 */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD_DAT2 */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD_DAT3 */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD_DAT4 */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD_DAT5 */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD_DAT6 */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD_DAT7 */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD_DAT8 */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD_DAT9 */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD_DAT10 */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD_DAT11 */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD_DAT12 */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD_DAT13 */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD_DAT14 */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD_DAT15 */ + {OFFSET(gpmc_ad8), (MODE(1))}, /* LCD_DAT16 */ + {OFFSET(gpmc_ad9), (MODE(1))}, /* LCD_DAT17 */ + {OFFSET(gpmc_ad10), (MODE(1))}, /* LCD_DAT18 */ + {OFFSET(gpmc_ad11), (MODE(1))}, /* LCD_DAT19 */ + {OFFSET(gpmc_ad12), (MODE(1))}, /* LCD_DAT20 */ + {OFFSET(gpmc_ad13), (MODE(1))}, /* LCD_DAT21 */ + {OFFSET(gpmc_ad14), (MODE(1))}, /* LCD_DAT22 */ + {OFFSET(gpmc_ad15), (MODE(1))}, /* LCD_DAT23 */ + {OFFSET(lcd_vsync), (MODE(0))}, /* LCD_VSYNC */ + {OFFSET(lcd_hsync), (MODE(0))}, /* LCD_HSYNC */ + {OFFSET(lcd_pclk), (MODE(0))}, /* LCD_PCLK */ + {OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD_AC_BIAS_EN */ + {-1}, +}; + +static struct module_pin_mux ecap0_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux gpio_pin_mux[] = { + {OFFSET(mcasp0_fsx), MODE(7)}, /* GPIO3_15 LCD power*/ + {OFFSET(mcasp0_axr0), MODE(7)}, /* GPIO3_16 Backlight */ + {OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25 Touch power */ + {-1}, +}; +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(i2c1_pin_mux); +#ifdef CONFIG_NAND + configure_module_pin_mux(nand_pin_mux); +#endif +#ifndef CONFIG_NO_ETH + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(rgmii2_pin_mux); +#endif +#ifdef CONFIG_MMC + configure_module_pin_mux(mmc0_pin_mux); +#endif + configure_module_pin_mux(lcdc_pin_mux); + configure_module_pin_mux(gpio_pin_mux); + configure_module_pin_mux(ecap0_pin_mux); +} diff --git a/board/siemens/pxm2/pmic.h b/board/siemens/pxm2/pmic.h new file mode 100644 index 0000000..c6347e5 --- /dev/null +++ b/board/siemens/pxm2/pmic.h @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef PMIC_H +#define PMIC_H + +/* + * The PMIC on this board is a TPS65910. + */ + +#define PMIC_SR_I2C_ADDR 0x12 +#define PMIC_CTRL_I2C_ADDR 0x2D +/* PMIC Register offsets */ +#define PMIC_VDD1_REG 0x21 +#define PMIC_VDD1_OP_REG 0x22 +#define PMIC_VDD2_REG 0x24 +#define PMIC_VDD2_OP_REG 0x25 +#define PMIC_DEVCTRL_REG 0x3f + +/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */ +#define PMIC_VGAIN_SEL_MASK (0x3 << 6) +#define PMIC_ILMAX_MASK (0x1 << 5) +#define PMIC_TSTEP_MASK (0x7 << 2) +#define PMIC_ST_MASK (0x3) + +#define PMIC_REG_VGAIN_SEL_X1 (0x0 << 6) +#define PMIC_REG_VGAIN_SEL_X1_0 (0x1 << 6) +#define PMIC_REG_VGAIN_SEL_X3 (0x2 << 6) +#define PMIC_REG_VGAIN_SEL_X4 (0x3 << 6) + +#define PMIC_REG_ILMAX_1_0_A (0x0 << 5) +#define PMIC_REG_ILMAX_1_5_A (0x1 << 5) + +#define PMIC_REG_TSTEP_ (0x0 << 2) +#define PMIC_REG_TSTEP_12_5 (0x1 << 2) +#define PMIC_REG_TSTEP_9_4 (0x2 << 2) +#define PMIC_REG_TSTEP_7_5 (0x3 << 2) +#define PMIC_REG_TSTEP_6_25 (0x4 << 2) +#define PMIC_REG_TSTEP_4_7 (0x5 << 2) +#define PMIC_REG_TSTEP_3_12 (0x6 << 2) +#define PMIC_REG_TSTEP_2_5 (0x7 << 2) + +#define PMIC_REG_ST_OFF (0x0) +#define PMIC_REG_ST_ON_HI_POW (0x1) +#define PMIC_REG_ST_OFF_1 (0x2) +#define PMIC_REG_ST_ON_LOW_POW (0x3) + + +/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ +#define PMIC_OP_REG_SEL (0x7F) + +#define PMIC_OP_REG_CMD_MASK (0x1 << 7) +#define PMIC_OP_REG_CMD_OP (0x0 << 7) +#define PMIC_OP_REG_CMD_SR (0x1 << 7) + +#define PMIC_OP_REG_SEL_MASK (0x7F) +#define PMIC_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ +#define PMIC_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */ + +/* Device control register . (DEVCTRL_REG) */ +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4) +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) + +#endif diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile new file mode 100644 index 0000000..a09b467 --- /dev/null +++ b/board/siemens/rut/Makefile @@ -0,0 +1,49 @@ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif + +COBJS += board.o +ifndef CONFIG_SPL_BUILD +COBJS += ../common/factoryset.o +endif +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c new file mode 100644 index 0000000..f2b0476 --- /dev/null +++ b/board/siemens/rut/board.c @@ -0,0 +1,432 @@ +/* + * Board functions for TI AM335X based rut board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/board.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" +#include "../common/factoryset.h" +#include "../../../drivers/video/da8xx-fb.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + return 0; +} + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs rut_ddr3_emif_reg_data = { + .sdram_config = 0x61C04AB2, + .sdram_tim1 = 0x0888A39B, + .sdram_tim2 = 0x26337FDA, + .sdram_tim3 = 0x501F830F, + .emif_ddr_phy_ctlr_1 = 0x6, + .zq_config = 0x50074BE4, + .ref_ctrl = 0x93B, +}; + +struct ddr_data rut_ddr3_data = { + .datardsratio0 = 0x3b, + .datawdsratio0 = 0x85, + .datafwsratio0 = 0x100, + .datawrsratio0 = 0xc1, + .datauserank0delay = 1, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +struct cmd_control rut_ddr3_cmd_ctrl_data = { + .cmd0csratio = 0x40, + .cmd0dldiff = 0, + .cmd0iclkout = 1, + .cmd1csratio = 0x40, + .cmd1dldiff = 0, + .cmd1iclkout = 1, + .cmd2csratio = 0x40, + .cmd2dldiff = 0, + .cmd2iclkout = 1, +}; + + config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data, + &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0); +} + +static void spl_siemens_board_init(void) +{ + return; +} +#endif /* if def CONFIG_SPL_BUILD */ + +#if defined(CONFIG_DRIVER_TI_CPSW) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 1, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + int n = 0; + int rv; + +#ifndef CONFIG_SPL_BUILD + factoryset_setenv(); +#endif + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#if defined(CONFIG_HW_WATCHDOG) +static bool hw_watchdog_init_done; +static int hw_watchdog_trigger_level; + +void hw_watchdog_reset(void) +{ + if (!hw_watchdog_init_done) + return; + + hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1; + gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); +} + +void hw_watchdog_init(void) +{ + gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger"); + gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); + + hw_watchdog_reset(); + + hw_watchdog_init_done = 1; +} +#endif /* defined(CONFIG_HW_WATCHDOG) */ + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +static struct da8xx_panel lcd_panels[] = { + /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */ + [0] = { + .name = "KWH043MC17-F01", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, + /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */ + [1] = { + .name = "KWH043ST20-F01", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, + /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */ + [2] = { + .name = "MI0430VT-1", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, +}; + +static const struct display_panel disp_panels[] = { + [0] = { + WVGA, + 16, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, + [1] = { + WVGA, + 16, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, + [2] = { + WVGA, + 24, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, +}; + +static const struct lcd_ctrl_config lcd_cfgs[] = { + [0] = { + &disp_panels[0], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + [1] = { + &disp_panels[1], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + [2] = { + &disp_panels[2], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 24, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + +}; + +/* no console on this board */ +int board_cfb_skip(void) +{ + return 1; +} + +#define PLL_GET_M(v) ((v >> 8) & 0x7ff) +#define PLL_GET_N(v) (v & 0x7f) + +static struct dpll_regs dpll_lcd_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x98, + .cm_idlest_dpll = CM_WKUP + 0x48, + .cm_clksel_dpll = CM_WKUP + 0x54, +}; + +static int get_clk(struct dpll_regs *dpll_regs) +{ + unsigned int val; + unsigned int m, n; + int f = 0; + + val = readl(dpll_regs->cm_clksel_dpll); + m = PLL_GET_M(val); + n = PLL_GET_N(val); + f = (m * V_OSCK) / n; + + return f; +}; + + + +int clk_get(int clk) +{ + return get_clk(&dpll_lcd_regs); +}; + +static int conf_disp_pll(int m, int n) +{ + struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; + struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; + struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1}; +#if defined(DISPL_PLL_SPREAD_SPECTRUM) + struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; +#endif + + u32 *const clk_domains[] = { + &cmper->lcdclkctrl, + 0 + }; + u32 *const clk_modules_explicit_en[] = { + &cmper->lcdclkctrl, + &cmper->lcdcclkstctrl, + &cmper->spi1clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + /* 0x44e0_0500 write lcdc pixel clock mux Linux hat hier 0 */ + writel(0x0, &cmdpll->clklcdcpixelclk); + + do_setup_dpll(&dpll_lcd_regs, &dpll_lcd); + +#if defined(DISPL_PLL_SPREAD_SPECTRUM) + writel(0x64, &cmwkup->resv6[3]); /* 0x50 */ + writel(0x800, &cmwkup->resv6[2]); /* 0x4c */ + writel(readl(&cmwkup->clkmoddplldisp) | (1 << 12), + &cmwkup->clkmoddplldisp); /* 0x98 */ +#endif + return 0; +} + +static int set_gpio(int gpio, int state) +{ + gpio_request(gpio, "temp"); + gpio_direction_output(gpio, state); + gpio_set_value(gpio, state); + gpio_free(gpio); + return 0; +} + +static int enable_lcd(void) +{ + unsigned char buf[1]; + + set_gpio(BOARD_LCD_RESET, 1); + + /* spi lcd init */ + kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_3); + + /* backlight on */ + buf[0] = 0xf; + i2c_write(0x24, 0x7, 1, buf, 1); + buf[0] = 0x3f; + i2c_write(0x24, 0x8, 1, buf, 1); + return 0; +} + +int arch_early_init_r(void) +{ + enable_lcd(); + return 0; +} + +static int board_video_init(void) +{ + int i; + int anzdisp = ARRAY_SIZE(lcd_panels); + int display = 1; + + for (i = 0; i < anzdisp; i++) { + if (strncmp((const char *)factory_dat.disp_name, + lcd_panels[i].name, + strlen((const char *)factory_dat.disp_name)) == 0) { + printf("DISPLAY: %s\n", factory_dat.disp_name); + break; + } + } + if (i == anzdisp) { + i = 1; + printf("%s: %s not found, using default %s\n", __func__, + factory_dat.disp_name, lcd_panels[i].name); + } + conf_disp_pll(25, 2); + da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display], + lcd_cfgs[display].bpp); + + return 0; +} + + +#endif /* ifdef CONFIG_VIDEO */ +#include "../common/board.c" diff --git a/board/siemens/rut/board.h b/board/siemens/rut/board.h new file mode 100644 index 0000000..0362612 --- /dev/null +++ b/board/siemens/rut/board.h @@ -0,0 +1,22 @@ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/siemens/rut/mux.c b/board/siemens/rut/mux.c new file mode 100644 index 0000000..1eced01 --- /dev/null +++ b/board/siemens/rut/mux.c @@ -0,0 +1,347 @@ +/* + * pinmux setup for siemens rut board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux ddr_pin_mux[] = { + {OFFSET(ddr_resetn), (MODE(0))}, + {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ck), (MODE(0))}, + {OFFSET(ddr_nck), (MODE(0))}, + {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba2), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a2), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a3), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a4), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a5), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a6), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a7), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a8), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a9), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a10), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a11), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a12), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a13), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a14), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a15), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_odt), (MODE(0))}, + {OFFSET(ddr_d0), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d1), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d2), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d3), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d4), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d5), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d6), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d7), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d8), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d9), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d10), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d11), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d12), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d13), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d14), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d15), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqm0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_dqm1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_dqs0), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqsn0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ddr_dqs1), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqsn1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ddr_vref), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ddr_vtp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(gpmc_ad8), (MODE(1))}, + {OFFSET(gpmc_ad9), (MODE(1))}, + {OFFSET(gpmc_ad10), (MODE(1))}, + {OFFSET(gpmc_ad11), (MODE(1))}, + {OFFSET(gpmc_ad12), (MODE(1))}, + {OFFSET(gpmc_ad13), (MODE(1))}, + {OFFSET(gpmc_ad14), (MODE(1))}, + {OFFSET(gpmc_ad15), (MODE(1))}, + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_vsync), (MODE(0))}, + {OFFSET(lcd_hsync), (MODE(0))}, + {OFFSET(lcd_pclk), (MODE(0))}, + {OFFSET(lcd_ac_bias_en), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux mii_pin_mux[] = { + {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_txen), (MODE(1))}, + {OFFSET(mii1_txd1), (MODE(1))}, + {OFFSET(mii1_txd0), (MODE(1))}, + {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, + {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, + {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux gpio_pin_mux[] = { + {OFFSET(mii1_col), (MODE(7) | RXACTIVE)}, + {OFFSET(uart1_ctsn), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_rtsn), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_txd), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txclk), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxclk), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxd2), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a0), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a1), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a4), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a5), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a6), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a7), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_wpn), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_be1n), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn1), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn2), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn3), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_aclkr), (MODE(7) | RXACTIVE)}, + {OFFSET(mcasp0_fsr), (MODE(7))}, + {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)}, + {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE)}, + {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(xdma_event_intr1), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux usb0_pin_mux[] = { + {OFFSET(usb0_dm), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_dp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_ce), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_id), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_drvvbus), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux usb1_pin_mux[] = { + {OFFSET(usb1_dm), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_dp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_ce), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_id), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_drvvbus), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux spi0_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_cs1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux spi1_pin_mux[] = { + {OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux jtag_pin_mux[] = { + {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdo), (MODE(0) | PULLUP_EN)}, + {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ntrst), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux ainx_pin_mux[] = { + {OFFSET(ain7), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain6), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain5), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain4), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain3), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain2), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux rtc_pin_mux[] = { + {OFFSET(osc1_in), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(osc1_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux gpmc_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_clk), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux pmic_pin_mux[] = { + {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux osc_pin_mux[] = { + {OFFSET(osc0_in), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(osc0_out), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux pwm_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(gpmc_a2), (MODE(6))}, + {OFFSET(gpmc_a3), (MODE(6))}, + {-1}, +}; + +static struct module_pin_mux emu_pin_mux[] = { + {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux vref_pin_mux[] = { + {OFFSET(vrefp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(vrefn), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux misc_pin_mux[] = { + {OFFSET(porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(ddr_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(mii_pin_mux); + configure_module_pin_mux(gpio_pin_mux); + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(usb0_pin_mux); + configure_module_pin_mux(usb1_pin_mux); + configure_module_pin_mux(spi0_pin_mux); + configure_module_pin_mux(spi1_pin_mux); + configure_module_pin_mux(jtag_pin_mux); + configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(ainx_pin_mux); + configure_module_pin_mux(rtc_pin_mux); + configure_module_pin_mux(gpmc_pin_mux); + configure_module_pin_mux(pmic_pin_mux); + configure_module_pin_mux(osc_pin_mux); + configure_module_pin_mux(pwm_pin_mux); + configure_module_pin_mux(emu_pin_mux); + configure_module_pin_mux(vref_pin_mux); + configure_module_pin_mux(misc_pin_mux); +} diff --git a/boards.cfg b/boards.cfg index d7c8d34..7ccc7ce 100644 --- a/boards.cfg +++ b/boards.cfg @@ -254,6 +254,9 @@ am335x_evm_uart5 arm armv7 am335x ti am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT am335x_boneblack arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT am43xx_evm arm armv7 am43xx ti am33xx am43xx_evm:SERIAL1,CONS_INDEX=1 +dxr2 arm armv7 dxr2 siemens am33xx +pxm2 arm armv7 pxm2 siemens am33xx +rut arm armv7 rut siemens am33xx ti814x_evm arm armv7 ti814x ti am33xx ti816x_evm arm armv7 ti816x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 diff --git a/include/configs/dxr2.h b/include/configs/dxr2.h new file mode 100644 index 0000000..cd553ec --- /dev/null +++ b/include/configs/dxr2.h @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_DXR2_H +#define __CONFIG_DXR2_H + +#define CONFIG_SIEMENS_DXR2 +#define MACH_TYPE_DXR2 4315 +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DXR2 + +#include "siemens-am33x-common.h" + +#define CONFIG_SYS_MPUCLK 275 +#define DXR2_IOCTRL_VAL 0x18b +#define DDR_PLL_FREQ 266 +#define CONFIG_SPL_AM33XX_DO_NOT_ENABLE_RTC32K + +#define BOARD_DFU_BUTTON_GPIO 27 +#define BOARD_DFU_BUTTON_LED 64 + +#undef CONFIG_DOS_PARTITION +#undef CONFIG_CMD_FAT + + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define EEPROM_ADDR_DDR3 0x90 +#define EEPROM_ADDR_CHIP 0x120 + +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 + +#undef CONFIG_SPL_NET_SUPPORT +#undef CONFIG_SPL_NET_VCI_STRING +#undef CONFIG_SPL_ETH_SUPPORT + +#undef CONFIG_MII +#undef CONFIG_PHY_GIGE +#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_SMSC + +#define CONFIG_FACTORYSET + +/* Watchdog */ +#define CONFIG_OMAP_WATCHDOG + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=dxr2\0" \ + "nand_img_size=0x300000\0" \ + "optargs=\0" \ + CONFIG_COMMON_ENV_SETTINGS + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTCOMMAND \ +"if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ +"fi;" \ +"if ping ${serverip}; then " \ + "run net_nfs; " \ +"fi;" \ +"run nand_boot;" + +#else +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ +#endif /* ! __CONFIG_DXR2_H */ diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h new file mode 100644 index 0000000..20b0f9a --- /dev/null +++ b/include/configs/pxm2.h @@ -0,0 +1,153 @@ +/* + * siemens pxm2 + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PXM2_H +#define __CONFIG_PXM2_H + +#define CONFIG_SIEMENS_PXM2 +#define MACH_TYPE_PXM2 4309 +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_PXM2 + +#include "siemens-am33x-common.h" + +#define CONFIG_SYS_MPUCLK 720 +#define DXR2_IOCTRL_VAL 0x18b +#define DDR_PLL_FREQ 266 + +#define BOARD_DFU_BUTTON_GPIO 59 +#define BOARD_DFU_BUTTON_LED 117 +#define BOARD_LCD_POWER 111 +#define BOARD_BACK_LIGHT 112 +#define BOARD_TOUCH_POWER 57 + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + + +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 + +#undef CONFIG_SPL_NET_SUPPORT +#undef CONFIG_SPL_NET_VCI_STRING +#undef CONFIG_SPL_ETH_SUPPORT + +#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_ATHEROS + +#define CONFIG_FACTORYSET + +/* UBI Support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#endif + +/* Watchdog */ +#define CONFIG_OMAP_WATCHDOG + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=pxm2\0" \ + "nand_img_size=0x500000\0" \ + "optargs=\0" \ + CONFIG_COMMON_ENV_SETTINGS \ + "mmc_dev=0\0" \ + "mmc_root=/dev/mmcblk0p2 rw\0" \ + "mmc_root_fs_type=ext4 rootwait\0" \ + "mmc_load_uimage=" \ + "mmc rescan; " \ + "setenv bootfile uImage;" \ + "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \ + "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "mmc_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv bootargs ${bootargs} " \ + "root=${mmc_root} ${mtdparts}" \ + "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \ + "eth=${ethaddr} " \ + "\0" \ + "mmc_boot=run mmc_args; " \ + "run mmc_load_uimage; " \ + "bootm ${kloadaddr}\0" \ + "" + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTCOMMAND \ + "if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ + "fi; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmc_dev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run mmc_load_uimage; then " \ + "run mmc_args;" \ + "bootm ${kloadaddr};" \ + "fi;" \ + "fi;" \ + "run nand_boot;" \ + "if ping ${serverip}; then " \ + "run net_nfs; " \ + "fi; " + +#else +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_VIDEO +#if defined(CONFIG_VIDEO) +#define CONFIG_VIDEO_DA8XX +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CMD_BMP +#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE +#define PWM_TICKS 0x1388 +#define PWM_DUTY 0x200 +#endif + +#endif /* ! __CONFIG_PXM2_H */ diff --git a/include/configs/rut.h b/include/configs/rut.h new file mode 100644 index 0000000..7c94644 --- /dev/null +++ b/include/configs/rut.h @@ -0,0 +1,156 @@ +/* + * siemens rut + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RUT_H +#define __CONFIG_RUT_H + +#define CONFIG_SIEMENS_RUT +#define MACH_TYPE_RUT 4316 +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT + +#include "siemens-am33x-common.h" + +#define CONFIG_SYS_MPUCLK 600 +#define RUT_IOCTRL_VAL 0x18b +#define DDR_PLL_FREQ 303 + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 + +#undef CONFIG_SPL_NET_SUPPORT +#undef CONFIG_SPL_NET_VCI_STRING +#undef CONFIG_SPL_ETH_SUPPORT + +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY_NATSEMI + +#define CONFIG_FACTORYSET + +/* UBI Support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#endif + +/* Watchdog */ +#define WATCHDOG_TRIGGER_GPIO 14 + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=rut\0" \ + "splashpos=488,352\0" \ + "optargs=fixrtc --no-log consoleblank=0 \0" \ + CONFIG_COMMON_ENV_SETTINGS \ + "mmc_dev=0\0" \ + "mmc_root=/dev/mmcblk0p2 rw\0" \ + "mmc_root_fs_type=ext4 rootwait\0" \ + "mmc_load_uimage=" \ + "mmc rescan; " \ + "setenv bootfile uImage;" \ + "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \ + "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "mmc_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv bootargs ${bootargs} " \ + "root=${mmc_root} ${mtdparts}" \ + "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \ + "eth=${ethaddr} " \ + "\0" \ + "mmc_boot=run mmc_args; " \ + "run mmc_load_uimage; " \ + "bootm ${kloadaddr}\0" \ + "" + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmc_dev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run mmc_load_uimage; then " \ + "run mmc_args;" \ + "bootm ${kloadaddr};" \ + "fi;" \ + "fi;" \ + "run nand_boot;" \ + "if ping ${serverip}; then " \ + "run net_nfs; " \ + "fi; " + +#else +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif + +#endif /* CONFIG_SPL_BUILD */ + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_HW_WATCHDOG +#endif + +#define CONFIG_VIDEO +#if defined(CONFIG_VIDEO) +#define CONFIG_VIDEO_DA8XX +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CMD_BMP +#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE + +#define CONFIG_SPI +#define CONFIG_OMAP3_SPI + +#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */ +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_FORMIKE +#endif + +#endif /* ! __CONFIG_RUT_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h new file mode 100644 index 0000000..f0bac97 --- /dev/null +++ b/include/configs/siemens-am33x-common.h @@ -0,0 +1,463 @@ +/* + * siemens am33x common board options + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_SIEMENS_AM33X_COMMON_H +#define __CONFIG_SIEMENS_AM33X_COMMON_H + +#define CONFIG_AM33XX +#define CONFIG_OMAP +#define CONFIG_OMAP_COMMON + +#include + +#define CONFIG_DMA_COHERENT +#define CONFIG_DMA_COHERENT_SIZE (1 << 20) + +#define CONFIG_ENV_SIZE (0x2000) +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_NO_FLASH +#define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* commands to include */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_CACHE + +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#ifndef CONFIG_SPL_BUILD +#define CONFIG_ROOTPATH "/opt/eldk" +#endif + +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_AUTOLOAD "yes" + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 32 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * memtest works on 8 MB in DRAM after skipping 32MB from + * start addr of ram disk + */ +#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + + (8 * 1024 * 1024)) + +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ + +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#define CONFIG_SPI +#define CONFIG_OMAP3_SPI +#define CONFIG_MTD_DEVICE +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED (75000000) + + /* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + /* Platform/Board specific defs */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CONFIG_SYS_NS16550_COM4 0x481a6000 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SERIAL1 1 +#define CONFIG_CONS_INDEX 1 + +/* I2C Configuration */ +#define CONFIG_I2C +#define CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_DRIVER_OMAP24XX_I2C + + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (101 * 1024) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_FS_FAT +#define CONFIG_SPL_I2C_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT + +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_NAND_AM33XX_BCH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 + +#define CONFIG_SYS_NAND_ECCSTEPS 4 +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#ifndef CONFIG_SPL_BUILD +/* + * USB configuration + */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_GADGET +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_MUSB_HOST + +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + +#ifdef CONFIG_MUSB_GADGET +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" +#endif /* CONFIG_MUSB_GADGET */ + +#define CONFIG_USB_GADGET +#define CONFIG_USBDOWNLOAD_GADGET + +/* USB TI's IDs */ +#define CONFIG_USBD_HS +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_PRODUCT_NUM 0x4a47 +#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" + +/* USB Device Firmware Update support */ +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_NAND +#define CONFIG_CMD_DFU +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20) + +#endif /* CONFIG_SPL_BUILD */ + +/* + * Default to using SPI for environment, etc. We have multiple copies + * of SPL as the ROM will check these locations. + * 0x0 - 0x20000 : First copy of SPL + * 0x20000 - 0x40000 : Second copy of SPL + * 0x40000 - 0x60000 : Third copy of SPL + * 0x60000 - 0x80000 : Fourth copy of SPL + * 0x80000 - 0xDF000 : U-Boot + * 0xDF000 - 0xE0000 : U-Boot Environment + * 0xE0000 - 0x442000 : Linux Kernel + * 0x442000 - 0x800000 : Userland + */ +#if defined(CONFIG_SPI_BOOT) +# undef CONFIG_ENV_IS_NOWHERE +# define CONFIG_ENV_IS_IN_SPI_FLASH +# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */ +# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#endif /* SPI support */ + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_CMD_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI + +#define CONFIG_NAND +/* NAND support */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS + +#define MTDIDS_NAME_STR "omap2-nand.0" +#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR +#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ + "128k(spl)," \ + "128k(spl.backup1)," \ + "128k(spl.backup2)," \ + "128k(spl.backup3)," \ + "1920k(u-boot)," \ + "128k(uboot.env)," \ + "5120k(kernel_a)," \ + "5120k(kernel_b)," \ + "8192k(mtdoops)," \ + "-(rootfs)" +/* + * chip-size = 256MiB + *| name | size | address area | + *------------------------------------------------------- + *| spl | 128.000 KiB | 0x 0..0x 1ffff | + *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff | + *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff | + *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff | + *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff | + *| uboot.env | 128.000 KiB | 0x 260000..0x 27ffff | + *| kernel_a | 5.000 MiB | 0x 280000..0x 77ffff | + *| kernel_b | 5.000 MiB | 0x 780000..0x c7ffff | + *| mtdoops | 8.000 MiB | 0x c80000..0x 147ffff | + *| rootfs | 235.500 MiB | 0x 1480000..0x fffffff | + *------------------------------------------------------- + */ + +#define DFU_ALT_INFO_NAND \ + "spl part 0 1;" \ + "spl.backup1 part 0 2;" \ + "spl.backup2 part 0 3;" \ + "spl.backup3 part 0 4;" \ + "u-boot part 0 5;" \ + "u-boot.env part 0 6;" \ + "kernel_a part 0 7;" \ + "kernel_b part 0 8;" \ + "rootfs partubi 0 10" + +#define CONFIG_COMMON_ENV_SETTINGS \ + "verify=no \0" \ + "project_dir=systemone\0" \ + "loadaddr=0x82000000\0" \ + "kloadaddr=0x81000000\0" \ + "script_addr=0x81900000\0" \ + "console=console=ttyMTD,mtdoops console=ttyO0,115200n8\0" \ + "active_set=a\0" \ + "nand_active_ubi_vol=rootfs_a\0" \ + "nand_root_fs_type=ubifs rootwait=1\0" \ + "nand_src_addr=0x280000\0" \ + "nand_src_addr_a=0x280000\0" \ + "nand_src_addr_b=0x780000\0" \ + "nfsopts=nolock rw mem=128M\0" \ + "ip_method=none\0" \ + "bootenv=uEnv.txt\0" \ + "bootargs_defaults=setenv bootargs " \ + "console=${console} " \ + "${optargs}\0" \ + "nand_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv nand_active_ubi_vol rootfs_${active_set};" \ + "setenv ${active_set} true;" \ + "if test -n ${a}; then " \ + "setenv nand_src_addr ${nand_src_addr_a};" \ + "fi;" \ + "if test -n ${b}; then " \ + "setenv nand_src_addr ${nand_src_addr_b};" \ + "fi;" \ + "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ + "ubi.mtd=9,2048;" \ + "setenv bootargs ${bootargs} " \ + "root=${nand_root} noinitrd ${mtdparts} " \ + "rootfstype=${nand_root_fs_type} ip=${ip_method} " \ + "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \ + "=mtdoops\0" \ + "dfu_args=run bootargs_defaults;" \ + "setenv bootargs ${bootargs} ;" \ + "mtdparts default; " \ + "dfu nand 0; \0" \ + "dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \ + "net_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv bootfile ${project_dir}/kernel/uImage;" \ + "setenv rootpath /home/projects/${project_dir}/rootfs;" \ + "setenv bootargs ${bootargs} " \ + "root=/dev/nfs ${mtdparts} " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} " \ + "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ + "nand_boot=echo Booting from nand, active set ${active_set} ...; " \ + "run nand_args; " \ + "nand read.i ${kloadaddr} ${nand_src_addr} " \ + "${nand_img_size}; bootm ${kloadaddr}\0" \ + "net_nfs=echo Booting from network ...; " \ + "run net_args; " \ + "tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \ + "bootm ${kloadaddr}\0" \ + "flash_self=run nand_boot\0" \ + "flash_self_test=setenv bootargs_defaults ${bootargs_defaults} test; " \ + "run nand_boot\0" \ + "dfu_start=echo Preparing for dfu mode ...; " \ + "run dfu_args; \0" \ + "preboot=echo; "\ + "echo Type 'run flash_self' to use kernel and root " \ + "filesystem on memory; echo Type 'run flash_self_test' to " \ + "use kernel and root filesystem on memory, boot in test " \ + "mode; echo Not ready yet: 'run flash_nfs' to use kernel " \ + "from memory and root filesystem over NFS; echo Type " \ + "'run net_nfs' to get Kernel over TFTP and mount root " \ + "filesystem over NFS; echo Set active_set variable to 'a' " \ + "or 'b' to select kernel and rootfs partition; " \ + "echo" \ + "\0" + +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ + /* to access nand at */ + /* CS0 */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND + devices */ +#if !defined(CONFIG_SPI_BOOT) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#endif +#endif + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_OMAP_GPIO +#endif + +/* Watchdog */ +#define CONFIG_HW_WATCHDOG + +/* Stop autoboot with ESC ESC key detected */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "\x1b\x1b" +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ + "press \"\" to stop\n", bootdelay + +#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */ diff --git 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zpVWEBLuGf#C@1VsWE9H8r$O`tE%c|y<75nq3gVN@qT|`YzqD${-=0Sf-iW-L@3Wo)4 z?NiL7j#I<6eTXg)sd-6%C2r)%qkrG=!{w{SX3)hBspeb~VZTGjO^lCu?rXoRruLI zGp;Dv`6cIvx`j=YRps2}oZ~bri>A%z-p2@HKWV!(-hBI`F1N5O(NZpQKo&{ Date: Wed, 28 Aug 2013 12:00:18 -0400 Subject: [PATCH 26/26] siemens-am33x-common.h: Always build CONFIG_OMAP_GPIO support The MMC driver relies on this block now. Signed-off-by: Tom Rini --- include/configs/siemens-am33x-common.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index f0bac97..5426ee8 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -447,9 +447,7 @@ #endif #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_OMAP_GPIO -#endif /* Watchdog */ #define CONFIG_HW_WATCHDOG