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@ -20,8 +20,9 @@ |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <libfdt.h> |
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#include <fdt_support.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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#include <command.h> |
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@ -31,16 +32,16 @@ |
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DECLARE_GLOBAL_DATA_PTR; |
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extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/ |
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#if 0 |
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#define FPGA_DEBUG |
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#endif |
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extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
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extern void __ft_board_setup(void *blob, bd_t *bd); |
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#undef FPGA_DEBUG |
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/* fpga configuration data - generated by bin2cc */ |
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const unsigned char fpgadata[] = |
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{ |
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#ifdef CONFIG_CPCI405_VER2 |
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# ifdef CONFIG_CPCI405AB |
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#if defined(CONFIG_CPCI405_VER2) |
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# if defined(CONFIG_CPCI405AB) |
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# include "fpgadata_cpci405ab.c" |
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# else |
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# include "fpgadata_cpci4052.c" |
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@ -56,7 +57,7 @@ const unsigned char fpgadata[] = |
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#include "../common/fpga.c" |
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#include "../common/auto_update.h" |
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#ifdef CONFIG_CPCI405AB |
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#if defined(CONFIG_CPCI405AB) |
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au_image_t au_image[] = { |
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{"cpci405ab/preinst.img", 0, -1, AU_SCRIPT}, |
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{"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR}, |
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@ -65,7 +66,7 @@ au_image_t au_image[] = { |
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{"cpci405ab/postinst.img", 0, 0, AU_SCRIPT}, |
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}; |
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#else |
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#ifdef CONFIG_CPCI405_VER2 |
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#if defined(CONFIG_CPCI405_VER2) |
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au_image_t au_image[] = { |
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{"cpci4052/preinst.img", 0, -1, AU_SCRIPT}, |
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{"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR}, |
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@ -91,7 +92,7 @@ int cpci405_version(void); |
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int gunzip(void *, int, unsigned char *, unsigned long *); |
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void lxt971_no_sleep(void); |
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int board_early_init_f (void) |
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int board_early_init_f(void) |
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{ |
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#ifndef CONFIG_CPCI405_VER2 |
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int index, len, i; |
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@ -100,18 +101,19 @@ int board_early_init_f (void) |
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#ifdef FPGA_DEBUG |
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/* set up serial port with default baudrate */ |
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(void) get_clocks (); |
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(void)get_clocks(); |
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gd->baudrate = CONFIG_BAUDRATE; |
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serial_init (); |
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serial_init(); |
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console_init_f(); |
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#endif |
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/*
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* First pull fpga-prg pin low, to disable fpga logic (on version 2 board) |
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* First pull fpga-prg pin low, |
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* to disable fpga logic (on version 2 board) |
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*/ |
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out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ |
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out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ |
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out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ |
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out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ |
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out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ |
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out32(GPIO0_OR, 0); /* pull prg low */ |
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/*
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@ -124,39 +126,42 @@ int board_early_init_f (void) |
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/* booting FPGA failed */ |
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#ifndef FPGA_DEBUG |
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/* set up serial port with default baudrate */ |
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(void) get_clocks (); |
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(void)get_clocks(); |
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gd->baudrate = CONFIG_BAUDRATE; |
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serial_init (); |
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serial_init(); |
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console_init_f(); |
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#endif |
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printf("\nFPGA: Booting failed "); |
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switch (status) { |
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case ERROR_FPGA_PRG_INIT_LOW: |
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printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); |
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printf("(Timeout: INIT not low after " |
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"asserting PROGRAM*)\n "); |
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break; |
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case ERROR_FPGA_PRG_INIT_HIGH: |
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printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); |
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printf("(Timeout: INIT not high after " |
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"deasserting PROGRAM*)\n "); |
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break; |
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case ERROR_FPGA_PRG_DONE: |
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printf("(Timeout: DONE not high after programming FPGA)\n "); |
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printf("(Timeout: DONE not high after " |
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"programming FPGA)\n "); |
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break; |
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} |
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/* display infos on fpgaimage */ |
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index = 15; |
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for (i=0; i<4; i++) { |
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for (i = 0; i < 4; i++) { |
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len = fpgadata[index]; |
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printf("FPGA: %s\n", &(fpgadata[index+1])); |
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index += len+3; |
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printf("FPGA: %s\n", &(fpgadata[index + 1])); |
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index += len + 3; |
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} |
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putc ('\n'); |
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putc('\n'); |
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/* delayed reboot */ |
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for (i=20; i>0; i--) { |
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for (i = 20; i > 0; i--) { |
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printf("Rebooting in %2d seconds \r",i); |
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for (index=0;index<1000;index++) |
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for (index = 0; index < 1000; index++) |
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udelay(1000); |
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} |
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putc ('\n'); |
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putc('\n'); |
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do_reset(NULL, 0, 0, NULL); |
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} |
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} |
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@ -167,7 +172,7 @@ int board_early_init_f (void) |
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* IRQ 16 405GP internally generated; active low; level sensitive |
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* IRQ 17-24 RESERVED |
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive |
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* IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive |
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* IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens. |
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* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive |
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* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive |
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* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive |
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@ -177,7 +182,7 @@ int board_early_init_f (void) |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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mtdcr(uicer, 0x00000000); /* disable all ints */ |
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ |
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#ifdef CONFIG_CPCI405_6U |
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#if defined(CONFIG_CPCI405_6U) |
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if (cpci405_version() == 3) { |
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mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ |
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} else { |
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@ -187,21 +192,20 @@ int board_early_init_f (void) |
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mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ |
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#endif |
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mtdcr(uictr, 0x10000000); /* set int trigger levels */ |
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ |
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,
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* INT0 highest priority */ |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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return 0; |
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} |
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/* ------------------------------------------------------------------------- */ |
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int ctermm2(void) |
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{ |
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#ifdef CONFIG_CPCI405_VER2 |
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#if defined(CONFIG_CPCI405_VER2) |
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return 0; /* no, board is cpci405 */ |
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#else |
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if ((*(unsigned char *)0xf0000400 == 0x00) && |
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(*(unsigned char *)0xf0000401 == 0x01)) |
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if ((in_8((void*)0xf0000400) == 0x00) && |
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(in_8((void*)0xf0000401) == 0x01)) |
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return 0; /* no, board is cpci405 */ |
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else |
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return -1; /* yes, board is cterm-m2 */ |
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@ -228,8 +232,8 @@ int cpci405_version(void) |
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mtdcr(cntrl0, cntrl0Reg | 0x03000000); |
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out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); |
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out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); |
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udelay(1000); /* wait some time before reading input */ |
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value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ |
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udelay(1000); /* wait some time before reading input */ |
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value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ |
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/*
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* Restore GPIO settings |
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@ -263,7 +267,7 @@ int misc_init_r (void) |
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
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gd->bd->bi_flashoffset = 0; |
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#ifdef CONFIG_CPCI405_VER2 |
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#if defined(CONFIG_CPCI405_VER2) |
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{ |
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unsigned char *dst; |
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ulong len = sizeof(fpgadata); |
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@ -283,9 +287,10 @@ int misc_init_r (void) |
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mtdcr(cntrl0, cntrl0Reg | 0x00300000); |
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dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); |
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if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { |
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printf ("GUNZIP ERROR - must RESET board to recover\n"); |
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do_reset (NULL, 0, 0, NULL); |
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if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, |
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(uchar *)fpgadata, &len) != 0) { |
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printf("GUNZIP ERROR - must RESET board to recover\n"); |
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do_reset(NULL, 0, 0, NULL); |
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} |
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status = fpga_boot(dst, len); |
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@ -293,31 +298,34 @@ int misc_init_r (void) |
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printf("\nFPGA: Booting failed "); |
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switch (status) { |
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case ERROR_FPGA_PRG_INIT_LOW: |
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printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); |
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printf("(Timeout: INIT not low after " |
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"asserting PROGRAM*)\n "); |
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break; |
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case ERROR_FPGA_PRG_INIT_HIGH: |
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printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); |
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printf("(Timeout: INIT not high after " |
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"deasserting PROGRAM*)\n "); |
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break; |
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case ERROR_FPGA_PRG_DONE: |
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printf("(Timeout: DONE not high after programming FPGA)\n "); |
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printf("(Timeout: DONE not high after " |
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"programming FPGA)\n "); |
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break; |
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} |
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/* display infos on fpgaimage */ |
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index = 15; |
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for (i=0; i<4; i++) { |
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for (i = 0; i < 4; i++) { |
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len = dst[index]; |
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printf("FPGA: %s\n", &(dst[index+1])); |
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index += len+3; |
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printf("FPGA: %s\n", &(dst[index + 1])); |
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index += len + 3; |
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} |
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putc ('\n'); |
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putc('\n'); |
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/* delayed reboot */ |
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for (i=20; i>0; i--) { |
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printf("Rebooting in %2d seconds \r",i); |
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for (index=0;index<1000;index++) |
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for (i = 20; i > 0; i--) { |
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printf("Rebooting in %2d seconds \r", i); |
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for (index = 0; index < 1000; index++) |
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udelay(1000); |
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} |
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putc ('\n'); |
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putc('\n'); |
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do_reset(NULL, 0, 0, NULL); |
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} |
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@ -328,12 +336,12 @@ int misc_init_r (void) |
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/* display infos on fpgaimage */ |
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index = 15; |
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for (i=0; i<4; i++) { |
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for (i = 0; i < 4; i++) { |
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len = dst[index]; |
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printf("%s ", &(dst[index+1])); |
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index += len+3; |
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printf("%s ", &(dst[index + 1])); |
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index += len + 3; |
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} |
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putc ('\n'); |
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putc('\n'); |
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free(dst); |
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@ -345,68 +353,48 @@ int misc_init_r (void) |
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); |
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udelay(1000); /* wait 1ms */ |
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#ifdef CONFIG_CPCI405_6U |
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#if defined(CONFIG_CPCI405_6U) |
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#error HIER GETH ES WEITER MIT IO ACCESSORS |
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if (cpci405_version() == 3) { |
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volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR; |
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volatile unsigned char *leds = (unsigned char *)CONFIG_SYS_LED_ADDR; |
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/*
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* Enable outputs in fpga on version 3 board |
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*/ |
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*fpga_mode |= CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT; |
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out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, |
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in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | |
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CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT); |
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/*
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* Set outputs to 0 |
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*/ |
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*leds = 0x00; |
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out_8((void*)CONFIG_SYS_LED_ADDR, 0x00); |
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/*
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* Reset external DUART |
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*/ |
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*fpga_mode |= CONFIG_SYS_FPGA_MODE_DUART_RESET; |
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out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, |
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in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | |
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CONFIG_SYS_FPGA_MODE_DUART_RESET); |
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udelay(100); |
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*fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_DUART_RESET); |
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out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, |
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in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) & |
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~CONFIG_SYS_FPGA_MODE_DUART_RESET); |
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} |
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#endif |
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} |
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|
else { |
|
|
|
|
puts("\n*** U-Boot Version does not match Board Version!\n"); |
|
|
|
|
puts("*** CPCI-405 Version 1.x detected!\n"); |
|
|
|
|
puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n"); |
|
|
|
|
puts("*** Please use correct U-Boot version " |
|
|
|
|
"(CPCI405 instead of CPCI4052)!\n\n"); |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
#else /* CONFIG_CPCI405_VER2 */ |
|
|
|
|
|
|
|
|
|
#if 0 /* test-only: code-plug now not relavant for ip-address any more */
|
|
|
|
|
/*
|
|
|
|
|
* Generate last byte of ip-addr from code-plug @ 0xf0000400 |
|
|
|
|
*/ |
|
|
|
|
if (ctermm2()) { |
|
|
|
|
char str[32]; |
|
|
|
|
unsigned char ipbyte = *(unsigned char *)0xf0000400; |
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Only overwrite ip-addr with allowed values |
|
|
|
|
*/ |
|
|
|
|
if ((ipbyte != 0x00) && (ipbyte != 0xff)) { |
|
|
|
|
bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte; |
|
|
|
|
sprintf(str, "%ld.%ld.%ld.%ld", |
|
|
|
|
(bd->bi_ip_addr & 0xff000000) >> 24, |
|
|
|
|
(bd->bi_ip_addr & 0x00ff0000) >> 16, |
|
|
|
|
(bd->bi_ip_addr & 0x0000ff00) >> 8, |
|
|
|
|
(bd->bi_ip_addr & 0x000000ff)); |
|
|
|
|
setenv("ipaddr", str); |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
if (cpci405_version() >= 2) { |
|
|
|
|
puts("\n*** U-Boot Version does not match Board Version!\n"); |
|
|
|
|
puts("*** CPCI-405 Board Version 2.x detected!\n"); |
|
|
|
|
puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n"); |
|
|
|
|
puts("*** Please use correct U-Boot version " |
|
|
|
|
"(CPCI4052 instead of CPCI405)!\n\n"); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_CPCI405_VER2 */ |
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
@ -415,46 +403,33 @@ int misc_init_r (void) |
|
|
|
|
cntrl0Reg = mfdcr(cntrl0); |
|
|
|
|
mtdcr(cntrl0, cntrl0Reg | 0x00001000); |
|
|
|
|
|
|
|
|
|
return (0); |
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Check Board Identity: |
|
|
|
|
*/ |
|
|
|
|
|
|
|
|
|
int checkboard (void) |
|
|
|
|
int checkboard(void) |
|
|
|
|
{ |
|
|
|
|
#ifndef CONFIG_CPCI405_VER2 |
|
|
|
|
int index; |
|
|
|
|
int len; |
|
|
|
|
#endif |
|
|
|
|
char str[64]; |
|
|
|
|
int i = getenv_r ("serial#", str, sizeof(str)); |
|
|
|
|
int i = getenv_r("serial#", str, sizeof(str)); |
|
|
|
|
unsigned short ver; |
|
|
|
|
|
|
|
|
|
puts ("Board: "); |
|
|
|
|
puts("Board: "); |
|
|
|
|
|
|
|
|
|
if (i == -1) { |
|
|
|
|
puts ("### No HW ID - assuming CPCI405"); |
|
|
|
|
} else { |
|
|
|
|
if (i == -1) |
|
|
|
|
puts("### No HW ID - assuming CPCI405"); |
|
|
|
|
else |
|
|
|
|
puts(str); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
ver = cpci405_version(); |
|
|
|
|
printf(" (Ver %d.x, ", ver); |
|
|
|
|
|
|
|
|
|
#if 0 /* test-only */
|
|
|
|
|
if (ver >= 2) { |
|
|
|
|
volatile u16 *fpga_status = (u16 *)CONFIG_SYS_FPGA_BASE_ADDR + 1; |
|
|
|
|
|
|
|
|
|
if (*fpga_status & CONFIG_SYS_FPGA_STATUS_FLASH) { |
|
|
|
|
puts ("FLASH Bank B, "); |
|
|
|
|
} else { |
|
|
|
|
puts ("FLASH Bank A, "); |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
if (ctermm2()) { |
|
|
|
|
char str[4]; |
|
|
|
|
|
|
|
|
@ -465,32 +440,31 @@ int checkboard (void) |
|
|
|
|
setenv("boardid", str); |
|
|
|
|
printf("CTERM-M2 - Id=%s)", str); |
|
|
|
|
} else { |
|
|
|
|
if (cpci405_host()) { |
|
|
|
|
puts ("PCI Host Version)"); |
|
|
|
|
} else { |
|
|
|
|
puts ("PCI Adapter Version)"); |
|
|
|
|
} |
|
|
|
|
if (cpci405_host()) |
|
|
|
|
puts("PCI Host Version)"); |
|
|
|
|
else |
|
|
|
|
puts("PCI Adapter Version)"); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
#ifndef CONFIG_CPCI405_VER2 |
|
|
|
|
puts ("\nFPGA: "); |
|
|
|
|
puts("\nFPGA: "); |
|
|
|
|
|
|
|
|
|
/* display infos on fpgaimage */ |
|
|
|
|
index = 15; |
|
|
|
|
for (i=0; i<4; i++) { |
|
|
|
|
for (i = 0; i < 4; i++) { |
|
|
|
|
len = fpgadata[index]; |
|
|
|
|
printf("%s ", &(fpgadata[index+1])); |
|
|
|
|
index += len+3; |
|
|
|
|
printf("%s ", &(fpgadata[index + 1])); |
|
|
|
|
index += len + 3; |
|
|
|
|
} |
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
putc ('\n'); |
|
|
|
|
putc('\n'); |
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
void reset_phy(void) |
|
|
|
|
{ |
|
|
|
|
#ifdef CONFIG_LXT971_NO_SLEEP |
|
|
|
|
#if defined(CONFIG_LXT971_NO_SLEEP) |
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Disable sleep mode in LXT971 |
|
|
|
@ -499,25 +473,24 @@ void reset_phy(void) |
|
|
|
|
#endif |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_CPCI405_VER2 |
|
|
|
|
#ifdef CONFIG_IDE_RESET |
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET) |
|
|
|
|
void ide_set_reset(int on) |
|
|
|
|
{ |
|
|
|
|
volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR; |
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Assert or deassert CompactFlash Reset Pin |
|
|
|
|
*/ |
|
|
|
|
if (on) { /* assert RESET */ |
|
|
|
|
*fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_CF_RESET); |
|
|
|
|
} else { /* release RESET */ |
|
|
|
|
*fpga_mode |= CONFIG_SYS_FPGA_MODE_CF_RESET; |
|
|
|
|
if (on) { /* assert RESET */ |
|
|
|
|
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, |
|
|
|
|
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) & |
|
|
|
|
~CONFIG_SYS_FPGA_MODE_CF_RESET); |
|
|
|
|
} else { /* release RESET */ |
|
|
|
|
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, |
|
|
|
|
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | |
|
|
|
|
CONFIG_SYS_FPGA_MODE_CF_RESET); |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_IDE_RESET */ |
|
|
|
|
#endif /* CONFIG_CPCI405_VER2 */ |
|
|
|
|
#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */ |
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_PCI) |
|
|
|
|
void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) |
|
|
|
@ -552,15 +525,44 @@ int pci_pre_init(struct pci_controller *hose) |
|
|
|
|
} |
|
|
|
|
#endif /* defined(CONFIG_PCI) */ |
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
|
|
|
|
void ft_board_setup(void *blob, bd_t *bd) |
|
|
|
|
{ |
|
|
|
|
int rc; |
|
|
|
|
|
|
|
|
|
__ft_board_setup(blob, bd); |
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Disable PCI in adapter mode. |
|
|
|
|
*/ |
|
|
|
|
if (!cpci405_host()) { |
|
|
|
|
rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status", |
|
|
|
|
"disabled", sizeof("disabled"), 1); |
|
|
|
|
if (rc) { |
|
|
|
|
printf("Unable to update property status in PCI node, " |
|
|
|
|
"err=%s\n", |
|
|
|
|
fdt_strerror(rc)); |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_CPCI405AB) |
|
|
|
|
#define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ |
|
|
|
|
CONFIG_SYS_FPGA_MODE), \
|
|
|
|
|
in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
|
|
|
|
|
CONFIG_SYS_FPGA_MODE)) | \
|
|
|
|
|
CONFIG_SYS_FPGA_MODE_1WIRE_DIR) |
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_CPCI405AB |
|
|
|
|
#define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ |
|
|
|
|
CONFIG_SYS_FPGA_MODE), \
|
|
|
|
|
in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
|
|
|
|
|
CONFIG_SYS_FPGA_MODE)) & \
|
|
|
|
|
~CONFIG_SYS_FPGA_MODE_1WIRE_DIR) |
|
|
|
|
|
|
|
|
|
#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \ |
|
|
|
|
|= CONFIG_SYS_FPGA_MODE_1WIRE_DIR) |
|
|
|
|
#define ONE_WIRE_SET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \ |
|
|
|
|
&= ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR) |
|
|
|
|
#define ONE_WIRE_GET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_STATUS) \ |
|
|
|
|
& CONFIG_SYS_FPGA_MODE_1WIRE) |
|
|
|
|
#define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ |
|
|
|
|
CONFIG_SYS_FPGA_STATUS)) & \
|
|
|
|
|
CONFIG_SYS_FPGA_MODE_1WIRE) |
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Generate a 1-wire reset, return 1 if no presence detect was found, |
|
|
|
@ -630,7 +632,7 @@ void OWWriteByte(int data) |
|
|
|
|
{ |
|
|
|
|
int loop; |
|
|
|
|
|
|
|
|
|
for (loop=0; loop<8; loop++) { |
|
|
|
|
for (loop = 0; loop < 8; loop++) { |
|
|
|
|
OWWriteBit(data & 0x01); |
|
|
|
|
data >>= 1; |
|
|
|
|
} |
|
|
|
@ -640,11 +642,10 @@ int OWReadByte(void) |
|
|
|
|
{ |
|
|
|
|
int loop, result = 0; |
|
|
|
|
|
|
|
|
|
for (loop=0; loop<8; loop++) { |
|
|
|
|
for (loop = 0; loop < 8; loop++) { |
|
|
|
|
result >>= 1; |
|
|
|
|
if (OWReadBit()) { |
|
|
|
|
if (OWReadBit()) |
|
|
|
|
result |= 0x80; |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
return result; |
|
|
|
@ -652,7 +653,7 @@ int OWReadByte(void) |
|
|
|
|
|
|
|
|
|
int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
|
|
|
|
{ |
|
|
|
|
volatile unsigned short val; |
|
|
|
|
unsigned short val; |
|
|
|
|
int result; |
|
|
|
|
int i; |
|
|
|
|
unsigned char ow_id[6]; |
|
|
|
@ -662,23 +663,25 @@ int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
|
|
|
|
/*
|
|
|
|
|
* Clear 1-wire bit (open drain with pull-up) |
|
|
|
|
*/ |
|
|
|
|
val = *(volatile unsigned short *)0xf0400000; |
|
|
|
|
val &= ~0x1000; /* clear 1-wire bit */ |
|
|
|
|
*(volatile unsigned short *)0xf0400000 = val; |
|
|
|
|
val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + |
|
|
|
|
CONFIG_SYS_FPGA_MODE)); |
|
|
|
|
val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */ |
|
|
|
|
out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + |
|
|
|
|
CONFIG_SYS_FPGA_MODE), val); |
|
|
|
|
|
|
|
|
|
result = OWTouchReset(); |
|
|
|
|
if (result != 0) { |
|
|
|
|
if (result != 0) |
|
|
|
|
puts("No 1-wire device detected!\n"); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
OWWriteByte(0x33); /* send read rom command */ |
|
|
|
|
OWReadByte(); /* skip family code ( == 0x01) */ |
|
|
|
|
for (i=0; i<6; i++) { |
|
|
|
|
for (i = 0; i < 6; i++) |
|
|
|
|
ow_id[i] = OWReadByte(); |
|
|
|
|
} |
|
|
|
|
ow_crc = OWReadByte(); /* read crc */ |
|
|
|
|
|
|
|
|
|
sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]); |
|
|
|
|
sprintf(str, "%08X%04X", |
|
|
|
|
*(unsigned int *)&ow_id[0], |
|
|
|
|
*(unsigned short *)&ow_id[4]); |
|
|
|
|
printf("Setting environment variable 'ow_id' to %s\n", str); |
|
|
|
|
setenv("ow_id", str); |
|
|
|
|
|
|
|
|
@ -690,8 +693,8 @@ U_BOOT_CMD( |
|
|
|
|
NULL |
|
|
|
|
); |
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ |
|
|
|
|
#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/ |
|
|
|
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */ |
|
|
|
|
#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */ |
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Write backplane ip-address... |
|
|
|
@ -706,12 +709,14 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
|
|
|
|
IPaddr_t ipaddr; |
|
|
|
|
|
|
|
|
|
buf = malloc(CONFIG_ENV_SIZE_2); |
|
|
|
|
if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { |
|
|
|
|
if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, |
|
|
|
|
(uchar *)buf, CONFIG_ENV_SIZE_2)) |
|
|
|
|
puts("\nError reading backplane EEPROM!\n"); |
|
|
|
|
} else { |
|
|
|
|
crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4); |
|
|
|
|
else { |
|
|
|
|
crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4); |
|
|
|
|
if (crc != *(ulong *)buf) { |
|
|
|
|
printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf); |
|
|
|
|
printf("ERROR: crc mismatch %08lx %08lx\n", |
|
|
|
|
crc, *(ulong *)buf); |
|
|
|
|
return -1; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
@ -768,12 +773,12 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
|
|
|
|
memset(buf, 0, CONFIG_ENV_SIZE_2); |
|
|
|
|
sprintf(str, "bp_ip=%s", argv[1]); |
|
|
|
|
strcpy(buf+4, str); |
|
|
|
|
crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4); |
|
|
|
|
crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4); |
|
|
|
|
*(ulong *)buf = crc; |
|
|
|
|
|
|
|
|
|
if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { |
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if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, |
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0, (uchar *)buf, CONFIG_ENV_SIZE_2)) |
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puts("\nError writing backplane EEPROM!\n"); |
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} |
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free(buf); |
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