diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 2922816..9bb1a1c 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -290,8 +290,8 @@ void watchdog_init(void)
 	 * should not be running and does not generate a PRCM reset.
 	 */
 
-	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
-	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
+	setbits_le32(&prcm_base->fclken_wkup, 0x20);
+	setbits_le32(&prcm_base->iclken_wkup, 0x20);
 	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
 
 	writel(WD_UNLOCK1, &wd2_base->wspr);
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 5ab6db9..0dfb4ad 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -308,7 +308,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 	/* Now we can enable our port clocks */
 	utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
 	utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
-	sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
+	setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
 
 	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
 	if (ret < 0)