Add DTS support for dra72 evm Rev C which has the following changes * Two ethernet ports now instead of the single one in rev B. * DP83867 ethernet phy instead of DP838865. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>master
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692fcdd800
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e8131386dc
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/* |
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* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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/dts-v1/; |
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|
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#include "dra72x.dtsi" |
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#include <dt-bindings/gpio/gpio.h> |
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|
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/ { |
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compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; |
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|
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chosen { |
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stdout-path = &uart1; |
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tick-timer = &timer2; |
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}; |
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|
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aliases { |
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display0 = &hdmi0; |
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}; |
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|
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evm_3v3: fixedregulator-evm_3v3 { |
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compatible = "regulator-fixed"; |
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regulator-name = "evm_3v3"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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}; |
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|
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extcon_usb1: extcon_usb1 { |
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compatible = "linux,extcon-usb-gpio"; |
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id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; |
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}; |
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|
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extcon_usb2: extcon_usb2 { |
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compatible = "linux,extcon-usb-gpio"; |
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id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; |
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}; |
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|
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hdmi0: connector { |
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compatible = "hdmi-connector"; |
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label = "hdmi"; |
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type = "a"; |
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port { |
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hdmi_connector_in: endpoint { |
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remote-endpoint = <&tpd12s015_out>; |
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}; |
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}; |
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}; |
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|
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tpd12s015: encoder { |
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compatible = "ti,tpd12s015"; |
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gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ |
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<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ |
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<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ |
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|
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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tpd12s015_in: endpoint { |
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remote-endpoint = <&hdmi_out>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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tpd12s015_out: endpoint { |
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remote-endpoint = <&hdmi_connector_in>; |
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}; |
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}; |
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}; |
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}; |
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}; |
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&dra7_pmx_core { |
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mmc1_pins_default: mmc1_pins_default { |
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pinctrl-single,pins = < |
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0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ |
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0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ |
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0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ |
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0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ |
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0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ |
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0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ |
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>; |
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}; |
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mmc2_pins_default: mmc2_pins_default { |
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pinctrl-single,pins = < |
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0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ |
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0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ |
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0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ |
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0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ |
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0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ |
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0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ |
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0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ |
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0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ |
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0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ |
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0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ |
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>; |
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}; |
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dcan1_pins_default: dcan1_pins_default { |
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pinctrl-single,pins = < |
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0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ |
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0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ |
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>; |
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}; |
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dcan1_pins_sleep: dcan1_pins_sleep { |
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pinctrl-single,pins = < |
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0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ |
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0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ |
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>; |
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}; |
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}; |
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&i2c1 { |
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status = "okay"; |
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clock-frequency = <400000>; |
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tps65917: tps65917@58 { |
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compatible = "ti,tps65917"; |
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reg = <0x58>; |
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interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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ti,system-power-controller; |
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tps65917_pmic { |
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compatible = "ti,tps65917-pmic"; |
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tps65917_regulators: regulators { |
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smps1_reg: smps1 { |
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/* VDD_MPU */ |
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regulator-name = "smps1"; |
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regulator-min-microvolt = <850000>; |
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regulator-max-microvolt = <1250000>; |
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regulator-always-on; |
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regulator-boot-on; |
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}; |
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smps2_reg: smps2 { |
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/* VDD_CORE */ |
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regulator-name = "smps2"; |
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regulator-min-microvolt = <850000>; |
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regulator-max-microvolt = <1060000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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smps3_reg: smps3 { |
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/* VDD_GPU IVA DSPEVE */ |
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regulator-name = "smps3"; |
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regulator-min-microvolt = <850000>; |
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regulator-max-microvolt = <1250000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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smps4_reg: smps4 { |
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/* VDDS1V8 */ |
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regulator-name = "smps4"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-always-on; |
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regulator-boot-on; |
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}; |
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smps5_reg: smps5 { |
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/* VDD_DDR */ |
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regulator-name = "smps5"; |
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regulator-min-microvolt = <1350000>; |
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regulator-max-microvolt = <1350000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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ldo1_reg: ldo1 { |
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/* LDO1_OUT --> SDIO */ |
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regulator-name = "ldo1"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-allow-bypass; |
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}; |
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ldo3_reg: ldo3 { |
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/* VDDA_1V8_PHY */ |
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regulator-name = "ldo3"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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ldo5_reg: ldo5 { |
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/* VDDA_1V8_PLL */ |
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regulator-name = "ldo5"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-always-on; |
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regulator-boot-on; |
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}; |
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ldo4_reg: ldo4 { |
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/* VDDA_3V_USB: VDDA_USBHS33 */ |
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regulator-name = "ldo4"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-boot-on; |
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}; |
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}; |
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}; |
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tps65917_power_button { |
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compatible = "ti,palmas-pwrbutton"; |
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interrupt-parent = <&tps65917>; |
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interrupts = <1 IRQ_TYPE_NONE>; |
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wakeup-source; |
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ti,palmas-long-press-seconds = <6>; |
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}; |
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}; |
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pcf_gpio_21: gpio@21 { |
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compatible = "ti,pcf8575"; |
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u-boot,i2c-offset-len = <0>; |
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reg = <0x21>; |
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lines-initial-states = <0x1408>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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}; |
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&i2c5 { |
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status = "okay"; |
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clock-frequency = <400000>; |
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pcf_hdmi: pcf8575@26 { |
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compatible = "nxp,pcf8575"; |
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u-boot,i2c-offset-len = <0>; |
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reg = <0x26>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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/* |
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* initial state is used here to keep the mdio interface |
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* selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and |
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* VIN2_S0 driven high otherwise Ethernet stops working |
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* VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 |
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*/ |
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lines-initial-states = <0x0f2b>; |
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p1 { |
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/* vin6_sel_s0: high: VIN6, low: audio */ |
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gpio-hog; |
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gpios = <1 GPIO_ACTIVE_HIGH>; |
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output-low; |
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line-name = "vin6_sel_s0"; |
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}; |
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}; |
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}; |
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&uart1 { |
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status = "okay"; |
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interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, |
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<&dra7_pmx_core 0x3e0>; |
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}; |
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&elm { |
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status = "okay"; |
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}; |
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&gpmc { |
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/* |
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* For the existing IOdelay configuration via U-Boot we don't |
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* support NAND on dra72-evm. Keep it disabled. Enabling it |
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* requires a different configuration by U-Boot. |
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*/ |
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status = "disabled"; |
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ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ |
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nand@0,0 { |
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/* To use NAND, DIP switch SW5 must be set like so: |
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* SW5.1 (NAND_SELn) = ON (LOW) |
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* SW5.9 (GPMC_WPN) = OFF (HIGH) |
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*/ |
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compatible = "ti,omap2-nand"; |
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reg = <0 0 4>; /* device IO registers */ |
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interrupt-parent = <&gpmc>; |
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ |
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<1 IRQ_TYPE_NONE>; /* termcount */ |
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rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ /* device IO registers */ |
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ti,nand-ecc-opt = "bch8"; |
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ti,elm-id = <&elm>; |
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nand-bus-width = <16>; |
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gpmc,device-width = <2>; |
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gpmc,sync-clk-ps = <0>; |
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gpmc,cs-on-ns = <0>; |
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gpmc,cs-rd-off-ns = <80>; |
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gpmc,cs-wr-off-ns = <80>; |
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gpmc,adv-on-ns = <0>; |
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gpmc,adv-rd-off-ns = <60>; |
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gpmc,adv-wr-off-ns = <60>; |
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gpmc,we-on-ns = <10>; |
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gpmc,we-off-ns = <50>; |
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gpmc,oe-on-ns = <4>; |
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gpmc,oe-off-ns = <40>; |
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gpmc,access-ns = <40>; |
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gpmc,wr-access-ns = <80>; |
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gpmc,rd-cycle-ns = <80>; |
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gpmc,wr-cycle-ns = <80>; |
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gpmc,bus-turnaround-ns = <0>; |
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gpmc,cycle2cycle-delay-ns = <0>; |
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gpmc,clk-activation-ns = <0>; |
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gpmc,wait-monitoring-ns = <0>; |
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gpmc,wr-data-mux-bus-ns = <0>; |
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/* MTD partition table */ |
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/* All SPL-* partitions are sized to minimal length |
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* which can be independently programmable. For |
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* NAND flash this is equal to size of erase-block */ |
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#address-cells = <1>; |
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#size-cells = <1>; |
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partition@0 { |
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label = "NAND.SPL"; |
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reg = <0x00000000 0x000020000>; |
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}; |
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partition@1 { |
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label = "NAND.SPL.backup1"; |
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reg = <0x00020000 0x00020000>; |
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}; |
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partition@2 { |
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label = "NAND.SPL.backup2"; |
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reg = <0x00040000 0x00020000>; |
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}; |
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partition@3 { |
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label = "NAND.SPL.backup3"; |
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reg = <0x00060000 0x00020000>; |
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}; |
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partition@4 { |
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label = "NAND.u-boot-spl-os"; |
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reg = <0x00080000 0x00040000>; |
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}; |
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partition@5 { |
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label = "NAND.u-boot"; |
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reg = <0x000c0000 0x00100000>; |
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}; |
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partition@6 { |
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label = "NAND.u-boot-env"; |
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reg = <0x001c0000 0x00020000>; |
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}; |
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partition@7 { |
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label = "NAND.u-boot-env.backup1"; |
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reg = <0x001e0000 0x00020000>; |
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}; |
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partition@8 { |
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label = "NAND.kernel"; |
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reg = <0x00200000 0x00800000>; |
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}; |
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partition@9 { |
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label = "NAND.file-system"; |
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reg = <0x00a00000 0x0f600000>; |
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}; |
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}; |
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}; |
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&usb2_phy1 { |
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phy-supply = <&ldo4_reg>; |
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}; |
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&usb2_phy2 { |
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phy-supply = <&ldo4_reg>; |
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}; |
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&omap_dwc3_1 { |
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extcon = <&extcon_usb1>; |
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}; |
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&omap_dwc3_2 { |
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extcon = <&extcon_usb2>; |
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}; |
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&usb1 { |
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dr_mode = "otg"; |
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}; |
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&usb2 { |
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dr_mode = "host"; |
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}; |
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&mmc1 { |
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status = "okay"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&mmc1_pins_default>; |
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vmmc_aux-supply = <&ldo1_reg>; |
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bus-width = <4>; |
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/* |
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* SDCD signal is not being used here - using the fact that GPIO mode |
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* is a viable alternative |
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*/ |
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cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; |
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max-frequency = <192000000>; |
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}; |
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&mmc2 { |
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/* SW5-3 in ON position */ |
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status = "okay"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&mmc2_pins_default>; |
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vmmc-supply = <&evm_3v3>; |
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bus-width = <8>; |
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ti,non-removable; |
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max-frequency = <192000000>; |
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}; |
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&mac { |
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status = "okay"; |
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}; |
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&dcan1 { |
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status = "ok"; |
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}; |
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&qspi { |
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status = "okay"; |
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spi-max-frequency = <76800000>; |
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m25p80@0 { |
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compatible = "s25fl256s1", "spi-flash"; |
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spi-max-frequency = <64000000>; |
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reg = <0>; |
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spi-tx-bus-width = <1>; |
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spi-rx-bus-width = <4>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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|
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/* MTD partition table. |
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* The ROM checks the first four physical blocks |
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* for a valid file to boot and the flash here is |
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* 64KiB block size. |
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*/ |
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partition@0 { |
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label = "QSPI.SPL"; |
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reg = <0x00000000 0x000010000>; |
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}; |
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partition@1 { |
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label = "QSPI.SPL.backup1"; |
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reg = <0x00010000 0x00010000>; |
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}; |
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partition@2 { |
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label = "QSPI.SPL.backup2"; |
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reg = <0x00020000 0x00010000>; |
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}; |
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partition@3 { |
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label = "QSPI.SPL.backup3"; |
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reg = <0x00030000 0x00010000>; |
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}; |
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partition@4 { |
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label = "QSPI.u-boot"; |
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reg = <0x00040000 0x00100000>; |
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}; |
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partition@5 { |
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label = "QSPI.u-boot-spl-os"; |
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reg = <0x00140000 0x00080000>; |
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}; |
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partition@6 { |
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label = "QSPI.u-boot-env"; |
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reg = <0x001c0000 0x00010000>; |
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}; |
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partition@7 { |
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label = "QSPI.u-boot-env.backup1"; |
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reg = <0x001d0000 0x0010000>; |
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}; |
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partition@8 { |
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label = "QSPI.kernel"; |
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reg = <0x001e0000 0x0800000>; |
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}; |
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partition@9 { |
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label = "QSPI.file-system"; |
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reg = <0x009e0000 0x01620000>; |
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}; |
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}; |
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}; |
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|
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&dss { |
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status = "ok"; |
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vdda_video-supply = <&ldo5_reg>; |
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}; |
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&hdmi { |
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status = "ok"; |
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|
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port { |
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hdmi_out: endpoint { |
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remote-endpoint = <&tpd12s015_in>; |
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}; |
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}; |
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}; |
@ -0,0 +1,70 @@ |
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/* |
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* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#include "dra72-evm-common.dtsi" |
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#include <dt-bindings/net/ti-dp83867.h> |
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|
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/ { |
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model = "TI DRA722 Rev C EVM"; |
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|
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memory { |
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device_type = "memory"; |
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reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ |
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}; |
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}; |
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|
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&tps65917_regulators { |
||||
ldo2_reg: ldo2 { |
||||
/* LDO2_OUT --> VDDA_1V8_PHY2 */ |
||||
regulator-name = "ldo2"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-always-on; |
||||
regulator-boot-on; |
||||
}; |
||||
}; |
||||
|
||||
&hdmi { |
||||
vdda_video-supply = <&ldo2_reg>; |
||||
}; |
||||
|
||||
&mac { |
||||
mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, |
||||
<&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ |
||||
<&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ |
||||
dual_emac; |
||||
}; |
||||
|
||||
&cpsw_emac0 { |
||||
phy-handle = <&dp83867_0>; |
||||
phy-mode = "rgmii-id"; |
||||
dual_emac_res_vlan = <1>; |
||||
}; |
||||
|
||||
&cpsw_emac1 { |
||||
phy-handle = <&dp83867_1>; |
||||
phy-mode = "rgmii-id"; |
||||
dual_emac_res_vlan = <2>; |
||||
}; |
||||
|
||||
&davinci_mdio { |
||||
dp83867_0: ethernet-phy@2 { |
||||
reg = <2>; |
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; |
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; |
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; |
||||
ti,min-output-imepdance; |
||||
}; |
||||
|
||||
dp83867_1: ethernet-phy@3 { |
||||
reg = <3>; |
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; |
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; |
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; |
||||
ti,min-output-imepdance; |
||||
}; |
||||
}; |
Loading…
Reference in new issue