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arm: dra7xx: clock: Add the dplls data

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A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
master
Lokesh Vutla 12 years ago committed by Tom Rini
parent d4e4129c31
commit ea8eff1fe0
4 changed files with 94 additions and 8 deletions
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  1. 26
      arch/arm/cpu/armv7/omap-common/clocks-common.c
  2. 9
      arch/arm/cpu/armv7/omap4/hw_data.c
  3. 64
      arch/arm/cpu/armv7/omap5/hw_data.c
  4. 3
      arch/arm/include/asm/omap_common.h

26
arch/arm/cpu/armv7/omap-common/clocks-common.c
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@ -55,11 +55,12 @@ const u32 sys_clk_array[8] = {
26000000, /* 26 MHz */
27000000, /* 27 MHz */
38400000, /* 38.4 MHz */
20000000, /* 20 MHz */
};
static inline u32 __get_sys_clk_index(void)
{
u32 ind;
s8 ind;
/*
* For ES1 the ROM code calibration of sys clock is not reliable
* due to hw issue. So, use hard-coded value. If this value is not
@ -73,6 +74,13 @@ static inline u32 __get_sys_clk_index(void)
/* SYS_CLKSEL - 1 to match the dpll param array indices */
ind = (readl((*prcm)->cm_sys_clksel) &
CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
/*
* SYS_CLKSEL value for 20MHz is 0. This is introduced newly
* in DRA7XX socs. SYS_CLKSEL -1 will be greater than
* NUM_SYS_CLK. So considering the last 3 bits as the index
* for the dpll param array.
*/
ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
}
return ind;
}
@ -201,12 +209,25 @@ const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
#endif
}
static const struct dpll_params *get_ddr_dpll_params
(struct dplls const *dpll_data)
{
u32 sysclk_ind = get_sys_clk_index();
if (!dpll_data->ddr)
return NULL;
return &dpll_data->ddr[sysclk_ind];
}
static void do_setup_dpll(u32 const base, const struct dpll_params *params,
u8 lock, char *dpll)
{
u32 temp, M, N;
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
if (!params)
return;
temp = readl(&dpll_regs->cm_clksel_dpll);
if (check_for_lock(base)) {
@ -397,6 +418,9 @@ static void setup_dplls(void)
#ifdef CONFIG_USB_EHCI_OMAP
setup_usb_dpll();
#endif
params = get_ddr_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
params, DPLL_LOCK, "ddr");
}
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL

9
arch/arm/cpu/armv7/omap4/hw_data.c
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@ -182,7 +182,8 @@ struct dplls omap4430_dplls_es1 = {
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls omap4430_dplls = {
@ -195,7 +196,8 @@ struct dplls omap4430_dplls = {
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls omap4460_dplls = {
@ -208,7 +210,8 @@ struct dplls omap4460_dplls = {
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct pmic_data twl6030_4430es1 = {

64
arch/arm/cpu/armv7/omap5/hw_data.c
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@ -98,6 +98,17 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
{493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
{250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
{266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
@ -121,6 +132,18 @@ static const struct dpll_params
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
{266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */
{277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */
{368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */
{266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
{266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
@ -162,6 +185,17 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
{10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
{32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
{96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
@ -196,7 +230,19 @@ static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
{48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
};
static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = {
{533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
{533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
};
struct dplls omap5_dplls_es1 = {
@ -209,7 +255,8 @@ struct dplls omap5_dplls_es1 = {
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls omap5_dplls_es2 = {
@ -222,7 +269,16 @@ struct dplls omap5_dplls_es2 = {
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls dra7xx_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_ddr532_dra7xx,
.per = per_dpll_params_768mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_1066mhz,
};
struct pmic_data palmas = {
@ -505,6 +561,8 @@ void hw_data_init(void)
case DRA752_ES1_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra7xx_dplls;
*omap_vcores = &omap5430_volts_es2;
break;
default:

3
arch/arm/include/asm/omap_common.h
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@ -27,7 +27,7 @@
#include <common.h>
#define NUM_SYS_CLKS 7
#define NUM_SYS_CLKS 8
struct prcm_regs {
/* cm1.ckgen */
@ -473,6 +473,7 @@ struct dplls {
const struct dpll_params *abe;
const struct dpll_params *iva;
const struct dpll_params *usb;
const struct dpll_params *ddr;
};
struct pmic_data {

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