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@ -16,18 +16,18 @@ |
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/* Dual SPI flash memories - see SPI_COMM_DUAL_... */ |
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enum spi_dual_flash { |
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SF_SINGLE_FLASH = 0, |
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SF_DUAL_STACKED_FLASH = 1 << 0, |
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SF_DUAL_PARALLEL_FLASH = 1 << 1, |
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SF_DUAL_STACKED_FLASH = BIT(0), |
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SF_DUAL_PARALLEL_FLASH = BIT(1), |
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}; |
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/* Enum list - Full read commands */ |
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enum spi_read_cmds { |
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ARRAY_SLOW = 1 << 0, |
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ARRAY_FAST = 1 << 1, |
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DUAL_OUTPUT_FAST = 1 << 2, |
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DUAL_IO_FAST = 1 << 3, |
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QUAD_OUTPUT_FAST = 1 << 4, |
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QUAD_IO_FAST = 1 << 5, |
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ARRAY_SLOW = BIT(0), |
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ARRAY_FAST = BIT(1), |
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DUAL_OUTPUT_FAST = BIT(2), |
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DUAL_IO_FAST = BIT(3), |
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QUAD_OUTPUT_FAST = BIT(4), |
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QUAD_IO_FAST = BIT(5), |
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}; |
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/* Normal - Extended - Full command set */ |
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@ -37,20 +37,20 @@ enum spi_read_cmds { |
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/* sf param flags */ |
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enum { |
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#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS |
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SECT_4K = 1 << 0, |
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#ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS |
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SECT_4K = 0, |
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#else |
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SECT_4K = 0 << 0, |
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SECT_4K = BIT(0), |
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#endif |
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SECT_32K = 1 << 1, |
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E_FSR = 1 << 2, |
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SST_WR = 1 << 3, |
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WR_QPP = 1 << 4, |
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SECT_32K = BIT(1), |
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E_FSR = BIT(2), |
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SST_WR = BIT(3), |
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WR_QPP = BIT(4), |
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}; |
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enum spi_nor_option_flags { |
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SNOR_F_SST_WR = (1 << 0), |
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SNOR_F_USE_FSR = (1 << 1), |
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SNOR_F_SST_WR = BIT(0), |
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SNOR_F_USE_FSR = BIT(1), |
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}; |
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#define SPI_FLASH_3B_ADDR_LEN 3 |
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@ -100,10 +100,10 @@ enum spi_nor_option_flags { |
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#endif |
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/* Common status */ |
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#define STATUS_WIP (1 << 0) |
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#define STATUS_QEB_WINSPAN (1 << 1) |
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#define STATUS_QEB_MXIC (1 << 6) |
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#define STATUS_PEC (1 << 7) |
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#define STATUS_WIP BIT(0) |
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#define STATUS_QEB_WINSPAN BIT(1) |
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#define STATUS_QEB_MXIC BIT(6) |
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#define STATUS_PEC BIT(7) |
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#define SR_BP0 BIT(2) /* Block protect 0 */ |
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#define SR_BP1 BIT(3) /* Block protect 1 */ |
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#define SR_BP2 BIT(4) /* Block protect 2 */ |
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