Tom Rini
10 years ago
commit
ec0cc98f2c
@ -0,0 +1,15 @@ |
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/*
|
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/*
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* Dummy header file to enable CONFIG_OF_CONTROL. |
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* If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. |
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* It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable |
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* OF_CONTROL must have arch/gpio.h. |
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*/ |
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|
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#ifndef __ASM_ARCH_MX85XX_GPIO_H |
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#define __ASM_ARCH_MX85XX_GPIO_H |
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#endif |
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@ -1,7 +1,7 @@ |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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#serdes protocol 27_56_1_9 |
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#serdes protocol 27_55_1_9 |
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16070019 18101916 00000000 00000000 |
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6c700848 00448c00 6c020000 f5000000 |
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6c6e0848 00448c00 6c020000 f5000000 |
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00000000 ee0000ee 00000000 000287fc |
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00000000 50000000 00000000 00000028 |
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@ -0,0 +1,4 @@ |
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CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT" |
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CONFIG_PPC=y |
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CONFIG_MPC85xx=y |
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CONFIG_TARGET_C29XPCIE=y |
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@ -0,0 +1,4 @@ |
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CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT" |
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CONFIG_PPC=y |
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CONFIG_MPC85xx=y |
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CONFIG_TARGET_C29XPCIE=y |
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@ -0,0 +1,4 @@ |
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CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" |
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CONFIG_PPC=y |
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CONFIG_MPC85xx=y |
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CONFIG_TARGET_P5040DS=y |
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@ -0,0 +1,4 @@ |
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" |
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CONFIG_PPC=y |
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CONFIG_MPC85xx=y |
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CONFIG_TARGET_T102XQDS=y |
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@ -0,0 +1,4 @@ |
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB" |
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CONFIG_PPC=y |
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CONFIG_MPC85xx=y |
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CONFIG_TARGET_T104XRDB=y |
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@ -0,0 +1,48 @@ |
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This file contains information for VSC9953, a Vitesse L2 Switch IP |
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which is integrated in the T1040/T1020 Freescale SoCs. |
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|
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About Device: |
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============= |
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VSC9953 is an 8-port Gigabit Ethernet switch supports the following features: |
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- 8192 MAC addresses |
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- Static Address provisioning |
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- Dynamic learning of MAC addresses and aging |
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- 4096 VLANs |
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- Independent and shared VLAN learning (IVL, SVL) |
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- Policing with storm control and MC/BC protection |
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- IPv4 and IPv6 multicast |
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- Jumbo frames (9.6 KB) |
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- Access Control List |
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- VLAN editing, translation and remarking |
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- RMON counters per port |
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|
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Switch interfaces: |
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- 8 Gigabit switch ports (ports 0 to 7) are external and are connected to external PHYs |
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- 2 switch ports (ports 8 and 9) of 2.5 G are connected (fixed links) |
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to FMan ports (FM1@DTSEC1 and FM1@DTSEC2) |
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|
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Commands Overview: |
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============= |
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Commands supported |
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- enable/disable a port |
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- check a port's link speed, duplexity and status. |
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|
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Commands syntax |
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ethsw port <port_nr> enable|disable - enable/disable an l2 switch port |
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ethsw port <port_nr> show - show an l2 switch port's configuration |
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port_nr=0..9; use "all" for all ports |
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=> ethsw port all show |
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Port Status Link Speed Duplex |
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0 enabled down 10 half |
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1 enabled down 10 half |
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2 enabled down 10 half |
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3 enabled up 1000 full |
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4 disabled down - half |
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5 disabled down - half |
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6 disabled down - half |
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7 disabled down - half |
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8 enabled up 2500 full |
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9 enabled up 2500 full |
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=> |
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@ -0,0 +1,156 @@ |
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/*
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* Aquantia PHY drivers |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Copyright 2014 Freescale Semiconductor, Inc. |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <phy.h> |
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#ifndef CONFIG_PHYLIB_10G |
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#error The Aquantia PHY needs 10G support |
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#endif |
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#define AQUNTIA_10G_CTL 0x20 |
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#define AQUNTIA_VENDOR_P1 0xc400 |
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#define AQUNTIA_SPEED_LSB_MASK 0x2000 |
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#define AQUNTIA_SPEED_MSB_MASK 0x40 |
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int aquantia_config(struct phy_device *phydev) |
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{ |
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u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); |
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if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { |
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/* 1000BASE-T mode */ |
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phydev->advertising = SUPPORTED_1000baseT_Full; |
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phydev->supported = phydev->advertising; |
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val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK; |
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phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); |
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} else if (phydev->interface == PHY_INTERFACE_MODE_XGMII) { |
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/* 10GBASE-T mode */ |
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phydev->advertising = SUPPORTED_10000baseT_Full; |
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phydev->supported = phydev->advertising; |
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if (!(val & AQUNTIA_SPEED_LSB_MASK) || |
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!(val & AQUNTIA_SPEED_MSB_MASK)) |
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phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, |
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AQUNTIA_SPEED_LSB_MASK | |
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AQUNTIA_SPEED_MSB_MASK); |
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} else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) { |
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/* 2.5GBASE-T mode */ |
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phydev->advertising = SUPPORTED_1000baseT_Full; |
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phydev->supported = phydev->advertising; |
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phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1); |
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phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440); |
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} else if (phydev->interface == PHY_INTERFACE_MODE_MII) { |
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/* 100BASE-TX mode */ |
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phydev->advertising = SUPPORTED_100baseT_Full; |
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phydev->supported = phydev->advertising; |
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val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK; |
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phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); |
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} |
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return 0; |
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} |
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int aquantia_startup(struct phy_device *phydev) |
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{ |
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u32 reg, speed; |
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int i = 0; |
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phydev->duplex = DUPLEX_FULL; |
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/* if the AN is still in progress, wait till timeout. */ |
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phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); |
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reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); |
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if (!(reg & MDIO_AN_STAT1_COMPLETE)) { |
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printf("%s Waiting for PHY auto negotiation to complete", |
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phydev->dev->name); |
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do { |
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udelay(1000); |
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reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); |
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if ((i++ % 500) == 0) |
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printf("."); |
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} while (!(reg & MDIO_AN_STAT1_COMPLETE) && |
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i < (4 * PHY_ANEG_TIMEOUT)); |
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if (i > PHY_ANEG_TIMEOUT) |
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printf(" TIMEOUT !\n"); |
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} |
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/* Read twice because link state is latched and a
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* read moves the current state into the register */ |
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phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); |
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reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); |
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if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS)) |
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phydev->link = 0; |
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else |
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phydev->link = 1; |
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speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); |
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if (speed & AQUNTIA_SPEED_MSB_MASK) { |
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if (speed & AQUNTIA_SPEED_LSB_MASK) |
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phydev->speed = SPEED_10000; |
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else |
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phydev->speed = SPEED_1000; |
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} else { |
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if (speed & AQUNTIA_SPEED_LSB_MASK) |
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phydev->speed = SPEED_100; |
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else |
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phydev->speed = SPEED_10; |
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} |
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return 0; |
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} |
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struct phy_driver aq1202_driver = { |
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.name = "Aquantia AQ1202", |
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.uid = 0x3a1b445, |
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.mask = 0xfffffff0, |
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.features = PHY_10G_FEATURES, |
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.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| |
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MDIO_MMD_PHYXS | MDIO_MMD_AN | |
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MDIO_MMD_VEND1), |
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.config = &aquantia_config, |
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.startup = &aquantia_startup, |
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.shutdown = &gen10g_shutdown, |
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}; |
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struct phy_driver aq2104_driver = { |
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.name = "Aquantia AQ2104", |
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.uid = 0x3a1b460, |
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.mask = 0xfffffff0, |
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.features = PHY_10G_FEATURES, |
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.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| |
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MDIO_MMD_PHYXS | MDIO_MMD_AN | |
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MDIO_MMD_VEND1), |
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.config = &aquantia_config, |
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.startup = &aquantia_startup, |
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.shutdown = &gen10g_shutdown, |
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}; |
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struct phy_driver aqr105_driver = { |
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.name = "Aquantia AQR105", |
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.uid = 0x3a1b4a2, |
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.mask = 0xfffffff0, |
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.features = PHY_10G_FEATURES, |
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.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| |
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MDIO_MMD_PHYXS | MDIO_MMD_AN | |
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MDIO_MMD_VEND1), |
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.config = &aquantia_config, |
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.startup = &aquantia_startup, |
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.shutdown = &gen10g_shutdown, |
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}; |
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int phy_aquantia_init(void) |
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{ |
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phy_register(&aq1202_driver); |
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phy_register(&aq2104_driver); |
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phy_register(&aqr105_driver); |
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return 0; |
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} |
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@ -0,0 +1,497 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Driver for the Vitesse VSC9953 L2 Switch |
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*/ |
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#include <asm/io.h> |
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#include <asm/fsl_serdes.h> |
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#include <fm_eth.h> |
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#include <asm/fsl_memac.h> |
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#include <vsc9953.h> |
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static struct vsc9953_info vsc9953_l2sw = { |
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.port[0] = VSC9953_PORT_INFO_INITIALIZER(0), |
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.port[1] = VSC9953_PORT_INFO_INITIALIZER(1), |
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.port[2] = VSC9953_PORT_INFO_INITIALIZER(2), |
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.port[3] = VSC9953_PORT_INFO_INITIALIZER(3), |
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.port[4] = VSC9953_PORT_INFO_INITIALIZER(4), |
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.port[5] = VSC9953_PORT_INFO_INITIALIZER(5), |
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.port[6] = VSC9953_PORT_INFO_INITIALIZER(6), |
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.port[7] = VSC9953_PORT_INFO_INITIALIZER(7), |
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.port[8] = VSC9953_PORT_INFO_INITIALIZER(8), |
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.port[9] = VSC9953_PORT_INFO_INITIALIZER(9), |
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}; |
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void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus) |
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{ |
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if (!VSC9953_PORT_CHECK(port)) |
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return; |
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vsc9953_l2sw.port[port].bus = bus; |
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} |
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void vsc9953_port_info_set_phy_address(int port, int address) |
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{ |
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if (!VSC9953_PORT_CHECK(port)) |
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return; |
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vsc9953_l2sw.port[port].phyaddr = address; |
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} |
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void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int) |
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{ |
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if (!VSC9953_PORT_CHECK(port)) |
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return; |
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vsc9953_l2sw.port[port].enet_if = phy_int; |
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} |
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void vsc9953_port_enable(int port) |
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{ |
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if (!VSC9953_PORT_CHECK(port)) |
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return; |
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vsc9953_l2sw.port[port].enabled = 1; |
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} |
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void vsc9953_port_disable(int port) |
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{ |
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if (!VSC9953_PORT_CHECK(port)) |
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return; |
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vsc9953_l2sw.port[port].enabled = 0; |
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} |
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static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr, |
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int regnum, int value) |
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{ |
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int timeout = 50000; |
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out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) | |
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((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) | |
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(0x1 << 1)); |
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asm("sync"); |
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while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout) |
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udelay(1); |
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if (timeout == 0) |
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debug("Timeout waiting for MDIO write\n"); |
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} |
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static int vsc9953_mdio_read(struct vsc9953_mii_mng *phyregs, int port_addr, |
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int regnum) |
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{ |
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int value = 0xFFFF; |
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int timeout = 50000; |
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while ((in_le32(&phyregs->miimstatus) & MIIMIND_OPR_PEND) && --timeout) |
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udelay(1); |
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if (timeout == 0) { |
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debug("Timeout waiting for MDIO operation to finish\n"); |
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return value; |
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} |
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/* Put the address of the phy, and the register
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* number into MIICMD |
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*/ |
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out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) | |
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((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) | |
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(0x2 << 1)); |
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timeout = 50000; |
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/* Wait for the the indication that the read is done */ |
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while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout) |
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udelay(1); |
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if (timeout == 0) |
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debug("Timeout waiting for MDIO read\n"); |
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|
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/* Grab the value read from the PHY */ |
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value = in_le32(&phyregs->miimdata); |
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|
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if ((value & 0x00030000) == 0) |
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return value & 0x0000ffff; |
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return value; |
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} |
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|
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static int init_phy(struct eth_device *dev) |
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{ |
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struct vsc9953_port_info *l2sw_port = dev->priv; |
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struct phy_device *phydev = NULL; |
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|
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#ifdef CONFIG_PHYLIB |
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if (!l2sw_port->bus) |
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return 0; |
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phydev = phy_connect(l2sw_port->bus, l2sw_port->phyaddr, dev, |
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l2sw_port->enet_if); |
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if (!phydev) { |
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printf("Failed to connect\n"); |
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return -1; |
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} |
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|
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phydev->supported &= SUPPORTED_10baseT_Half | |
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SUPPORTED_10baseT_Full | |
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SUPPORTED_100baseT_Half | |
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SUPPORTED_100baseT_Full | |
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SUPPORTED_1000baseT_Full; |
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phydev->advertising = phydev->supported; |
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|
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l2sw_port->phydev = phydev; |
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|
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phy_config(phydev); |
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#endif |
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|
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return 0; |
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} |
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|
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static int vsc9953_port_init(int port) |
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{ |
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struct eth_device *dev; |
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|
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/* Internal ports never have a PHY */ |
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if (VSC9953_INTERNAL_PORT_CHECK(port)) |
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return 0; |
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|
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/* alloc eth device */ |
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dev = (struct eth_device *)calloc(1, sizeof(struct eth_device)); |
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if (!dev) |
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return 1; |
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|
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sprintf(dev->name, "SW@PORT%d", port); |
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dev->priv = &vsc9953_l2sw.port[port]; |
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dev->init = NULL; |
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dev->halt = NULL; |
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dev->send = NULL; |
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dev->recv = NULL; |
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|
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if (init_phy(dev)) { |
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free(dev); |
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return 1; |
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} |
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|
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return 0; |
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} |
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|
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void vsc9953_init(bd_t *bis) |
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{ |
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u32 i, hdx_cfg = 0, phy_addr = 0; |
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int timeout; |
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struct vsc9953_system_reg *l2sys_reg; |
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struct vsc9953_qsys_reg *l2qsys_reg; |
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struct vsc9953_dev_gmii *l2dev_gmii_reg; |
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struct vsc9953_analyzer *l2ana_reg; |
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struct vsc9953_devcpu_gcb *l2dev_gcb; |
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|
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l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(VSC9953_OFFSET + |
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VSC9953_DEV_GMII_OFFSET); |
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|
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l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + |
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VSC9953_ANA_OFFSET); |
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|
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l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET + |
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VSC9953_SYS_OFFSET); |
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|
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l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + |
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VSC9953_QSYS_OFFSET); |
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|
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l2dev_gcb = (struct vsc9953_devcpu_gcb *)(VSC9953_OFFSET + |
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VSC9953_DEVCPU_GCB); |
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|
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out_le32(&l2dev_gcb->chip_regs.soft_rst, |
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CONFIG_VSC9953_SOFT_SWC_RST_ENA); |
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timeout = 50000; |
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while ((in_le32(&l2dev_gcb->chip_regs.soft_rst) & |
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CONFIG_VSC9953_SOFT_SWC_RST_ENA) && --timeout) |
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udelay(1); /* busy wait for vsc9953 soft reset */ |
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if (timeout == 0) |
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debug("Timeout waiting for VSC9953 to reset\n"); |
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|
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out_le32(&l2sys_reg->sys.reset_cfg, CONFIG_VSC9953_MEM_ENABLE | |
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CONFIG_VSC9953_MEM_INIT); |
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|
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timeout = 50000; |
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while ((in_le32(&l2sys_reg->sys.reset_cfg) & |
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CONFIG_VSC9953_MEM_INIT) && --timeout) |
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udelay(1); /* busy wait for vsc9953 memory init */ |
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if (timeout == 0) |
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debug("Timeout waiting for VSC9953 memory to initialize\n"); |
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|
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out_le32(&l2sys_reg->sys.reset_cfg, (in_le32(&l2sys_reg->sys.reset_cfg) |
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| CONFIG_VSC9953_CORE_ENABLE)); |
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|
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/* VSC9953 Setting to be done once only */ |
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out_le32(&l2qsys_reg->sys.ext_cpu_cfg, 0x00000b00); |
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|
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for (i = 0; i < VSC9953_MAX_PORTS; i++) { |
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if (vsc9953_port_init(i)) |
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printf("Failed to initialize l2switch port %d\n", i); |
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|
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/* Enable VSC9953 GMII Ports Port ID 0 - 7 */ |
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if (VSC9953_INTERNAL_PORT_CHECK(i)) { |
||||
out_le32(&l2ana_reg->pfc[i].pfc_cfg, |
||||
CONFIG_VSC9953_PFC_FC_QSGMII); |
||||
out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i], |
||||
CONFIG_VSC9953_MAC_FC_CFG_QSGMII); |
||||
} else { |
||||
out_le32(&l2ana_reg->pfc[i].pfc_cfg, |
||||
CONFIG_VSC9953_PFC_FC); |
||||
out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i], |
||||
CONFIG_VSC9953_MAC_FC_CFG); |
||||
} |
||||
out_le32(&l2dev_gmii_reg->port_mode.clock_cfg, |
||||
CONFIG_VSC9953_CLOCK_CFG); |
||||
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ena_cfg, |
||||
CONFIG_VSC9953_MAC_ENA_CFG); |
||||
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_mode_cfg, |
||||
CONFIG_VSC9953_MAC_MODE_CFG); |
||||
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ifg_cfg, |
||||
CONFIG_VSC9953_MAC_IFG_CFG); |
||||
/* mac_hdx_cfg varies with port id*/ |
||||
hdx_cfg = (CONFIG_VSC9953_MAC_HDX_CFG | (i << 16)); |
||||
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_hdx_cfg, hdx_cfg); |
||||
out_le32(&l2sys_reg->sys.front_port_mode[i], |
||||
CONFIG_VSC9953_FRONT_PORT_MODE); |
||||
out_le32(&l2qsys_reg->sys.switch_port_mode[i], |
||||
CONFIG_VSC9953_PORT_ENA); |
||||
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_maxlen_cfg, |
||||
CONFIG_VSC9953_MAC_MAX_LEN); |
||||
out_le32(&l2sys_reg->pause_cfg.pause_cfg[i], |
||||
CONFIG_VSC9953_PAUSE_CFG); |
||||
/* WAIT FOR 2 us*/ |
||||
udelay(2); |
||||
|
||||
l2dev_gmii_reg = (struct vsc9953_dev_gmii *)( |
||||
(char *)l2dev_gmii_reg |
||||
+ T1040_SWITCH_GMII_DEV_OFFSET); |
||||
|
||||
/* Initialize Lynx PHY Wrappers */ |
||||
phy_addr = 0; |
||||
if (vsc9953_l2sw.port[i].enet_if == |
||||
PHY_INTERFACE_MODE_QSGMII) |
||||
phy_addr = (i + 0x4) & 0x1F; |
||||
else if (vsc9953_l2sw.port[i].enet_if == |
||||
PHY_INTERFACE_MODE_SGMII) |
||||
phy_addr = (i + 1) & 0x1F; |
||||
|
||||
if (phy_addr) { |
||||
/* SGMII IF mode + AN enable */ |
||||
vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, |
||||
0x14, PHY_SGMII_IF_MODE_AN | |
||||
PHY_SGMII_IF_MODE_SGMII); |
||||
/* Dev ability according to SGMII specification */ |
||||
vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, |
||||
0x4, PHY_SGMII_DEV_ABILITY_SGMII); |
||||
/* Adjust link timer for SGMII
|
||||
* 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 |
||||
*/ |
||||
vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, |
||||
0x13, 0x0003); |
||||
vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, |
||||
0x12, 0x0d40); |
||||
/* Restart AN */ |
||||
vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, |
||||
0x0, PHY_SGMII_CR_DEF_VAL | |
||||
PHY_SGMII_CR_RESET_AN); |
||||
|
||||
timeout = 50000; |
||||
while ((vsc9953_mdio_read(&l2dev_gcb->mii_mng[0], |
||||
phy_addr, 0x01) & 0x0020) && --timeout) |
||||
udelay(1); /* wait for AN to complete */ |
||||
if (timeout == 0) |
||||
debug("Timeout waiting for AN to complete\n"); |
||||
} |
||||
} |
||||
|
||||
printf("VSC9953 L2 switch initialized\n"); |
||||
return; |
||||
} |
||||
|
||||
#ifdef CONFIG_VSC9953_CMD |
||||
/* Enable/disable status of a VSC9953 port */ |
||||
static void vsc9953_port_status_set(int port_nr, u8 enabled) |
||||
{ |
||||
u32 val; |
||||
struct vsc9953_qsys_reg *l2qsys_reg; |
||||
|
||||
/* Administrative down */ |
||||
if (vsc9953_l2sw.port[port_nr].enabled == 0) |
||||
return; |
||||
|
||||
l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + |
||||
VSC9953_QSYS_OFFSET); |
||||
|
||||
val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_nr]); |
||||
if (enabled == 1) |
||||
val |= (1 << 13); |
||||
else |
||||
val &= ~(1 << 13); |
||||
|
||||
out_le32(&l2qsys_reg->sys.switch_port_mode[port_nr], val); |
||||
} |
||||
|
||||
/* Set all VSC9953 ports' status */ |
||||
static void vsc9953_port_all_status_set(u8 enabled) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < VSC9953_MAX_PORTS; i++) |
||||
vsc9953_port_status_set(i, enabled); |
||||
} |
||||
|
||||
/* Start autonegotiation for a VSC9953 PHY */ |
||||
static void vsc9953_phy_autoneg(int port_nr) |
||||
{ |
||||
if (!vsc9953_l2sw.port[port_nr].phydev) |
||||
return; |
||||
|
||||
if (vsc9953_l2sw.port[port_nr].phydev->drv->startup( |
||||
vsc9953_l2sw.port[port_nr].phydev)) |
||||
printf("Failed to start PHY for port %d\n", port_nr); |
||||
} |
||||
|
||||
/* Start autonegotiation for all VSC9953 PHYs */ |
||||
static void vsc9953_phy_all_autoneg(void) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < VSC9953_MAX_PORTS; i++) |
||||
vsc9953_phy_autoneg(i); |
||||
} |
||||
|
||||
/* Print a VSC9953 port's configuration */ |
||||
static void vsc9953_port_config_show(int port) |
||||
{ |
||||
int speed; |
||||
int duplex; |
||||
int link; |
||||
u8 enabled; |
||||
u32 val; |
||||
struct vsc9953_qsys_reg *l2qsys_reg; |
||||
|
||||
l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + |
||||
VSC9953_QSYS_OFFSET); |
||||
|
||||
val = in_le32(&l2qsys_reg->sys.switch_port_mode[port]); |
||||
enabled = vsc9953_l2sw.port[port].enabled & |
||||
((val & 0x00002000) >> 13); |
||||
|
||||
/* internal ports (8 and 9) are fixed */ |
||||
if (VSC9953_INTERNAL_PORT_CHECK(port)) { |
||||
link = 1; |
||||
speed = SPEED_2500; |
||||
duplex = DUPLEX_FULL; |
||||
} else { |
||||
if (vsc9953_l2sw.port[port].phydev) { |
||||
link = vsc9953_l2sw.port[port].phydev->link; |
||||
speed = vsc9953_l2sw.port[port].phydev->speed; |
||||
duplex = vsc9953_l2sw.port[port].phydev->duplex; |
||||
} else { |
||||
link = -1; |
||||
speed = -1; |
||||
duplex = -1; |
||||
} |
||||
} |
||||
|
||||
printf("%8d ", port); |
||||
printf("%8s ", enabled == 1 ? "enabled" : "disabled"); |
||||
printf("%8s ", link == 1 ? "up" : "down"); |
||||
|
||||
switch (speed) { |
||||
case SPEED_10: |
||||
printf("%8d ", 10); |
||||
break; |
||||
case SPEED_100: |
||||
printf("%8d ", 100); |
||||
break; |
||||
case SPEED_1000: |
||||
printf("%8d ", 1000); |
||||
break; |
||||
case SPEED_2500: |
||||
printf("%8d ", 2500); |
||||
break; |
||||
case SPEED_10000: |
||||
printf("%8d ", 10000); |
||||
break; |
||||
default: |
||||
printf("%8s ", "-"); |
||||
} |
||||
|
||||
printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half"); |
||||
} |
||||
|
||||
/* Print VSC9953 ports' configuration */ |
||||
static void vsc9953_port_all_config_show(void) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < VSC9953_MAX_PORTS; i++) |
||||
vsc9953_port_config_show(i); |
||||
} |
||||
|
||||
/* function to interpret commands starting with "ethsw " */ |
||||
static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
u8 enable; |
||||
u32 port; |
||||
|
||||
if (argc < 4) |
||||
return -1; |
||||
|
||||
if (strcmp(argv[1], "port")) |
||||
return -1; |
||||
|
||||
if (!strcmp(argv[3], "show")) { |
||||
if (!strcmp(argv[2], "all")) { |
||||
vsc9953_phy_all_autoneg(); |
||||
printf("%8s %8s %8s %8s %8s\n", |
||||
"Port", "Status", "Link", "Speed", |
||||
"Duplex"); |
||||
vsc9953_port_all_config_show(); |
||||
return 0; |
||||
} else { |
||||
port = simple_strtoul(argv[2], NULL, 10); |
||||
if (!VSC9953_PORT_CHECK(port)) |
||||
return -1; |
||||
vsc9953_phy_autoneg(port); |
||||
printf("%8s %8s %8s %8s %8s\n", |
||||
"Port", "Status", "Link", "Speed", |
||||
"Duplex"); |
||||
vsc9953_port_config_show(port); |
||||
return 0; |
||||
} |
||||
} else if (!strcmp(argv[3], "enable")) { |
||||
enable = 1; |
||||
} else if (!strcmp(argv[3], "disable")) { |
||||
enable = 0; |
||||
} else { |
||||
return -1; |
||||
} |
||||
|
||||
if (!strcmp(argv[2], "all")) { |
||||
vsc9953_port_all_status_set(enable); |
||||
return 0; |
||||
} else { |
||||
port = simple_strtoul(argv[2], NULL, 10); |
||||
if (!VSC9953_PORT_CHECK(port)) |
||||
return -1; |
||||
vsc9953_port_status_set(port, enable); |
||||
return 0; |
||||
} |
||||
|
||||
return -1; |
||||
} |
||||
|
||||
U_BOOT_CMD(ethsw, 5, 0, do_ethsw, |
||||
"vsc9953 l2 switch commands", |
||||
"port <port_nr> enable|disable\n" |
||||
" - enable/disable an l2 switch port\n" |
||||
" port_nr=0..9; use \"all\" for all ports\n" |
||||
"ethsw port <port_nr> show\n" |
||||
" - show an l2 switch port's configuration\n" |
||||
" port_nr=0..9; use \"all\" for all ports\n" |
||||
); |
||||
#endif /* CONFIG_VSC9953_CMD */ |
||||
@ -0,0 +1,402 @@ |
||||
/*
|
||||
* vsc9953.h |
||||
* |
||||
* Driver for the Vitesse VSC9953 L2 Switch |
||||
* |
||||
* This software may be used and distributed according to the |
||||
* terms of the GNU Public License, Version 2, incorporated |
||||
* herein by reference. |
||||
* |
||||
* Copyright 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _VSC9953_H_ |
||||
#define _VSC9953_H_ |
||||
|
||||
#include <config.h> |
||||
#include <miiphy.h> |
||||
#include <asm/types.h> |
||||
#include <malloc.h> |
||||
|
||||
#define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) |
||||
|
||||
#define VSC9953_SYS_OFFSET 0x010000 |
||||
#define VSC9953_DEV_GMII_OFFSET 0x100000 |
||||
#define VSC9953_QSYS_OFFSET 0x200000 |
||||
#define VSC9953_ANA_OFFSET 0x280000 |
||||
#define VSC9953_DEVCPU_GCB 0x070000 |
||||
#define VSC9953_ES0 0x040000 |
||||
#define VSC9953_IS1 0x050000 |
||||
#define VSC9953_IS2 0x060000 |
||||
|
||||
#define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 |
||||
#define VSC9953_PHY_REGS_OFFST 0x0000AC |
||||
|
||||
#define CONFIG_VSC9953_SOFT_SWC_RST_ENA 0x00000001 |
||||
#define CONFIG_VSC9953_CORE_ENABLE 0x80 |
||||
#define CONFIG_VSC9953_MEM_ENABLE 0x40 |
||||
#define CONFIG_VSC9953_MEM_INIT 0x20 |
||||
|
||||
#define CONFIG_VSC9953_PORT_ENA 0x00003a00 |
||||
#define CONFIG_VSC9953_MAC_ENA_CFG 0x00000011 |
||||
#define CONFIG_VSC9953_MAC_MODE_CFG 0x00000011 |
||||
#define CONFIG_VSC9953_MAC_IFG_CFG 0x00000515 |
||||
#define CONFIG_VSC9953_MAC_HDX_CFG 0x00001043 |
||||
#define CONFIG_VSC9953_CLOCK_CFG 0x00000001 |
||||
#define CONFIG_VSC9953_CLOCK_CFG_1000M 0x00000001 |
||||
#define CONFIG_VSC9953_PFC_FC 0x00000001 |
||||
#define CONFIG_VSC9953_PFC_FC_QSGMII 0x00000000 |
||||
#define CONFIG_VSC9953_MAC_FC_CFG 0x04700000 |
||||
#define CONFIG_VSC9953_MAC_FC_CFG_QSGMII 0x00700000 |
||||
#define CONFIG_VSC9953_PAUSE_CFG 0x001ffffe |
||||
#define CONFIG_VSC9953_TOT_TAIL_DROP_LVL 0x000003ff |
||||
#define CONFIG_VSC9953_FRONT_PORT_MODE 0x00000000 |
||||
#define CONFIG_VSC9953_MAC_MAX_LEN 0x000005ee |
||||
|
||||
#define CONFIG_VSC9953_VCAP_MV_CFG 0x0000ffff |
||||
#define CONFIG_VSC9953_VCAP_UPDATE_CTRL 0x01000004 |
||||
#define VSC9953_MAX_PORTS 10 |
||||
#define VSC9953_PORT_CHECK(port) \ |
||||
(((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) |
||||
#define VSC9953_INTERNAL_PORT_CHECK(port) ( \ |
||||
( \
|
||||
(port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
|
||||
) ? 0 : 1 \
|
||||
) |
||||
|
||||
#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" |
||||
|
||||
#define MIIMIND_OPR_PEND 0x00000004 |
||||
|
||||
struct vsc9953_mdio_info { |
||||
struct vsc9953_mii_mng *regs; |
||||
char *name; |
||||
}; |
||||
|
||||
/* VSC9953 ANA structure for T1040 U-boot*/ |
||||
|
||||
struct vsc9953_ana_port { |
||||
u32 vlan_cfg; |
||||
u32 drop_cfg; |
||||
u32 qos_cfg; |
||||
u32 vcap_cfg; |
||||
u32 vcap_s1_key_cfg[3]; |
||||
u32 vcap_s2_cfg; |
||||
u32 qos_pcp_dei_map_cfg[16]; |
||||
u32 cpu_fwd_cfg; |
||||
u32 cpu_fwd_bpdu_cfg; |
||||
u32 cpu_fwd_garp_cfg; |
||||
u32 cpu_fwd_ccm_cfg; |
||||
u32 port_cfg; |
||||
u32 pol_cfg; |
||||
u32 reserved[34]; |
||||
}; |
||||
|
||||
struct vsc9953_ana_pol { |
||||
u32 pol_pir_cfg; |
||||
u32 pol_cir_cfg; |
||||
u32 pol_mode_cfg; |
||||
u32 pol_pir_state; |
||||
u32 pol_cir_state; |
||||
u32 reserved1[3]; |
||||
}; |
||||
|
||||
struct vsc9953_ana_ana_tables { |
||||
u32 entry_lim[11]; |
||||
u32 an_moved; |
||||
u32 mach_data; |
||||
u32 macl_data; |
||||
u32 mac_access; |
||||
u32 mact_indx; |
||||
u32 vlan_access; |
||||
u32 vlan_tidx; |
||||
}; |
||||
|
||||
struct vsc9953_ana_ana { |
||||
u32 adv_learn; |
||||
u32 vlan_mask; |
||||
u32 anag_efil; |
||||
u32 an_events; |
||||
u32 storm_limit_burst; |
||||
u32 storm_limit_cfg[4]; |
||||
u32 isolated_prts; |
||||
u32 community_ports; |
||||
u32 auto_age; |
||||
u32 mac_options; |
||||
u32 learn_disc; |
||||
u32 agen_ctrl; |
||||
u32 mirror_ports; |
||||
u32 emirror_ports; |
||||
u32 flooding; |
||||
u32 flooding_ipmc; |
||||
u32 sflow_cfg[11]; |
||||
u32 port_mode[12]; |
||||
}; |
||||
|
||||
struct vsc9953_ana_pgid { |
||||
u32 port_grp_id[91]; |
||||
}; |
||||
|
||||
struct vsc9953_ana_pfc { |
||||
u32 pfc_cfg; |
||||
u32 reserved1[15]; |
||||
}; |
||||
|
||||
struct vsc9953_ana_pol_misc { |
||||
u32 pol_flowc[10]; |
||||
u32 reserved1[17]; |
||||
u32 pol_hyst; |
||||
}; |
||||
|
||||
struct vsc9953_ana_common { |
||||
u32 aggr_cfg; |
||||
u32 cpuq_cfg; |
||||
u32 cpuq_8021_cfg; |
||||
u32 dscp_cfg; |
||||
u32 dscp_rewr_cfg; |
||||
u32 vcap_rng_type_cfg; |
||||
u32 vcap_rng_val_cfg; |
||||
u32 discard_cfg; |
||||
u32 fid_cfg; |
||||
}; |
||||
|
||||
struct vsc9953_analyzer { |
||||
struct vsc9953_ana_port port[11]; |
||||
u32 reserved1[9536]; |
||||
struct vsc9953_ana_pol pol[164]; |
||||
struct vsc9953_ana_ana_tables ana_tables; |
||||
u32 reserved2[14]; |
||||
struct vsc9953_ana_ana ana; |
||||
u32 reserved3[22]; |
||||
struct vsc9953_ana_pgid port_id_tbl; |
||||
u32 reserved4[549]; |
||||
struct vsc9953_ana_pfc pfc[10]; |
||||
struct vsc9953_ana_pol_misc pol_misc; |
||||
u32 reserved5[196]; |
||||
struct vsc9953_ana_common common; |
||||
}; |
||||
/* END VSC9953 ANA structure for T1040 U-boot*/ |
||||
|
||||
/* VSC9953 DEV_GMII structure for T1040 U-boot*/ |
||||
|
||||
struct vsc9953_dev_gmii_port_mode { |
||||
u32 clock_cfg; |
||||
u32 port_misc; |
||||
u32 reserved1; |
||||
u32 eee_cfg; |
||||
}; |
||||
|
||||
struct vsc9953_dev_gmii_mac_cfg_status { |
||||
u32 mac_ena_cfg; |
||||
u32 mac_mode_cfg; |
||||
u32 mac_maxlen_cfg; |
||||
u32 mac_tags_cfg; |
||||
u32 mac_adv_chk_cfg; |
||||
u32 mac_ifg_cfg; |
||||
u32 mac_hdx_cfg; |
||||
u32 mac_fc_mac_low_cfg; |
||||
u32 mac_fc_mac_high_cfg; |
||||
u32 mac_sticky; |
||||
}; |
||||
|
||||
struct vsc9953_dev_gmii { |
||||
struct vsc9953_dev_gmii_port_mode port_mode; |
||||
struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; |
||||
}; |
||||
|
||||
/* END VSC9953 DEV_GMII structure for T1040 U-boot*/ |
||||
|
||||
/* VSC9953 QSYS structure for T1040 U-boot*/ |
||||
|
||||
struct vsc9953_qsys_hsch { |
||||
u32 cir_cfg; |
||||
u32 reserved1; |
||||
u32 se_cfg; |
||||
u32 se_dwrr_cfg[8]; |
||||
u32 cir_state; |
||||
u32 reserved2[20]; |
||||
}; |
||||
|
||||
struct vsc9953_qsys_sys { |
||||
u32 port_mode[12]; |
||||
u32 switch_port_mode[11]; |
||||
u32 stat_cnt_cfg; |
||||
u32 eee_cfg[10]; |
||||
u32 eee_thrs; |
||||
u32 igr_no_sharing; |
||||
u32 egr_no_sharing; |
||||
u32 sw_status[11]; |
||||
u32 ext_cpu_cfg; |
||||
u32 cpu_group_map; |
||||
u32 reserved1[23]; |
||||
}; |
||||
|
||||
struct vsc9953_qsys_qos_cfg { |
||||
u32 red_profile[16]; |
||||
u32 res_qos_mode; |
||||
}; |
||||
|
||||
struct vsc9953_qsys_drop_cfg { |
||||
u32 egr_drop_mode; |
||||
}; |
||||
|
||||
struct vsc9953_qsys_mmgt { |
||||
u32 eq_cntrl; |
||||
u32 reserved1; |
||||
}; |
||||
|
||||
struct vsc9953_qsys_hsch_misc { |
||||
u32 hsch_misc_cfg; |
||||
u32 reserved1[546]; |
||||
}; |
||||
|
||||
struct vsc9953_qsys_res_ctrl { |
||||
u32 res_cfg; |
||||
u32 res_stat; |
||||
|
||||
}; |
||||
|
||||
struct vsc9953_qsys_reg { |
||||
struct vsc9953_qsys_hsch hsch[108]; |
||||
struct vsc9953_qsys_sys sys; |
||||
struct vsc9953_qsys_qos_cfg qos_cfg; |
||||
struct vsc9953_qsys_drop_cfg drop_cfg; |
||||
struct vsc9953_qsys_mmgt mmgt; |
||||
struct vsc9953_qsys_hsch_misc hsch_misc; |
||||
struct vsc9953_qsys_res_ctrl res_ctrl[1024]; |
||||
}; |
||||
|
||||
/* END VSC9953 QSYS structure for T1040 U-boot*/ |
||||
|
||||
/* VSC9953 SYS structure for T1040 U-boot*/ |
||||
|
||||
struct vsc9953_sys_stat { |
||||
u32 rx_cntrs[64]; |
||||
u32 tx_cntrs[64]; |
||||
u32 drop_cntrs[64]; |
||||
u32 reserved1[6]; |
||||
}; |
||||
|
||||
struct vsc9953_sys_sys { |
||||
u32 reset_cfg; |
||||
u32 reserved1; |
||||
u32 vlan_etype_cfg; |
||||
u32 port_mode[12]; |
||||
u32 front_port_mode[10]; |
||||
u32 frame_aging; |
||||
u32 stat_cfg; |
||||
u32 reserved2[50]; |
||||
}; |
||||
|
||||
struct vsc9953_sys_pause_cfg { |
||||
u32 pause_cfg[11]; |
||||
u32 pause_tot_cfg; |
||||
u32 tail_drop_level[11]; |
||||
u32 tot_tail_drop_lvl; |
||||
u32 mac_fc_cfg[10]; |
||||
}; |
||||
|
||||
struct vsc9953_sys_mmgt { |
||||
u16 free_cnt; |
||||
}; |
||||
|
||||
struct vsc9953_system_reg { |
||||
struct vsc9953_sys_stat stat; |
||||
struct vsc9953_sys_sys sys; |
||||
struct vsc9953_sys_pause_cfg pause_cfg; |
||||
struct vsc9953_sys_mmgt mmgt; |
||||
}; |
||||
|
||||
/* END VSC9953 SYS structure for T1040 U-boot*/ |
||||
|
||||
|
||||
/* VSC9953 DEVCPU_GCB structure for T1040 U-boot*/ |
||||
|
||||
struct vsc9953_chip_regs { |
||||
u32 chipd_id; |
||||
u32 gpr; |
||||
u32 soft_rst; |
||||
}; |
||||
|
||||
struct vsc9953_gpio { |
||||
u32 gpio_out_set[10]; |
||||
u32 gpio_out_clr[10]; |
||||
u32 gpio_out[10]; |
||||
u32 gpio_in[10]; |
||||
}; |
||||
|
||||
struct vsc9953_mii_mng { |
||||
u32 miimstatus; |
||||
u32 reserved1; |
||||
u32 miimcmd; |
||||
u32 miimdata; |
||||
u32 miimcfg; |
||||
u32 miimscan_0; |
||||
u32 miimscan_1; |
||||
u32 miiscan_lst_rslts; |
||||
u32 miiscan_lst_rslts_valid; |
||||
}; |
||||
|
||||
struct vsc9953_mii_read_scan { |
||||
u32 mii_scan_results_sticky[2]; |
||||
}; |
||||
|
||||
struct vsc9953_devcpu_gcb { |
||||
struct vsc9953_chip_regs chip_regs; |
||||
struct vsc9953_gpio gpio; |
||||
struct vsc9953_mii_mng mii_mng[2]; |
||||
struct vsc9953_mii_read_scan mii_read_scan; |
||||
}; |
||||
|
||||
/* END VSC9953 DEVCPU_GCB structure for T1040 U-boot*/ |
||||
|
||||
/* VSC9953 IS* structure for T1040 U-boot*/ |
||||
|
||||
struct vsc9953_vcap_core_cfg { |
||||
u32 vcap_update_ctrl; |
||||
u32 vcap_mv_cfg; |
||||
}; |
||||
|
||||
struct vsc9953_vcap { |
||||
struct vsc9953_vcap_core_cfg vcap_core_cfg; |
||||
}; |
||||
|
||||
/* END VSC9953 IS* structure for T1040 U-boot*/ |
||||
|
||||
#define VSC9953_PORT_INFO_INITIALIZER(idx) \ |
||||
{ \
|
||||
.enabled = 0, \
|
||||
.phyaddr = 0, \
|
||||
.index = idx, \
|
||||
.phy_regs = NULL, \
|
||||
.enet_if = PHY_INTERFACE_MODE_NONE, \
|
||||
.bus = NULL, \
|
||||
.phydev = NULL, \
|
||||
} |
||||
|
||||
/* Structure to describe a VSC9953 port */ |
||||
struct vsc9953_port_info { |
||||
u8 enabled; |
||||
u8 phyaddr; |
||||
int index; |
||||
void *phy_regs; |
||||
phy_interface_t enet_if; |
||||
struct mii_dev *bus; |
||||
struct phy_device *phydev; |
||||
}; |
||||
|
||||
/* Structure to describe a VSC9953 switch */ |
||||
struct vsc9953_info { |
||||
struct vsc9953_port_info port[VSC9953_MAX_PORTS]; |
||||
}; |
||||
|
||||
void vsc9953_init(bd_t *bis); |
||||
|
||||
void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus); |
||||
void vsc9953_port_info_set_phy_address(int port, int address); |
||||
void vsc9953_port_enable(int port); |
||||
void vsc9953_port_disable(int port); |
||||
void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int); |
||||
|
||||
#endif /* _VSC9953_H_ */ |
||||
Loading…
Reference in new issue