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arm64: versal: Add support for new Xilinx Versal ACAPs

Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.

The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek 3 years ago
parent
commit
ec48b6c991

+ 1 - 1
Kconfig

@@ -144,7 +144,7 @@ config SYS_MALLOC_F_LEN
144 144
 
145 145
 config SYS_MALLOC_LEN
146 146
 	hex "Define memory for Dynamic allocation"
147
-	depends on ARCH_ZYNQ
147
+	depends on ARCH_ZYNQ || ARCH_VERSAL
148 148
 	help
149 149
 	  This defines memory to be allocated for Dynamic allocation
150 150
 	  TODO: Use for other architectures

+ 6 - 0
MAINTAINERS

@@ -287,6 +287,12 @@ F:	arch/arm/mach-uniphier/
287 287
 F:	configs/uniphier_*_defconfig
288 288
 N:	uniphier
289 289
 
290
+ARM VERSAL
291
+M:	Michal Simek <michal.simek@xilinx.com>
292
+S:	Maintained
293
+T:	git git://git.denx.de/u-boot-microblaze.git
294
+F:	arch/arm/mach-versal/
295
+
290 296
 ARM VERSATILE EXPRESS DRIVERS
291 297
 M:	Liviu Dudau <liviu.dudau@foss.arm.com>
292 298
 S:	Maintained

+ 10 - 0
arch/arm/Kconfig

@@ -853,6 +853,14 @@ config ARCH_SUNXI
853 853
 	imply SPL_SERIAL_SUPPORT
854 854
 	imply USB_GADGET
855 855
 
856
+config ARCH_VERSAL
857
+	bool "Support Xilinx Versal Platform"
858
+	select ARM64
859
+	select CLK
860
+	select DM
861
+	select DM_SERIAL
862
+	select OF_CONTROL
863
+
856 864
 config ARCH_VF610
857 865
 	bool "Freescale Vybrid"
858 866
 	select CPU_V7A
@@ -1449,6 +1457,8 @@ source "arch/arm/cpu/armv7/vf610/Kconfig"
1449 1457
 
1450 1458
 source "arch/arm/mach-zynq/Kconfig"
1451 1459
 
1460
+source "arch/arm/mach-versal/Kconfig"
1461
+
1452 1462
 source "arch/arm/mach-zynqmp-r5/Kconfig"
1453 1463
 
1454 1464
 source "arch/arm/cpu/armv7/Kconfig"

+ 1 - 0
arch/arm/Makefile

@@ -80,6 +80,7 @@ machine-$(CONFIG_ARCH_STM32MP)		+= stm32mp
80 80
 machine-$(CONFIG_TEGRA)			+= tegra
81 81
 machine-$(CONFIG_ARCH_UNIPHIER)		+= uniphier
82 82
 machine-$(CONFIG_ARCH_ZYNQ)		+= zynq
83
+machine-$(CONFIG_ARCH_VERSAL)		+= versal
83 84
 machine-$(CONFIG_ARCH_ZYNQMP_R5)	+= zynqmp-r5
84 85
 
85 86
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))

+ 39 - 0
arch/arm/mach-versal/Kconfig

@@ -0,0 +1,39 @@
1
+# SPDX-License-Identifier: GPL-2.0+
2
+
3
+if ARCH_VERSAL
4
+
5
+config SYS_BOARD
6
+	string "Board name"
7
+	default "versal"
8
+
9
+config SYS_VENDOR
10
+	string "Vendor name"
11
+	default "xilinx"
12
+
13
+config SYS_SOC
14
+	default "versal"
15
+
16
+config SYS_CONFIG_NAME
17
+	string "Board configuration name"
18
+	default "xilinx_versal"
19
+	help
20
+	  This option contains information about board configuration name.
21
+	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
22
+	  will be used for board configuration.
23
+
24
+config GICV3
25
+	def_bool y
26
+
27
+config SYS_MALLOC_LEN
28
+	default 0x2000000
29
+
30
+config COUNTER_FREQUENCY
31
+	int "Timer clock frequency"
32
+	default 0
33
+	help
34
+	  Setup time clock frequency for certain platform
35
+
36
+config ZYNQ_SDHCI_MAX_FREQ
37
+	default 200000000
38
+
39
+endif

+ 8 - 0
arch/arm/mach-versal/Makefile

@@ -0,0 +1,8 @@
1
+# SPDX-License-Identifier: GPL-2.0+
2
+#
3
+# (C) Copyright 2016 - 2018 Xilinx, Inc.
4
+# Michal Simek <michal.simek@xilinx.com>
5
+#
6
+
7
+obj-y	+= clk.o
8
+obj-y	+= cpu.o

+ 30 - 0
arch/arm/mach-versal/clk.c

@@ -0,0 +1,30 @@
1
+// SPDX-License-Identifier: GPL-2.0+
2
+/*
3
+ * (C) Copyright 2016 - 2018 Xilinx, Inc.
4
+ * Michal Simek <michal.simek@xilinx.com>
5
+ */
6
+
7
+#include <common.h>
8
+
9
+DECLARE_GLOBAL_DATA_PTR;
10
+
11
+#ifdef CONFIG_CLOCKS
12
+/**
13
+ * set_cpu_clk_info - Initialize clock framework
14
+ *
15
+ * Return: 0 always.
16
+ *
17
+ * This function is called from common code after relocation and sets up the
18
+ * clock framework. The framework must not be used before this function had been
19
+ * called.
20
+ */
21
+int set_cpu_clk_info(void)
22
+{
23
+	gd->cpu_clk = get_tbclk();
24
+
25
+	gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
26
+	gd->bd->bi_dsp_freq = 0;
27
+
28
+	return 0;
29
+}
30
+#endif

+ 69 - 0
arch/arm/mach-versal/cpu.c

@@ -0,0 +1,69 @@
1
+// SPDX-License-Identifier: GPL-2.0+
2
+/*
3
+ * (C) Copyright 2016 - 2018 Xilinx, Inc.
4
+ * Michal Simek <michal.simek@xilinx.com>
5
+ */
6
+
7
+#include <common.h>
8
+#include <asm/armv8/mmu.h>
9
+#include <asm/io.h>
10
+
11
+static struct mm_region versal_mem_map[] = {
12
+	{
13
+		.virt = 0x0UL,
14
+		.phys = 0x0UL,
15
+		.size = 0x80000000UL,
16
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
17
+			 PTE_BLOCK_INNER_SHARE
18
+	}, {
19
+		.virt = 0x80000000UL,
20
+		.phys = 0x80000000UL,
21
+		.size = 0x70000000UL,
22
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
23
+			 PTE_BLOCK_NON_SHARE |
24
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
25
+	}, {
26
+		.virt = 0xf0000000UL,
27
+		.phys = 0xf0000000UL,
28
+		.size = 0x0fe00000UL,
29
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
30
+			 PTE_BLOCK_NON_SHARE |
31
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
32
+	}, {
33
+		.virt = 0xffe00000UL,
34
+		.phys = 0xffe00000UL,
35
+		.size = 0x00200000UL,
36
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
37
+			 PTE_BLOCK_INNER_SHARE
38
+	}, {
39
+		.virt = 0x400000000UL,
40
+		.phys = 0x400000000UL,
41
+		.size = 0x200000000UL,
42
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
43
+			 PTE_BLOCK_NON_SHARE |
44
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
45
+	}, {
46
+		.virt = 0x600000000UL,
47
+		.phys = 0x600000000UL,
48
+		.size = 0x800000000UL,
49
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
50
+			 PTE_BLOCK_INNER_SHARE
51
+	}, {
52
+		.virt = 0xe00000000UL,
53
+		.phys = 0xe00000000UL,
54
+		.size = 0xf200000000UL,
55
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
56
+			 PTE_BLOCK_NON_SHARE |
57
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
58
+	}, {
59
+		/* List terminator */
60
+		0,
61
+	}
62
+};
63
+
64
+struct mm_region *mem_map = versal_mem_map;
65
+
66
+u64 get_page_table_size(void)
67
+{
68
+	return 0x14000;
69
+}

+ 6 - 0
arch/arm/mach-versal/include/mach/gpio.h

@@ -0,0 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
2
+/*
3
+ * Copyright 2016 - 2018 Xilinx, Inc.
4
+ */
5
+
6
+/* Empty file - for compilation */

+ 34 - 0
arch/arm/mach-versal/include/mach/hardware.h

@@ -0,0 +1,34 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
2
+/*
3
+ * Copyright 2016 - 2018 Xilinx, Inc.
4
+ */
5
+
6
+#define VERSAL_CRL_APB_BASEADDR	0xFF5E0000
7
+
8
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT	BIT(25)
9
+
10
+#define IOU_SWITCH_CTRL_CLKACT_BIT	BIT(25)
11
+#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT	8
12
+
13
+struct crlapb_regs {
14
+	u32 reserved0[69];
15
+	u32 iou_switch_ctrl; /* 0x114 */
16
+	u32 reserved1[13];
17
+	u32 timestamp_ref_ctrl; /* 0x14c */
18
+	u32 reserved2[126];
19
+	u32 rst_timestamp; /* 0x348 */
20
+};
21
+
22
+#define crlapb_base ((struct crlapb_regs *)VERSAL_CRL_APB_BASEADDR)
23
+
24
+#define VERSAL_IOU_SCNTR_SECURE	0xFF140000
25
+
26
+#define IOU_SCNTRS_CONTROL_EN	1
27
+
28
+struct iou_scntrs_regs {
29
+	u32 counter_control_register; /* 0x0 */
30
+	u32 reserved0[7];
31
+	u32 base_frequency_id_register; /* 0x20 */
32
+};
33
+
34
+#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_IOU_SCNTR_SECURE)

+ 6 - 0
arch/arm/mach-versal/include/mach/sys_proto.h

@@ -0,0 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
2
+/*
3
+ * Copyright 2016 - 2018 Xilinx, Inc.
4
+ */
5
+
6
+/* Empty file - for compilation */

+ 7 - 0
board/xilinx/versal/MAINTAINERS

@@ -0,0 +1,7 @@
1
+XILINX_VERSAL BOARDS
2
+M:	Michal Simek <michal.simek@xilinx.com>
3
+S:	Maintained
4
+F:	arch/arm/dts/versal*
5
+F:	board/xilinx/versal/
6
+F:	include/configs/xilinx_versal*
7
+F:	configs/xilinx_versal*

+ 7 - 0
board/xilinx/versal/Makefile

@@ -0,0 +1,7 @@
1
+# SPDX-License-Identifier: GPL-2.0+
2
+#
3
+# (C) Copyright 2016 - 2018 Xilinx, Inc.
4
+# Michal Simek <michal.simek@xilinx.com>
5
+#
6
+
7
+obj-y	:= board.o

+ 81 - 0
board/xilinx/versal/board.c

@@ -0,0 +1,81 @@
1
+// SPDX-License-Identifier: GPL-2.0+
2
+/*
3
+ * (C) Copyright 2014 - 2018 Xilinx, Inc.
4
+ * Michal Simek <michal.simek@xilinx.com>
5
+ */
6
+
7
+#include <common.h>
8
+#include <fdtdec.h>
9
+#include <malloc.h>
10
+#include <asm/io.h>
11
+#include <asm/arch/hardware.h>
12
+
13
+DECLARE_GLOBAL_DATA_PTR;
14
+
15
+int board_init(void)
16
+{
17
+	printf("EL Level:\tEL%d\n", current_el());
18
+
19
+	return 0;
20
+}
21
+
22
+int board_early_init_r(void)
23
+{
24
+	if (current_el() == 3) {
25
+		u32 val;
26
+
27
+		writel(IOU_SWITCH_CTRL_CLKACT_BIT |
28
+		       (0x20 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
29
+		       &crlapb_base->iou_switch_ctrl);
30
+
31
+		/* Global timer init - Program time stamp reference clk */
32
+		val = readl(&crlapb_base->timestamp_ref_ctrl);
33
+		val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
34
+		writel(val, &crlapb_base->timestamp_ref_ctrl);
35
+
36
+		debug("ref ctrl 0x%x\n",
37
+		      readl(&crlapb_base->timestamp_ref_ctrl));
38
+
39
+		/* Clear reset of timestamp reg */
40
+		writel(0, &crlapb_base->rst_timestamp);
41
+
42
+		/*
43
+		 * Program freq register in System counter and
44
+		 * enable system counter.
45
+		 */
46
+		writel(COUNTER_FREQUENCY,
47
+		       &iou_scntr_secure->base_frequency_id_register);
48
+
49
+		debug("counter val 0x%x\n",
50
+		      readl(&iou_scntr_secure->base_frequency_id_register));
51
+
52
+		writel(IOU_SCNTRS_CONTROL_EN,
53
+		       &iou_scntr_secure->counter_control_register);
54
+
55
+		debug("scntrs control 0x%x\n",
56
+		      readl(&iou_scntr_secure->counter_control_register));
57
+		debug("timer 0x%llx\n", get_ticks());
58
+		debug("timer 0x%llx\n", get_ticks());
59
+	}
60
+
61
+	return 0;
62
+}
63
+
64
+int dram_init_banksize(void)
65
+{
66
+	fdtdec_setup_memory_banksize();
67
+
68
+	return 0;
69
+}
70
+
71
+int dram_init(void)
72
+{
73
+	if (fdtdec_setup_mem_size_base() != 0)
74
+		return -EINVAL;
75
+
76
+	return 0;
77
+}
78
+
79
+void reset_cpu(ulong addr)
80
+{
81
+}

+ 1 - 1
drivers/mmc/Kconfig

@@ -538,7 +538,7 @@ config MMC_SDHCI_TEGRA
538 538
 
539 539
 config MMC_SDHCI_ZYNQ
540 540
 	bool "Arasan SDHCI controller support"
541
-	depends on ARCH_ZYNQ || ARCH_ZYNQMP
541
+	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
542 542
 	depends on DM_MMC && OF_CONTROL && BLK
543 543
 	depends on MMC_SDHCI
544 544
 	help

+ 1 - 1
drivers/net/Kconfig

@@ -344,7 +344,7 @@ config XILINX_EMACLITE
344 344
 	  This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
345 345
 
346 346
 config ZYNQ_GEM
347
-	depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP)
347
+	depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL)
348 348
 	select PHYLIB
349 349
 	bool "Xilinx Ethernet GEM"
350 350
 	help

+ 2 - 2
drivers/spi/Kconfig

@@ -243,7 +243,7 @@ config XILINX_SPI
243 243
 
244 244
 config ZYNQ_SPI
245 245
 	bool "Zynq SPI driver"
246
-	depends on ARCH_ZYNQ || ARCH_ZYNQMP
246
+	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
247 247
 	help
248 248
 	  Enable the Zynq SPI driver. This driver can be used to
249 249
 	  access the SPI NOR flash on platforms embedding this Zynq
@@ -260,7 +260,7 @@ config ZYNQ_QSPI
260 260
 
261 261
 config ZYNQMP_GQSPI
262 262
 	bool "Configure ZynqMP Generic QSPI"
263
-	depends on ARCH_ZYNQMP
263
+	depends on ARCH_ZYNQMP || ARCH_VERSAL
264 264
 	help
265 265
 	  This option is used to enable ZynqMP QSPI controller driver which
266 266
 	  is used to communicate with qspi flash devices.

+ 2 - 2
env/Kconfig

@@ -431,7 +431,7 @@ config ENV_EXT4_FILE
431 431
 	  It's a string of the EXT4 file name. This file use to store the
432 432
 	  environment (explicit path to the file)
433 433
 
434
-if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP
434
+if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
435 435
 
436 436
 config ENV_OFFSET
437 437
 	hex "Environment Offset"
@@ -448,7 +448,7 @@ config ENV_SIZE
448 448
 	hex "Environment Size"
449 449
 	default 0x40000 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP
450 450
 	default 0x20000 if ARCH_SUNXI || ARCH_ZYNQ
451
-	default 0x8000 if ARCH_ROCKCHIP || ARCH_ZYNQMP
451
+	default 0x8000 if ARCH_ROCKCHIP || ARCH_ZYNQMP || ARCH_VERSAL
452 452
 	help
453 453
 	  Size of the environment storage area
454 454
 

+ 91 - 0
include/configs/xilinx_versal.h

@@ -0,0 +1,91 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
2
+/*
3
+ * Configuration for Xilinx Versal
4
+ * (C) Copyright 2016 - 2018 Xilinx, Inc.
5
+ * Michal Simek <michal.simek@xilinx.com>
6
+ *
7
+ * Based on Configuration for Xilinx ZynqMP
8
+ */
9
+
10
+#ifndef __XILINX_VERSAL_H
11
+#define __XILINX_VERSAL_H
12
+
13
+#define CONFIG_REMAKE_ELF
14
+
15
+/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
16
+
17
+/* Generic Interrupt Controller Definitions */
18
+#define GICD_BASE	0xF9000000
19
+#define GICR_BASE	0xF9080000
20
+
21
+#define CONFIG_SYS_MEMTEST_SCRATCH	0xfffc0000
22
+
23
+#define CONFIG_SYS_MEMTEST_START	0
24
+#define CONFIG_SYS_MEMTEST_END		1000
25
+
26
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
27
+
28
+/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
29
+#if CONFIG_COUNTER_FREQUENCY
30
+# define COUNTER_FREQUENCY	CONFIG_COUNTER_FREQUENCY
31
+#endif
32
+
33
+/* Serial setup */
34
+#define CONFIG_ARM_DCC
35
+#define CONFIG_CPU_ARMV8
36
+
37
+#define CONFIG_SYS_BAUDRATE_TABLE \
38
+	{ 4800, 9600, 19200, 38400, 57600, 115200 }
39
+
40
+/* BOOTP options */
41
+#define CONFIG_BOOTP_BOOTFILESIZE
42
+#define CONFIG_BOOTP_MAY_FAIL
43
+
44
+#define CONFIG_IP_DEFRAG
45
+#define CONFIG_TFTP_BLOCKSIZE	4096
46
+
47
+/* Miscellaneous configurable options */
48
+#define CONFIG_SYS_LOAD_ADDR		0x8000000
49
+
50
+/* Monitor Command Prompt */
51
+/* Console I/O Buffer Size */
52
+#define CONFIG_SYS_CBSIZE		2048
53
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
54
+					sizeof(CONFIG_SYS_PROMPT) + 16)
55
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
56
+#define CONFIG_SYS_MAXARGS		64
57
+
58
+/* Ethernet driver */
59
+#if defined(CONFIG_ZYNQ_GEM)
60
+# define CONFIG_NET_MULTI
61
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
62
+# define PHY_ANEG_TIMEOUT       20000
63
+#endif
64
+
65
+#define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
66
+
67
+#define CONFIG_CLOCKS
68
+
69
+#define ENV_MEM_LAYOUT_SETTINGS \
70
+	"fdt_high=10000000\0" \
71
+	"initrd_high=10000000\0" \
72
+	"fdt_addr_r=0x40000000\0" \
73
+	"pxefile_addr_r=0x10000000\0" \
74
+	"kernel_addr_r=0x18000000\0" \
75
+	"scriptaddr=0x02000000\0" \
76
+	"ramdisk_addr_r=0x02100000\0"
77
+
78
+#define BOOT_TARGET_DEVICES(func) \
79
+	func(PXE, pxe, na) \
80
+	func(DHCP, dhcp, na)
81
+
82
+#include <config_distro_bootcmd.h>
83
+
84
+/* Initial environment variables */
85
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
86
+#define CONFIG_EXTRA_ENV_SETTINGS \
87
+	ENV_MEM_LAYOUT_SETTINGS \
88
+	BOOTENV
89
+#endif
90
+
91
+#endif /* __XILINX_VERSAL_H */