T series boards use unified RCW for sd, spi and nand boot. Now split txxx_rcw.cfg to txxx_sd_rcw.cfg, txxx_spi_rcw.cfg and txxx_nand_rcw.cfg for SPI/NAND/SD boot. And modify RCW[PBI_SRC] for them: PBI_SRC=5 for SPI 24-bit addressing PBI_SRC=6 for SD boot PBI_SRC=14 for IFC NAND boot Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>master
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44afdc4a12
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ec90ac7359
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# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz |
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# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz |
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|
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# PBL preamble and RCW header for T1024QDS |
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aa55aa55 010e0100 |
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# Serdes protocol 0x6F |
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0810000e 00000000 00000000 00000000 |
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37800001 00000012 68104000 21000000 |
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00000000 00000000 00000000 00030810 |
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00000000 036c5a00 00000000 00000006 |
@ -0,0 +1,10 @@ |
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# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz |
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# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz |
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|
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# PBL preamble and RCW header for T1024QDS |
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aa55aa55 010e0100 |
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# Serdes protocol 0x6F |
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0810000e 00000000 00000000 00000000 |
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37800001 00000012 58104000 21000000 |
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00000000 00000000 00000000 00030810 |
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00000000 036c5a00 00000000 00000006 |
@ -0,0 +1,8 @@ |
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#PBL preamble and RCW header for T1023RDB |
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aa55aa55 010e0100 |
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#SerDes Protocol: 0x77 |
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#Default Core=1200MHz, DDR=1600MT/s with single source clock |
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0810000c 00000000 00000000 00000000 |
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3b800003 00000012 68104000 21000000 |
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00000000 00000000 00000000 00022800 |
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00000130 04020200 00000000 00000006 |
@ -0,0 +1,8 @@ |
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#PBL preamble and RCW header for T1023RDB |
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aa55aa55 010e0100 |
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#SerDes Protocol: 0x77 |
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#Default Core=1200MHz, DDR=1600MT/s with single source clock |
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0810000c 00000000 00000000 00000000 |
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3b800003 00000012 58104000 21000000 |
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00000000 00000000 00000000 00022800 |
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00000130 04020200 00000000 00000006 |
@ -0,0 +1,8 @@ |
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#PBL preamble and RCW header for T1024RDB |
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aa55aa55 010e0100 |
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#SerDes Protocol: 0x95 |
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#Core/DDR: 1400Mhz/1600MT/s with single source clock |
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0810000c 00000000 00000000 00000000 |
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4a800003 80000012 6c027000 21000000 |
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00000000 00000000 00000000 00030810 |
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00000000 0b005a08 00000000 00000006 |
@ -0,0 +1,8 @@ |
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#PBL preamble and RCW header for T1024RDB |
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aa55aa55 010e0100 |
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#SerDes Protocol: 0x95 |
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#Core/DDR: 1400Mhz/1600MT/s with single source clock |
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0810000c 00000000 00000000 00000000 |
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4a800003 80000012 5c027000 21000000 |
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00000000 00000000 00000000 00030810 |
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00000000 0b005a08 00000000 00000006 |
@ -0,0 +1,7 @@ |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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# serdes protocol 0x66 |
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0c18000e 0e000000 00000000 00000000 |
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66000002 80000002 68106000 01000000 |
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00000000 00000000 00000000 00032810 |
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00000000 0342500f 00000000 00000000 |
@ -0,0 +1,7 @@ |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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# serdes protocol 0x66 |
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0c18000e 0e000000 00000000 00000000 |
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66000002 80000002 58106000 01000000 |
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00000000 00000000 00000000 00032810 |
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00000000 0342500f 00000000 00000000 |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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# serdes protocol 0x66 |
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0c18000e 0e000000 00000000 00000000 |
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66000002 40000002 6c027000 01000000 |
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00000000 00000000 00000000 00030810 |
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00000000 0342580f 00000000 00000000 |
@ -0,0 +1,7 @@ |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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# serdes protocol 0x66 |
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0c18000e 0e000000 00000000 00000000 |
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66000002 40000002 5c027000 01000000 |
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00000000 00000000 00000000 00030810 |
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00000000 0342580f 00000000 00000000 |
@ -0,0 +1,7 @@ |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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# serdes protocol 0x06 |
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0c18000e 0e000000 00000000 00000000 |
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06000002 00400002 68106000 01000000 |
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00000000 00000000 00000000 00030810 |
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00000000 01fe0a06 00000000 00000000 |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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# serdes protocol 0x06 |
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0c18000e 0e000000 00000000 00000000 |
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06000002 00400002 58106000 01000000 |
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00000000 00000000 00000000 00030810 |
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00000000 01fe0a06 00000000 00000000 |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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# serdes protocol 0x86 |
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0c18000e 0e000000 00000000 00000000 |
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86000002 80000002 6c027000 01000000 |
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00000000 00000000 00000000 00032810 |
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00000000 0342500f 00000000 00000000 |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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# serdes protocol 0x86 |
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0c18000e 0e000000 00000000 00000000 |
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86000002 80000002 5c027000 01000000 |
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00000000 00000000 00000000 00032810 |
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00000000 0342500f 00000000 00000000 |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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# serdes protocol 0x86 |
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0c18000e 0e000000 00000000 00000000 |
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86000002 40000002 6c027000 01000000 |
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00000000 00000000 00000000 00030810 |
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00000000 0342500f 00000000 00000000 |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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# serdes protocol 0x86 |
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0c18000e 0e000000 00000000 00000000 |
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86000002 40000002 5c027000 01000000 |
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00000000 00000000 00000000 00030810 |
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00000000 0342500f 00000000 00000000 |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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|
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#For T2080 v1.0 |
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#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s |
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#12100017 15000000 00000000 00000000 |
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#66150002 00008400 e8104000 c1000000 |
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#00000000 00000000 00000000 000307fc |
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#00000000 00000000 00000000 00000004 |
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#For T2080 v1.1 |
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#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s |
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0c070012 0e000000 00000000 00000000 |
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66150002 00000000 68104000 c1000000 |
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00000000 00000000 00000000 000307fc |
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00000000 00000000 00000000 00000004 |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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#For T2080 v1.0 |
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#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s |
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#12100017 15000000 00000000 00000000 |
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#66150002 00008400 e8104000 c1000000 |
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#00000000 00000000 00000000 000307fc |
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#00000000 00000000 00000000 00000004 |
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#For T2080 v1.1 |
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#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s |
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0c070012 0e000000 00000000 00000000 |
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66150002 00000000 58104000 c1000000 |
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00000000 00000000 00000000 000307fc |
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00000000 00000000 00000000 00000004 |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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#Default SerDes Protocol: 0x6C |
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#Core/DDR: 1533Mhz/2133MT/s |
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12100017 15000000 00000000 00000000 |
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6c000002 00008000 68104000 c1000000 |
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00000000 00000000 00000000 000307fc |
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00000000 00000000 00000000 00000004 |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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#Default SerDes Protocol: 0x6C |
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#Core/DDR: 1533Mhz/2133MT/s |
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12100017 15000000 00000000 00000000 |
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6c000002 00008000 58104000 c1000000 |
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00000000 00000000 00000000 000307fc |
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00000000 00000000 00000000 00000004 |
@ -0,0 +1,19 @@ |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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#For T2080 v1.0 |
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#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s |
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#120c0017 15000000 00000000 00000000 |
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#66150002 00008400 ec104000 c1000000 |
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#00000000 00000000 00000000 000307fc |
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#00000000 00000000 00000000 00000004 |
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#For T2080 v1.1 |
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#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s |
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#1206001b 15000000 00000000 00000000 |
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#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s |
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1207001b 15000000 00000000 00000000 |
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66150002 00000000 68104000 c1000000 |
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00800000 00000000 00000000 000307fc |
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00000000 00000000 00000000 00000004 |
@ -0,0 +1,19 @@ |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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#For T2080 v1.0 |
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#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s |
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#120c0017 15000000 00000000 00000000 |
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#66150002 00008400 ec104000 c1000000 |
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#00000000 00000000 00000000 000307fc |
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#00000000 00000000 00000000 00000004 |
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#For T2080 v1.1 |
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#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s |
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#1206001b 15000000 00000000 00000000 |
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#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s |
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1207001b 15000000 00000000 00000000 |
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66150002 00000000 58104000 c1000000 |
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00800000 00000000 00000000 000307fc |
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00000000 00000000 00000000 00000004 |
@ -0,0 +1,7 @@ |
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#PBL preamble and RCW header |
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aa55aa55 010e0100 |
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#serdes protocol 1_27_5_11 |
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1607001b 18101b16 00000000 00000000 |
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04362858 30548c00 68020000 f5000000 |
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00000000 ee0000ee 00000000 000307fc |
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00000000 00000000 00000000 00000028 |
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