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powerpc: remove orphaned boards mcc200 and prs200

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mcc200 and prs200 are old and have no maintainer. Remove the boards.

This also removes the mcc200 specific 1bpp BMP support from
common/lcd.c

Cc: Wolfgang Denk <wd@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
master
Nikita Kiryanov 10 years ago committed by Tom Rini
parent c88eaea0a0
commit ecfdcee5d9
27 changed files with 7 additions and 1600 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 4
      arch/powerpc/cpu/mpc5xxx/Kconfig
  2. 9
      board/mcc200/Kconfig
  3. 17
      board/mcc200/MAINTAINERS
  4. 8
      board/mcc200/Makefile
  5. 521
      board/mcc200/auto_update.c
  6. 200
      board/mcc200/lcd.c
  7. 314
      board/mcc200/mcc200.c
  8. 16
      board/mcc200/mt46v16m16-75.h
  9. 14
      board/mcc200/mt48lc16m16a2-75.h
  10. 14
      board/mcc200/mt48lc16m32s2-75.h
  11. 12
      board/mcc200/mt48lc8m32b2-6-7.h
  12. 24
      common/lcd.c
  13. 4
      configs/mcc200_COM12_SDRAM_defconfig
  14. 4
      configs/mcc200_COM12_defconfig
  15. 4
      configs/mcc200_COM12_highboot_SDRAM_defconfig
  16. 4
      configs/mcc200_COM12_highboot_defconfig
  17. 4
      configs/mcc200_SDRAM_defconfig
  18. 3
      configs/mcc200_defconfig
  19. 4
      configs/mcc200_highboot_SDRAM_defconfig
  20. 4
      configs/mcc200_highboot_defconfig
  21. 4
      configs/prs200_DDR_defconfig
  22. 4
      configs/prs200_defconfig
  23. 4
      configs/prs200_highboot_DDR_defconfig
  24. 4
      configs/prs200_highboot_defconfig
  25. 8
      doc/README.scrapyard
  26. 397
      include/configs/mcc200.h
  27. 2
      include/lcd.h

4
arch/powerpc/cpu/mpc5xxx/Kconfig
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@ -38,9 +38,6 @@ config TARGET_IPEK01
config TARGET_JUPITER
bool "Support jupiter"
config TARGET_MCC200
bool "Support mcc200"
config TARGET_MOTIONPRO
bool "Support motionpro"
@ -130,7 +127,6 @@ source "board/jupiter/Kconfig"
source "board/manroland/hmi1001/Kconfig"
source "board/manroland/mucmc52/Kconfig"
source "board/manroland/uc101/Kconfig"
source "board/mcc200/Kconfig"
source "board/motionpro/Kconfig"
source "board/munices/Kconfig"
source "board/phytec/pcm030/Kconfig"

9
board/mcc200/Kconfig
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@ -1,9 +0,0 @@
if TARGET_MCC200
config SYS_BOARD
default "mcc200"
config SYS_CONFIG_NAME
default "mcc200"
endif

17
board/mcc200/MAINTAINERS
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@ -1,17 +0,0 @@
MCC200 BOARD
#M: -
S: Maintained
F: board/mcc200/
F: include/configs/mcc200.h
F: configs/mcc200_defconfig
F: configs/mcc200_COM12_defconfig
F: configs/mcc200_COM12_highboot_defconfig
F: configs/mcc200_COM12_highboot_SDRAM_defconfig
F: configs/mcc200_COM12_SDRAM_defconfig
F: configs/mcc200_highboot_defconfig
F: configs/mcc200_highboot_SDRAM_defconfig
F: configs/mcc200_SDRAM_defconfig
F: configs/prs200_defconfig
F: configs/prs200_DDR_defconfig
F: configs/prs200_highboot_defconfig
F: configs/prs200_highboot_DDR_defconfig

8
board/mcc200/Makefile
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@ -1,8 +0,0 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mcc200.o lcd.o auto_update.o

521
board/mcc200/auto_update.c
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@ -1,521 +0,0 @@
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <image.h>
#include <asm/byteorder.h>
#include <usb.h>
#include <part.h>
#ifdef CONFIG_AUTO_UPDATE
#ifndef CONFIG_USB_OHCI
#error "must define CONFIG_USB_OHCI"
#endif
#ifndef CONFIG_USB_STORAGE
#error "must define CONFIG_USB_STORAGE"
#endif
#ifndef CONFIG_SYS_HUSH_PARSER
#error "must define CONFIG_SYS_HUSH_PARSER"
#endif
#if !defined(CONFIG_CMD_FAT)
#error "must define CONFIG_CMD_FAT"
#endif
#undef AU_DEBUG
#undef debug
#ifdef AU_DEBUG
#define debug(fmt,args...) printf (fmt ,##args)
#else
#define debug(fmt,args...)
#endif /* AU_DEBUG */
/* possible names of files on the USB stick. */
#define AU_FIRMWARE "u-boot.img"
#define AU_KERNEL "kernel.img"
#define AU_ROOTFS "rootfs.img"
struct flash_layout {
long start;
long end;
};
/* layout of the FLASH. ST = start address, ND = end address. */
#define AU_FL_FIRMWARE_ST 0xfC000000
#define AU_FL_FIRMWARE_ND 0xfC03FFFF
#define AU_FL_KERNEL_ST 0xfC0C0000
#define AU_FL_KERNEL_ND 0xfC1BFFFF
#define AU_FL_ROOTFS_ST 0xFC1C0000
#define AU_FL_ROOTFS_ND 0xFCFBFFFF
static int au_usb_stor_curr_dev; /* current device */
/* index of each file in the following arrays */
#define IDX_FIRMWARE 0
#define IDX_KERNEL 1
#define IDX_ROOTFS 2
/* max. number of files which could interest us */
#define AU_MAXFILES 3
/* pointers to file names */
char *aufile[AU_MAXFILES] = {
AU_FIRMWARE,
AU_KERNEL,
AU_ROOTFS
};
/* sizes of flash areas for each file */
long ausize[AU_MAXFILES] = {
(AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST,
(AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST,
(AU_FL_ROOTFS_ND + 1) - AU_FL_ROOTFS_ST,
};
/* array of flash areas start and end addresses */
struct flash_layout aufl_layout[AU_MAXFILES] = {
{ AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND, },
{ AU_FL_KERNEL_ST, AU_FL_KERNEL_ND, },
{ AU_FL_ROOTFS_ST, AU_FL_ROOTFS_ND, },
};
ulong totsize;
/* where to load files into memory */
#define LOAD_ADDR ((unsigned char *)0x00200000)
/* the root file system is the largest image */
#define MAX_LOADSZ ausize[IDX_ROOTFS]
/*i2c address of the keypad status*/
#define I2C_PSOC_KEYPAD_ADDR 0x53
/* keypad mask */
#define KEYPAD_ROW 2
#define KEYPAD_COL 2
#define KEYPAD_MASK_LO ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))&0xFF)
#define KEYPAD_MASK_HI ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))>>8)
/* externals */
extern int fat_register_device(block_dev_desc_t *, int);
extern int file_fat_detectfs(void);
extern long file_fat_read(const char *, void *, unsigned long);
extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int);
extern int flash_sect_erase(ulong, ulong);
extern int flash_sect_protect (int, ulong, ulong);
extern int flash_write (char *, ulong, ulong);
extern int u_boot_hush_start(void);
#ifdef CONFIG_PROGRESSBAR
extern void show_progress(int, int);
extern void lcd_puts (char *);
extern void lcd_enable(void);
#endif
int au_check_cksum_valid(int idx, long nbytes)
{
image_header_t *hdr;
hdr = (image_header_t *)LOAD_ADDR;
#if defined(CONFIG_FIT)
if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
puts ("Non legacy image format not supported\n");
return -1;
}
#endif
if (nbytes != image_get_image_size (hdr)) {
printf ("Image %s bad total SIZE\n", aufile[idx]);
return -1;
}
/* check the data CRC */
if (!image_check_dcrc (hdr)) {
printf ("Image %s bad data checksum\n", aufile[idx]);
return -1;
}
return 0;
}
int au_check_header_valid(int idx, long nbytes)
{
image_header_t *hdr;
unsigned long checksum, fsize;
hdr = (image_header_t *)LOAD_ADDR;
#if defined(CONFIG_FIT)
if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
puts ("Non legacy image format not supported\n");
return -1;
}
#endif
/* check the easy ones first */
#undef CHECK_VALID_DEBUG
#ifdef CHECK_VALID_DEBUG
printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC);
printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_ARM);
printf("size %#x %#lx ", image_get_data_size (hdr), nbytes);
printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL);
#endif
if (nbytes < image_get_header_size ()) {
printf ("Image %s bad header SIZE\n", aufile[idx]);
ausize[idx] = 0;
return -1;
}
if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) {
printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]);
ausize[idx] = 0;
return -1;
}
/* check the hdr CRC */
if (!image_check_hcrc (hdr)) {
printf ("Image %s bad header checksum\n", aufile[idx]);
ausize[idx] = 0;
return -1;
}
/* check the type - could do this all in one gigantic if() */
if ((idx == IDX_FIRMWARE) && !image_check_type (hdr, IH_TYPE_FIRMWARE)) {
printf ("Image %s wrong type\n", aufile[idx]);
ausize[idx] = 0;
return -1;
}
if ((idx == IDX_KERNEL) && !image_check_type (hdr, IH_TYPE_KERNEL)) {
printf ("Image %s wrong type\n", aufile[idx]);
ausize[idx] = 0;
return -1;
}
if ((idx == IDX_ROOTFS) &&
(!image_check_type (hdr, IH_TYPE_RAMDISK) &&
!image_check_type (hdr, IH_TYPE_FILESYSTEM))) {
printf ("Image %s wrong type\n", aufile[idx]);
ausize[idx] = 0;
return -1;
}
/* recycle checksum */
checksum = image_get_data_size (hdr);
fsize = checksum + image_get_header_size ();
/* for kernel and ramdisk the image header must also fit into flash */
if (idx == IDX_KERNEL || image_check_type (hdr, IH_TYPE_RAMDISK))
checksum += image_get_header_size ();
/* check the size does not exceed space in flash. HUSH scripts */
if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
printf ("Image %s is bigger than FLASH\n", aufile[idx]);
ausize[idx] = 0;
return -1;
}
/* Update with the real filesize */
ausize[idx] = fsize;
return checksum; /* return size to be written to flash */
}
int au_do_update(int idx, long sz)
{
image_header_t *hdr;
char *addr;
long start, end;
int off, rc;
uint nbytes;
hdr = (image_header_t *)LOAD_ADDR;
#if defined(CONFIG_FIT)
if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
puts ("Non legacy image format not supported\n");
return -1;
}
#endif
/* execute a script */
if (image_check_type (hdr, IH_TYPE_SCRIPT)) {
addr = (char *)((char *)hdr + image_get_header_size ());
/* stick a NULL at the end of the script, otherwise */
/* parse_string_outer() runs off the end. */
addr[image_get_data_size (hdr)] = 0;
addr += 8;
run_command_list(addr, -1, 0);
return 0;
}
start = aufl_layout[idx].start;
end = aufl_layout[idx].end;
/* unprotect the address range */
/* this assumes that ONLY the firmware is protected! */
if (idx == IDX_FIRMWARE) {
#undef AU_UPDATE_TEST
#ifdef AU_UPDATE_TEST
/* erase it where Linux goes */
start = aufl_layout[1].start;
end = aufl_layout[1].end;
#endif
flash_sect_protect(0, start, end);
}
/*
* erase the address range.
*/
debug ("flash_sect_erase(%lx, %lx);\n", start, end);
flash_sect_erase(start, end);
mdelay(100);
#ifdef CONFIG_PROGRESSBAR
show_progress(end - start, totsize);
#endif
/* strip the header - except for the kernel and ramdisk */
if (image_check_type (hdr, IH_TYPE_KERNEL) ||
image_check_type (hdr, IH_TYPE_RAMDISK)) {
addr = (char *)hdr;
off = image_get_header_size ();
nbytes = image_get_image_size (hdr);
} else {
addr = (char *)((char *)hdr + image_get_header_size ());
#ifdef AU_UPDATE_TEST
/* copy it to where Linux goes */
if (idx == IDX_FIRMWARE)
start = aufl_layout[1].start;
#endif
off = 0;
nbytes = image_get_data_size (hdr);
}
/* copy the data from RAM to FLASH */
debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
rc = flash_write(addr, start, nbytes);
if (rc != 0) {
printf("Flashing failed due to error %d\n", rc);
return -1;
}
#ifdef CONFIG_PROGRESSBAR
show_progress(nbytes, totsize);
#endif
/* check the data CRC of the copy */
if (crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)) !=
image_get_dcrc (hdr)) {
printf ("Image %s Bad Data Checksum after COPY\n", aufile[idx]);
return -1;
}
/* protect the address range */
/* this assumes that ONLY the firmware is protected! */
if (idx == IDX_FIRMWARE)
flash_sect_protect(1, start, end);
return 0;
}
/*
* this is called from board_init() after the hardware has been set up
* and is usable. That seems like a good time to do this.
* Right now the return value is ignored.
*/
int do_auto_update(void)
{
block_dev_desc_t *stor_dev;
long sz;
int i, res = 0, cnt, old_ctrlc;
char *env;
long start, end;
#if 0 /* disable key-press detection to speed up boot-up time */
uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0};
/*
* Read keypad status
*/
i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status1, 2);
mdelay(500);
i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status2, 2);
/*
* Check keypad
*/
if ( !(keypad_status1[1] & KEYPAD_MASK_LO) ||
(keypad_status1[1] != keypad_status2[1])) {
return 0;
}
#endif
au_usb_stor_curr_dev = -1;
/* start USB */
if (usb_stop() < 0) {
debug ("usb_stop failed\n");
return -1;
}
if (usb_init() < 0) {
debug ("usb_init failed\n");
return -1;
}
/*
* check whether a storage device is attached (assume that it's
* a USB memory stick, since nothing else should be attached).
*/
au_usb_stor_curr_dev = usb_stor_scan(0);
if (au_usb_stor_curr_dev == -1) {
debug ("No device found. Not initialized?\n");
res = -1;
goto xit;
}
/* check whether it has a partition table */
stor_dev = get_dev("usb", 0);
if (stor_dev == NULL) {
debug ("uknown device type\n");
res = -1;
goto xit;
}
if (fat_register_device(stor_dev, 1) != 0) {
debug ("Unable to use USB %d:%d for fatls\n",
au_usb_stor_curr_dev, 1);
res = -1;
goto xit;
}
if (file_fat_detectfs() != 0) {
debug ("file_fat_detectfs failed\n");
}
/*
* now check whether start and end are defined using environment
* variables.
*/
start = -1;
end = 0;
env = getenv("firmware_st");
if (env != NULL)
start = simple_strtoul(env, NULL, 16);
env = getenv("firmware_nd");
if (env != NULL)
end = simple_strtoul(env, NULL, 16);
if (start >= 0 && end && end > start) {
ausize[IDX_FIRMWARE] = (end + 1) - start;
aufl_layout[IDX_FIRMWARE].start = start;
aufl_layout[IDX_FIRMWARE].end = end;
}
start = -1;
end = 0;
env = getenv("kernel_st");
if (env != NULL)
start = simple_strtoul(env, NULL, 16);
env = getenv("kernel_nd");
if (env != NULL)
end = simple_strtoul(env, NULL, 16);
if (start >= 0 && end && end > start) {
ausize[IDX_KERNEL] = (end + 1) - start;
aufl_layout[IDX_KERNEL].start = start;
aufl_layout[IDX_KERNEL].end = end;
}
start = -1;
end = 0;
env = getenv("rootfs_st");
if (env != NULL)
start = simple_strtoul(env, NULL, 16);
env = getenv("rootfs_nd");
if (env != NULL)
end = simple_strtoul(env, NULL, 16);
if (start >= 0 && end && end > start) {
ausize[IDX_ROOTFS] = (end + 1) - start;
aufl_layout[IDX_ROOTFS].start = start;
aufl_layout[IDX_ROOTFS].end = end;
}
/* make certain that HUSH is runnable */
u_boot_hush_start();
/* make sure that we see CTRL-C and save the old state */
old_ctrlc = disable_ctrlc(0);
/* validate the images first */
for (i = 0; i < AU_MAXFILES; i++) {
ulong imsize;
/* just read the header */
sz = file_fat_read(aufile[i], LOAD_ADDR, image_get_header_size ());
debug ("read %s sz %ld hdr %d\n",
aufile[i], sz, image_get_header_size ());
if (sz <= 0 || sz < image_get_header_size ()) {
debug ("%s not found\n", aufile[i]);
ausize[i] = 0;
continue;
}
/* au_check_header_valid() updates ausize[] */
if ((imsize = au_check_header_valid(i, sz)) < 0) {
debug ("%s header not valid\n", aufile[i]);
continue;
}
/* totsize accounts for image size and flash erase size */
totsize += (imsize + (aufl_layout[i].end - aufl_layout[i].start));
}
#ifdef CONFIG_PROGRESSBAR
if (totsize) {
lcd_puts(" Update in progress\n");
lcd_enable();
}
#endif
/* just loop thru all the possible files */
for (i = 0; i < AU_MAXFILES && totsize; i++) {
if (!ausize[i]) {
continue;
}
sz = file_fat_read(aufile[i], LOAD_ADDR, ausize[i]);
debug ("read %s sz %ld hdr %d\n",
aufile[i], sz, image_get_header_size ());
if (sz != ausize[i]) {
printf ("%s: size %ld read %ld?\n", aufile[i], ausize[i], sz);
continue;
}
if (sz <= 0 || sz <= image_get_header_size ()) {
debug ("%s not found\n", aufile[i]);
continue;
}
if (au_check_cksum_valid(i, sz) < 0) {
debug ("%s checksum not valid\n", aufile[i]);
continue;
}
/* this is really not a good idea, but it's what the */
/* customer wants. */
cnt = 0;
do {
res = au_do_update(i, sz);
/* let the user break out of the loop */
if (ctrlc() || had_ctrlc()) {
clear_ctrlc();
break;
}
cnt++;
#ifdef AU_TEST_ONLY
} while (res < 0 && cnt < (AU_MAXFILES + 1));
if (cnt < (AU_MAXFILES + 1))
#else
} while (res < 0);
#endif
}
/* restore the old state */
disable_ctrlc(old_ctrlc);
#ifdef CONFIG_PROGRESSBAR
if (totsize) {
if (!res) {
lcd_puts("\n Update completed\n");
} else {
lcd_puts("\n Update error\n");
}
lcd_enable();
}
#endif
xit:
usb_stop();
return res;
}
#endif /* CONFIG_AUTO_UPDATE */

200
board/mcc200/lcd.c
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@ -1,200 +0,0 @@
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <lcd.h>
#include <mpc5xxx.h>
#include <malloc.h>
#ifdef CONFIG_LCD
#undef SWAPPED_LCD /* For the previous h/w version */
/*
* The name of the device used for communication
* with the PSoC.
*/
#define PSOC_PSC MPC5XXX_PSC2
#define PSOC_BAUD 230400UL
#define RTS_ASSERT 1
#define RTS_NEGATE 0
#define CTS_ASSERT 1
#define CTS_NEGATE 0
/*
* Dimensions in pixels
*/
#define LCD_WIDTH 160
#define LCD_HEIGHT 100
/*
* Dimensions in bytes
*/
#define LCD_BUF_SIZE ((LCD_WIDTH*LCD_HEIGHT)>>3)
#if LCD_BPP != LCD_MONOCHROME
#error "MCC200 support only monochrome displays (1 bpp)!"
#endif
#define PSOC_RETRIES 10 /* each of PSOC_WAIT_TIME */
#define PSOC_WAIT_TIME 10 /* usec */
#include <video_font.h>
#define FONT_WIDTH VIDEO_FONT_WIDTH
DECLARE_GLOBAL_DATA_PTR;
/*
* LCD information
*/
vidinfo_t panel_info = {
LCD_WIDTH, LCD_HEIGHT, LCD_BPP
};
/*
* The device we use to communicate with PSoC
*/
int serial_inited = 0;
/*
* Imported functions to support the PSoC protocol
*/
extern int serial_init_dev (unsigned long dev_base);
extern void serial_setrts_dev (unsigned long dev_base, int s);
extern int serial_getcts_dev (unsigned long dev_base);
extern void serial_putc_raw_dev(unsigned long dev_base, const char c);
/*
* Just stubs for our driver, needed for compiling compabilty with
* the common LCD driver code.
*/
void lcd_initcolregs (void)
{
}
void lcd_ctrl_init (void *lcdbase)
{
}
/*
* Function sends the contents of the frame-buffer to the LCD
*/
void lcd_enable (void)
{
int i, retries, fb_size;
if (!serial_inited) {
unsigned long baud;
baud = gd->baudrate;
gd->baudrate = PSOC_BAUD;
serial_init_dev(PSOC_PSC);
gd->baudrate = baud;
serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
serial_inited = 1;
}
/*
* Implement PSoC communication protocol:
* 1. Assert RTS, wait CTS assertion
* 2. Transmit data
* 3. Negate RTS, wait CTS negation
*/
/* 1 */
serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
for (retries = PSOC_RETRIES; retries; retries--) {
if (serial_getcts_dev(PSOC_PSC) == CTS_ASSERT)
break;
udelay (PSOC_WAIT_TIME);
}
if (!retries) {
printf ("%s Error: PSoC doesn't respond on "
"RTS ASSERT\n", __FUNCTION__);
}
/* 2 */
fb_size = panel_info.vl_row * (panel_info.vl_col >> 3);
#if !defined(SWAPPED_LCD)
for (i=0; i<fb_size; i++) {
serial_putc_raw_dev(PSOC_PSC, ((char *)gd->fb_base)[i]);
}
#else
{
int x, y, pwidth;
char *p = (char *)gd->fb_base;
pwidth = ((panel_info.vl_col+7) >> 3);
for (y=0; y<panel_info.vl_row; y++) {
i = y * pwidth;
for (x=0; x<pwidth; x+=5) {
serial_putc_raw_dev (PSOC_PSC, (p[i+x+2]<<4 & 0xF0) | (p[i+x+3]>>4 & 0x0F));
serial_putc_raw_dev (PSOC_PSC, (p[i+x+3]<<4 & 0xF0) | (p[i+x+4]>>4 & 0x0F));
serial_putc_raw_dev (PSOC_PSC, (p[i+x+4]<<4 & 0xF0) | (p[i+x]>>4 & 0x0F));
serial_putc_raw_dev (PSOC_PSC, (p[i+x]<<4 & 0xF0) | (p[i+x+1]>>4 & 0x0F));
serial_putc_raw_dev (PSOC_PSC, (p[i+x+1]<<4 & 0xF0) | (p[i+x+2]>>4 & 0x0F));
}
}
}
#endif
/* 3 */
serial_setrts_dev (PSOC_PSC, RTS_NEGATE);
for (retries = PSOC_RETRIES; retries; retries--) {
if (serial_getcts_dev(PSOC_PSC) == CTS_NEGATE)
break;
udelay (PSOC_WAIT_TIME);
}
return;
}
#ifdef CONFIG_PROGRESSBAR
void show_progress (int size, int tot)
{
int cnt;
int i;
static int rc = 0;
rc += size;
cnt = ((LCD_WIDTH/FONT_WIDTH) * rc) / tot;
rc -= (cnt * tot) / (LCD_WIDTH/FONT_WIDTH);
for (i = 0; i < cnt; i++) {
lcd_putc(0xdc);
}
if (cnt) {
lcd_enable(); /* MCC200-specific - send the framebuffer to PSoC */
}
}
#endif
int bmp_display(ulong addr, int x, int y)
{
int ret;
bmp_image_t *bmp = (bmp_image_t *)addr;
if (!bmp) {
printf("There is no valid bmp file at the given address\n");
return 1;
}
ret = lcd_display_bitmap((ulong)bmp, x, y);
if ((unsigned long)bmp != addr)
free(bmp);
return ret;
}
#endif /* CONFIG_LCD */

314
board/mcc200/mcc200.c
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@ -1,314 +0,0 @@
/*
* (C) Copyright 2003-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
/* Two MT48LC8M32B2 for 32 MB */
/* #include "mt48lc8m32b2-6-7.h" */
/* One MT48LC16M32S2 for 64 MB */
/* #include "mt48lc16m32s2-75.h" */
#if defined (CONFIG_MCC200_SDRAM)
#include "mt48lc16m16a2-75.h"
#else
#include "mt46v16m16-75.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[]; /* FLASH chips info */
extern int do_auto_update(void);
ulong flash_get_size (ulong base, int banknum);
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set mode register: extended mode */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
__asm__ volatile ("sync");
/* set mode register: reset DLL */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
__asm__ volatile ("sync");
#endif
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
__asm__ volatile ("sync");
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
udelay(10);
}
#endif
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
uint svr, pvr;
#ifndef CONFIG_SYS_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set tap delay */
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
__asm__ volatile ("sync");
#endif
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20)) {
dramsize = 0;
}
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
} else {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
}
/* let SDRAM CS1 start right after CS0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
/* find RAM size using SDRAM CS1 only */
if (!dramsize)
sdram_start(0);
test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
} else {
dramsize2 = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize2 < (1 << 20)) {
dramsize2 = 0;
}
/* set SDRAM CS1 size according to the amount of RAM found */
if (dramsize2 > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
} else {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
}
#else /* CONFIG_SYS_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
if (dramsize >= 0x13) {
dramsize = (1 << (dramsize - 0x13)) << 20;
} else {
dramsize = 0;
}
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
if (dramsize2 >= 0x13) {
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
} else {
dramsize2 = 0;
}
#endif /* CONFIG_SYS_RAMBOOT */
/*
* On MPC5200B we need to set the special configuration delay in the
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
*
* "The SDelay should be written to a value of 0x00000004. It is
* required to account for changes caused by normal wafer processing
* parameters."
*/
svr = get_svr();
pvr = get_pvr();
if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
__asm__ volatile ("sync");
}
return dramsize + dramsize2;
}
int checkboard (void)
{
#if defined(CONFIG_PRS200)
puts ("Board: PRS200\n");
#else
puts ("Board: MCC200\n");
#endif
return 0;
}
int misc_init_r (void)
{
ulong flash_sup_end, snum;
/*
* Adjust flash start and offset to detected values
*/
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
/*
* Check if boot FLASH isn't max size
*/
if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) {
/* adjust mapping */
*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
START_REG(gd->bd->bi_flashstart);
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
/*
* Re-do flash protection upon new addresses
*/
flash_protect (FLAG_PROTECT_CLEAR,
gd->bd->bi_flashstart, 0xffffffff,
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Redundant environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
}
if (gd->bd->bi_flashsize > (32 << 20)) {
/* Unprotect the upper bank of the Flash */
*(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
flash_protect (FLAG_PROTECT_CLEAR,
flash_info[0].start[0] + flash_info[0].size / 2,
(flash_info[0].start[0] - 1) + flash_info[0].size,
&flash_info[0]);
*(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
flash_info[0].size = 32 << 20;
for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
flash_info[0].start[snum] < flash_sup_end;
snum++);
flash_info[0].sector_count = snum;
}
#ifdef CONFIG_AUTO_UPDATE
do_auto_update();
#endif
return (0);
}
#ifdef CONFIG_PCI
static struct pci_controller hose;
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void)
{
pci_mpc5xxx_init(&hose);
}
#endif
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
void init_ide_reset (void)
{
debug ("init_ide_reset\n");
}
void ide_set_reset (int idereset)
{
debug ("ide_reset(%d)\n", idereset);
}
#endif
#if defined(CONFIG_CMD_DOC)
void doc_init (void)
{
doc_probe (CONFIG_SYS_DOC_BASE);
}
#endif

16
board/mcc200/mt46v16m16-75.h
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@ -1,16 +0,0 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define SDRAM_DDR 1 /* is DDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x714f0f00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000

14
board/mcc200/mt48lc16m16a2-75.h
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@ -1,14 +0,0 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define SDRAM_DDR 0 /* is SDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000

14
board/mcc200/mt48lc16m32s2-75.h
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@ -1,14 +0,0 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define SDRAM_DDR 0 /* is SDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000

12
board/mcc200/mt48lc8m32b2-6-7.h
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@ -1,12 +0,0 @@
/*
* Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform
*/
#define SDRAM_DDR 0 /* is SDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */
#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */
#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */
#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */

24
common/lcd.c
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@ -881,7 +881,7 @@ static void lcd_display_rle8_bitmap(bmp_image_t *bmp, ushort *cmap, uchar *fb,
}
#endif
#if defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
#if defined(CONFIG_MPC823)
#define FB_PUT_BYTE(fb, from) *(fb)++ = (255 - *(from)++)
#else
#define FB_PUT_BYTE(fb, from) *(fb)++ = *(from)++
@ -906,9 +906,7 @@ static inline void fb_put_word(uchar **fb, uchar **from)
int lcd_display_bitmap(ulong bmp_image, int x, int y)
{
#if !defined(CONFIG_MCC200)
ushort *cmap = NULL;
#endif
ushort *cmap_base = NULL;
ushort i, j;
uchar *fb;
@ -956,8 +954,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
debug("Display-bmp: %d x %d with %d colors\n",
(int)width, (int)height, (int)colors);
#if !defined(CONFIG_MCC200)
/* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
if (bmp_bpix == 8) {
cmap = configuration_get_cmap();
cmap_base = cmap;
@ -985,24 +981,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
#endif
}
}
#endif
/*
* BMP format for Monochrome assumes that the state of a
* pixel is described on a per Bit basis, not per Byte.
* So, in case of Monochrome BMP we should align widths
* on a byte boundary and convert them from Bit to Byte
* units.
* Probably, PXA250 and MPC823 process 1bpp BMP images in
* their own ways, so make the converting to be MCC200
* specific.
*/
#if defined(CONFIG_MCC200)
if (bpix == 1) {
width = ((width + 7) & ~7) >> 3;
x = ((x + 7) & ~7) >> 3;
pwidth= ((pwidth + 7) & ~7) >> 3;
}
#endif
padded_width = (width & 0x3 ? (width & ~0x3) + 4 : width);

4
configs/mcc200_COM12_SDRAM_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,MCC200_SDRAM"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MCC200=y

4
configs/mcc200_COM12_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MCC200=y

4
configs/mcc200_COM12_highboot_SDRAM_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MCC200=y

4
configs/mcc200_COM12_highboot_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MCC200=y

4
configs/mcc200_SDRAM_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="MCC200_SDRAM"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MCC200=y

3
configs/mcc200_defconfig
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@ -1,3 +0,0 @@
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MCC200=y

4
configs/mcc200_highboot_SDRAM_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MCC200=y

4
configs/mcc200_highboot_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MCC200=y

4
configs/prs200_DDR_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="PRS200"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MCC200=y

4
configs/prs200_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="PRS200,MCC200_SDRAM"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MCC200=y

4
configs/prs200_highboot_DDR_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="PRS200,SYS_TEXT_BASE=0xFFF00000"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MCC200=y

4
configs/prs200_highboot_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MCC200=y

8
doc/README.scrapyard
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@ -12,9 +12,11 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
TOP5200 powerpc mpc5200 - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP860 powerpc mpc860 - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP9000 arm at91sam9xeXXX - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
PRS200 powerpc mpc5200 - -
MCC200 powerpc mpc5200 - -
TOP5200 powerpc mpc5200 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP860 powerpc mpc860 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP9000 arm at91sam9xeXXX d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TQM8272 powerpc mpc8260 f06f9a1 2014-10-27 Wolfgang Denk <wd@denx.de>
TQM8260 powerpc mpc8260 ccc1950 2014-10-27 Wolfgang Denk <wd@denx.de>
IDS8247 powerpc mpc8260 6afb357 2014-10-27 Heiko Schocher <hs@denx.de>

397
include/configs/mcc200.h
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@ -1,397 +0,0 @@
/*
* (C) Copyright 2006-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5200
#define CONFIG_MCC200 1 /* MCC200 board */
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
* 0xFC000000 boot low (standard configuration)
* 0xFFF00000 boot high
* 0x00100000 boot from RAM (for testing only)
*/
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFC000000
#endif
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
#define CONFIG_MISC_INIT_R
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*
* To select console on the one of 8 external UARTs,
* define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
* or as 5, 6, 7, or 8 for the second Quad UART.
* COM11, COM12, COM13, COM14 are located on the second Quad UART.
*
* CONFIG_PSC_CONSOLE must be undefined in this case.
*/
#if !defined(CONFIG_PRS200)
/* MCC200 configuration: */
#ifdef CONFIG_CONSOLE_COM12
#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */
#else
#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */
#endif
#else
/* PRS200 configuration: */
#undef CONFIG_QUART_CONSOLE
#endif /* CONFIG_PRS200 */
/*
* To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
* and undefine CONFIG_QUART_CONSOLE.
*/
#if !defined(CONFIG_PRS200)
/* MCC200 configuration: */
#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */
#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */
#else
/* PRS200 configuration: */
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CONFIG_MII 1
#define CONFIG_DOS_PARTITION
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/* automatic software updates (see board/mcc200/auto_update.c) */
#define CONFIG_AUTO_UPDATE 1
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_USB
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#ifdef CONFIG_PRS200
# define CONFIG_SYS__BOARDNAME "prs200"
# define CONFIG_SYS__LINUX_CONSOLE "ttyS0"
#else
# define CONFIG_SYS__BOARDNAME "mcc200"
# define CONFIG_SYS__LINUX_CONSOLE "ttyEU5"
#endif
/* Network */
#define CONFIG_ETHADDR 00:17:17:ff:00:00
#define CONFIG_IPADDR 10.76.9.29
#define CONFIG_SERVERIP 10.76.9.1
#include <version.h> /* For U-Boot version */
#define CONFIG_EXTRA_ENV_SETTINGS \
"ubootver=" U_BOOT_VERSION "\0" \
"netdev=eth0\0" \
"hostname=" CONFIG_SYS__BOARDNAME "\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/mtdblock2 " \
"rootfstype=cramfs\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addcons=setenv bootargs ${bootargs} " \
"console=${console},${baudrate} " \
"ubootver=${ubootver} board=${board}\0" \
"flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};" \
"run nfsargs addip addcons;bootm\0" \
"console=" CONFIG_SYS__LINUX_CONSOLE "\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0" \
"load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0" \
"text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"kernel_addr=0xFC0C0000\0" \
"update=protect off ${text_base} +${filesize};" \
"era ${text_base} +${filesize};" \
"cp.b 200000 ${text_base} ${filesize}\0" \
"unlock=yes\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
/*
* IPB Bus clocking configuration.
*/
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* Flash configuration (8,16 or 32 MB)
* TEXT base always at 0xFFF00000
* ENV_ADDR always at 0xFFF40000
* FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
* 0xFE000000 for 32 MB
* 0xFF000000 for 16 MB
* 0xFF800000 for 8 MB
*/
#define CONFIG_SYS_FLASH_BASE 0xfc000000
#define CONFIG_SYS_FLASH_SIZE 0x04000000
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
#if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LOWBOOT 1
#endif
/*
* Memory map
*/
#define CONFIG_SYS_MBAR 0xf0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
/* #define CONFIG_MPC5xxx_FEC 1 */
/* #define CONFIG_MPC5xxx_FEC_MII100 */
/*
* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 1
/*
* LCD Splash Screen
*/
#if !defined(CONFIG_PRS200)
#define CONFIG_LCD 1
#define CONFIG_PROGRESSBAR 1
#endif
#if defined(CONFIG_LCD)
#define CONFIG_SPLASH_SCREEN 1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
#define LCD_BPP LCD_MONOCHROME
#endif
/*
* GPIO configuration
*/
/* 0x10000004 = 32MB SDRAM */
/* 0x90000004 = 64MB SDRAM */
#if defined(CONFIG_LCD)
/* set PSC2 in UART mode */
#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000044
#else
#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000004
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Various low-level settings
*/
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG 0x0004fb00
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
#define CONFIG_SYS_CS2_START 0x80000000
#define CONFIG_SYS_CS2_SIZE 0x00001000
#define CONFIG_SYS_CS2_CFG 0x1d300
/* Second Quad UART @0x80010000 */
#define CONFIG_SYS_CS1_START 0x80010000
#define CONFIG_SYS_CS1_SIZE 0x00001000
#define CONFIG_SYS_CS1_CFG 0x1d300
/* Leica - build revision resistors */
/*
#define CONFIG_SYS_CS3_START 0x80020000
#define CONFIG_SYS_CS3_SIZE 0x00000004
#define CONFIG_SYS_CS3_CFG 0x1d300
*/
/*
* Select one of quarts as a default
* console. If undefined - PSC console
* wil be default
*/
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
/*
* QUART Expanders support
*/
#if defined(CONFIG_QUART_CONSOLE)
/*
* We'll use NS16550 chip routines,
*/
#define CONFIG_SYS_NS16550 1
#define CONFIG_SYS_NS16550_SERIAL 1
#define CONFIG_CONS_INDEX 1
/*
* To achieve necessary offset on SC16C554
* A0-A2 (register select) pins with NS16550
* functions (in struct NS16550), REG_SIZE
* should be 4, because A0-A2 pins are connected
* to DA2-DA4 address bus lines.
*/
#define CONFIG_SYS_NS16550_REG_SIZE 4
/*
* LocalPlus Bus already inited in cpu_init_f(),
* so can work with QUART's chip selects.
* One of four SC16C554 UARTs is selected with
* A3-A4 (DA5-DA6) lines.
*/
#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
#else
#error "Wrong QUART expander number."
#endif
/*
* SC16C554 chip's external crystal oscillator frequency
* is 7.3728 MHz
*/
#define CONFIG_SYS_NS16550_CLK 7372800
#endif /* CONFIG_QUART_CONSOLE */
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00005000
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
#define CONFIG_AUTOBOOT_STOP_STR "432"
#define CONFIG_SILENT_CONSOLE 1
#endif /* __CONFIG_H */

2
include/lcd.h
Unescape View File

@ -250,7 +250,7 @@ typedef struct vidinfo {
void *priv; /* Pointer to driver-specific data */
} vidinfo_t;
#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */
#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_ATMEL_LCD */
extern vidinfo_t panel_info;

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