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@ -58,45 +58,12 @@ unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1; |
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int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; |
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#endif |
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#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178) |
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static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data) |
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{ |
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u16 val; |
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do { |
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FPGA_GET_REG(screen, extended_interrupt, &val); |
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} while (val & (1 << 12)); |
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FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8)); |
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FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1)); |
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} |
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static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg) |
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{ |
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unsigned int ctr = 0; |
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u16 val; |
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do { |
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FPGA_GET_REG(screen, extended_interrupt, &val); |
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} while (val & (1 << 12)); |
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FPGA_SET_REG(screen, extended_interrupt, 1 << 14); |
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FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg); |
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FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1)); |
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FPGA_GET_REG(screen, extended_interrupt, &val); |
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while (!(val & (1 << 14))) { |
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udelay(100000); |
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if (ctr++ > 5) { |
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printf("iic receive timeout\n"); |
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break; |
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} |
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FPGA_GET_REG(screen, extended_interrupt, &val); |
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} |
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#ifdef CONFIG_SYS_ICS8N3QV01 |
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int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C; |
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#endif |
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FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val); |
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return val >> 8; |
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} |
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#ifdef CONFIG_SYS_SIL1178 |
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int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C; |
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#endif |
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#ifdef CONFIG_SYS_MPC92469AC |
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@ -153,7 +120,7 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout) |
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#ifdef CONFIG_SYS_ICS8N3QV01 |
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static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index) |
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static unsigned int ics8n3qv01_get_fout_calc(unsigned index) |
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{ |
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unsigned long long n; |
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unsigned long long mint; |
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@ -164,11 +131,11 @@ static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index) |
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if (index > 3) |
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return 0; |
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reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index); |
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reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index); |
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reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index); |
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reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index); |
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reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index); |
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reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index); |
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reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index); |
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reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index); |
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reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index); |
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reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index); |
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mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20); |
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mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1) |
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@ -216,7 +183,7 @@ static void ics8n3qv01_calc_parameters(unsigned int fout, |
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*_n = n; |
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} |
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static void ics8n3qv01_set(unsigned screen, unsigned int fout) |
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static void ics8n3qv01_set(unsigned int fout) |
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{ |
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unsigned int n; |
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unsigned int mint; |
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@ -226,7 +193,7 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout) |
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long long off_ppm; |
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u8 reg0, reg4, reg8, reg12, reg18, reg20; |
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fout_calc = ics8n3qv01_get_fout_calc(screen, 1); |
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fout_calc = ics8n3qv01_get_fout_calc(1); |
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off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000 |
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/ ICS8N3QV01_F_DEFAULT_1; |
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printf(" PLL is off by %lld ppm\n", off_ppm); |
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@ -234,28 +201,28 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout) |
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/ ICS8N3QV01_F_DEFAULT_1; |
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ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n); |
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reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0; |
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reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0; |
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reg0 |= (mint & 0x1f) << 1; |
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reg0 |= (mfrac >> 17) & 0x01; |
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fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0); |
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i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0); |
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reg4 = mfrac >> 9; |
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fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4); |
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i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4); |
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reg8 = mfrac >> 1; |
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fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8); |
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i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8); |
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reg12 = mfrac << 7; |
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reg12 |= n & 0x7f; |
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fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12); |
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i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12); |
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reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03; |
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reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03; |
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reg18 |= 0x20; |
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fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18); |
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i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18); |
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reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f; |
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reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f; |
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reg20 |= mint & (1 << 5); |
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fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20); |
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i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20); |
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} |
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#endif |
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@ -315,9 +282,7 @@ int osd_probe(unsigned screen) |
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u16 version; |
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u16 features; |
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u8 value; |
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#ifdef CONFIG_SYS_CH7301 |
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int old_bus = i2c_get_bus_num(); |
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#endif |
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FPGA_GET_REG(0, osd.version, &version); |
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FPGA_GET_REG(0, osd.features, &features); |
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@ -345,7 +310,6 @@ int osd_probe(unsigned screen) |
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); |
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); |
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); |
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i2c_set_bus_num(old_bus); |
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#endif |
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#ifdef CONFIG_SYS_MPC92469AC |
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@ -353,29 +317,31 @@ int osd_probe(unsigned screen) |
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#endif |
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#ifdef CONFIG_SYS_ICS8N3QV01 |
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ics8n3qv01_set(screen, PIXCLK_640_480_60); |
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i2c_set_bus_num(ics8n3qv01_i2c[screen]); |
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ics8n3qv01_set(PIXCLK_640_480_60); |
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#endif |
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#ifdef CONFIG_SYS_SIL1178 |
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value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02); |
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i2c_set_bus_num(sil1178_i2c[screen]); |
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value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02); |
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if (value != 0x06) { |
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printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value); |
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printf(" Probing SIL1178, DEV_IDL %02x\n", value); |
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i2c_set_bus_num(old_bus); |
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return -1; |
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} |
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/* magic initialization sequence adapted from datasheet */ |
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fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36); |
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44); |
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c); |
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10); |
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80); |
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30); |
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89); |
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60); |
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36); |
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); |
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i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36); |
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44); |
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c); |
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10); |
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80); |
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30); |
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89); |
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60); |
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36); |
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); |
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#endif |
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FPGA_SET_REG(screen, videocontrol, 0x0002); |
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FPGA_SET_REG(screen, osd.control, 0x0049); |
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FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1)); |
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@ -385,6 +351,8 @@ int osd_probe(unsigned screen) |
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if (screen > max_osd_screen) |
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max_osd_screen = screen; |
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i2c_set_bus_num(old_bus); |
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return 0; |
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} |
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