The T4240QDS is a high-performance computing evaluation, development and test platform supporting the T4240 QorIQ Power Architecture™ processor. SERDES Connections 32 lanes grouped into four 8-lane banks Two “front side” banks dedicated to Ethernet Two “back side” banks dedicated to other protocols DDR Controllers Three independant 64-bit DDR3 controllers Supports rates up to 2133 MHz data-rate Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller QIXIS System Logic FPGA Each DDR controller has two DIMM slots. The first slot of each controller has up to 4 chip selects to support single-, dual- and quad-rank DIMMs. The second slot has only 2 chip selects to support single- and dual-rank DIMMs. At any given time, up to total 4 chip selects can be used. Detail information can be found in doc/README.t4qds Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>master
parent
98ffa19053
commit
ee52b188ca
@ -0,0 +1,54 @@ |
||||
#
|
||||
# Copyright 2012 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS-y += $(BOARD).o
|
||||
COBJS-y += ddr.o
|
||||
COBJS-$(CONFIG_T4240QDS)+= eth.o
|
||||
COBJS-$(CONFIG_PCI) += pci.o
|
||||
COBJS-y += law.o
|
||||
COBJS-y += tlb.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
clean: |
||||
rm -f $(OBJS) $(SOBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,186 @@ |
||||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License |
||||
* Version 2 or later as published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <hwconfig.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/fsl_ddr_sdram.h> |
||||
#include <asm/fsl_ddr_dimm_params.h> |
||||
#include <asm/fsl_law.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
struct board_specific_parameters { |
||||
u32 n_ranks; |
||||
u32 datarate_mhz_high; |
||||
u32 clk_adjust; |
||||
u32 wrlvl_start; |
||||
u32 wrlvl_ctl_2; |
||||
u32 wrlvl_ctl_3; |
||||
u32 cpo; |
||||
u32 write_data_delay; |
||||
u32 force_2T; |
||||
}; |
||||
|
||||
/*
|
||||
* This table contains all valid speeds we want to override with board |
||||
* specific parameters. datarate_mhz_high values need to be in ascending order |
||||
* for each n_ranks group. |
||||
*/ |
||||
static const struct board_specific_parameters udimm0[] = { |
||||
/*
|
||||
* memory controller 0 |
||||
* num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
||||
* ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | |
||||
*/ |
||||
{2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0}, |
||||
{2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, |
||||
{2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, |
||||
{1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, |
||||
{1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, |
||||
{1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, |
||||
{1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, |
||||
{} |
||||
}; |
||||
|
||||
/*
|
||||
* The three slots have slightly different timing. The center values are good |
||||
* for all slots. We use identical speed tables for them. In future use, if |
||||
* DIMMs require separated tables, make more entries as needed. |
||||
*/ |
||||
static const struct board_specific_parameters *udimms[] = { |
||||
udimm0, |
||||
}; |
||||
|
||||
static const struct board_specific_parameters rdimm0[] = { |
||||
/*
|
||||
* memory controller 0 |
||||
* num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
||||
* ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | |
||||
*/ |
||||
{4, 1350, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0}, |
||||
{4, 1666, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0}, |
||||
{4, 2140, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0}, |
||||
{2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0}, |
||||
{2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, |
||||
{2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, |
||||
{1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, |
||||
{1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, |
||||
{1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, |
||||
{1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, |
||||
{} |
||||
}; |
||||
|
||||
/*
|
||||
* The three slots have slightly different timing. See comments above. |
||||
*/ |
||||
static const struct board_specific_parameters *rdimms[] = { |
||||
rdimm0, |
||||
}; |
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts, |
||||
dimm_params_t *pdimm, |
||||
unsigned int ctrl_num) |
||||
{ |
||||
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
||||
ulong ddr_freq; |
||||
|
||||
if (ctrl_num > 2) { |
||||
printf("Not supported controller number %d\n", ctrl_num); |
||||
return; |
||||
} |
||||
if (!pdimm->n_ranks) |
||||
return; |
||||
|
||||
/*
|
||||
* we use identical timing for all slots. If needed, change the code |
||||
* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; |
||||
*/ |
||||
if (popts->registered_dimm_en) |
||||
pbsp = rdimms[0]; |
||||
else |
||||
pbsp = udimms[0]; |
||||
|
||||
|
||||
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
|
||||
* freqency and n_banks specified in board_specific_parameters table. |
||||
*/ |
||||
ddr_freq = get_ddr_freq(0) / 1000000; |
||||
while (pbsp->datarate_mhz_high) { |
||||
if (pbsp->n_ranks == pdimm->n_ranks) { |
||||
if (ddr_freq <= pbsp->datarate_mhz_high) { |
||||
popts->cpo_override = pbsp->cpo; |
||||
popts->write_data_delay = |
||||
pbsp->write_data_delay; |
||||
popts->clk_adjust = pbsp->clk_adjust; |
||||
popts->wrlvl_start = pbsp->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
popts->twoT_en = pbsp->force_2T; |
||||
goto found; |
||||
} |
||||
pbsp_highest = pbsp; |
||||
} |
||||
pbsp++; |
||||
} |
||||
|
||||
if (pbsp_highest) { |
||||
printf("Error: board specific timing not found " |
||||
"for data rate %lu MT/s\n" |
||||
"Trying to use the highest speed (%u) parameters\n", |
||||
ddr_freq, pbsp_highest->datarate_mhz_high); |
||||
popts->cpo_override = pbsp_highest->cpo; |
||||
popts->write_data_delay = pbsp_highest->write_data_delay; |
||||
popts->clk_adjust = pbsp_highest->clk_adjust; |
||||
popts->wrlvl_start = pbsp_highest->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
popts->twoT_en = pbsp_highest->force_2T; |
||||
} else { |
||||
panic("DIMM is not supported by this board"); |
||||
} |
||||
found: |
||||
/*
|
||||
* Factors to consider for half-strength driver enable: |
||||
* - number of DIMMs installed |
||||
*/ |
||||
popts->half_strength_driver_enable = 0; |
||||
/*
|
||||
* Write leveling override |
||||
*/ |
||||
popts->wrlvl_override = 1; |
||||
popts->wrlvl_sample = 0xf; |
||||
|
||||
/*
|
||||
* Rtt and Rtt_WR override |
||||
*/ |
||||
popts->rtt_override = 0; |
||||
|
||||
/* Enable ZQ calibration */ |
||||
popts->zq_en = 1; |
||||
|
||||
/* DHC_EN =1, ODT = 75 Ohm */ |
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); |
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
phys_size_t dram_size; |
||||
|
||||
puts("Initializing....using SPD\n"); |
||||
|
||||
dram_size = fsl_ddr_sdram(); |
||||
|
||||
dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
||||
dram_size *= 0x100000; |
||||
|
||||
puts(" DDR: "); |
||||
return dram_size; |
||||
} |
@ -0,0 +1,495 @@ |
||||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <netdev.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/fsl_ddr_sdram.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/fsl_portals.h> |
||||
#include <asm/fsl_liodn.h> |
||||
#include <malloc.h> |
||||
#include <fm_eth.h> |
||||
#include <fsl_mdio.h> |
||||
#include <miiphy.h> |
||||
#include <phy.h> |
||||
#include <asm/fsl_dtsec.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include "../common/qixis.h" |
||||
#include "../common/fman.h" |
||||
|
||||
#include "t4240qds_qixis.h" |
||||
|
||||
#define EMI_NONE 0xFFFFFFFF |
||||
#define EMI1_RGMII 0 |
||||
#define EMI1_SLOT1 1 |
||||
#define EMI1_SLOT2 2 |
||||
#define EMI1_SLOT3 3 |
||||
#define EMI1_SLOT4 4 |
||||
#define EMI1_SLOT5 5 |
||||
#define EMI1_SLOT7 7 |
||||
#define EMI2 8 /* tmp, FIXME */ |
||||
/* Slot6 and Slot8 do not have EMI connections */ |
||||
|
||||
static int mdio_mux[NUM_FM_PORTS]; |
||||
|
||||
static const char *mdio_names[] = { |
||||
"T4240QDS_MDIO0", |
||||
"T4240QDS_MDIO1", |
||||
"T4240QDS_MDIO2", |
||||
"T4240QDS_MDIO3", |
||||
"T4240QDS_MDIO4", |
||||
"T4240QDS_MDIO5", |
||||
"NULL", |
||||
"T4240QDS_MDIO7", |
||||
"T4240QDS_10GC", |
||||
}; |
||||
|
||||
static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2}; |
||||
static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4}; |
||||
|
||||
static const char *t4240qds_mdio_name_for_muxval(u8 muxval) |
||||
{ |
||||
return mdio_names[muxval]; |
||||
} |
||||
|
||||
struct mii_dev *mii_dev_for_muxval(u8 muxval) |
||||
{ |
||||
struct mii_dev *bus; |
||||
const char *name = t4240qds_mdio_name_for_muxval(muxval); |
||||
|
||||
if (!name) { |
||||
printf("No bus for muxval %x\n", muxval); |
||||
return NULL; |
||||
} |
||||
|
||||
bus = miiphy_get_dev_by_name(name); |
||||
|
||||
if (!bus) { |
||||
printf("No bus by name %s\n", name); |
||||
return NULL; |
||||
} |
||||
|
||||
return bus; |
||||
} |
||||
|
||||
struct t4240qds_mdio { |
||||
u8 muxval; |
||||
struct mii_dev *realbus; |
||||
}; |
||||
|
||||
static void t4240qds_mux_mdio(u8 muxval) |
||||
{ |
||||
u8 brdcfg4; |
||||
if ((muxval < 6) || (muxval == 7)) { |
||||
brdcfg4 = QIXIS_READ(brdcfg[4]); |
||||
brdcfg4 &= ~BRDCFG4_EMISEL_MASK; |
||||
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); |
||||
QIXIS_WRITE(brdcfg[4], brdcfg4); |
||||
} |
||||
} |
||||
|
||||
static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad, |
||||
int regnum) |
||||
{ |
||||
struct t4240qds_mdio *priv = bus->priv; |
||||
|
||||
t4240qds_mux_mdio(priv->muxval); |
||||
|
||||
return priv->realbus->read(priv->realbus, addr, devad, regnum); |
||||
} |
||||
|
||||
static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad, |
||||
int regnum, u16 value) |
||||
{ |
||||
struct t4240qds_mdio *priv = bus->priv; |
||||
|
||||
t4240qds_mux_mdio(priv->muxval); |
||||
|
||||
return priv->realbus->write(priv->realbus, addr, devad, regnum, value); |
||||
} |
||||
|
||||
static int t4240qds_mdio_reset(struct mii_dev *bus) |
||||
{ |
||||
struct t4240qds_mdio *priv = bus->priv; |
||||
|
||||
return priv->realbus->reset(priv->realbus); |
||||
} |
||||
|
||||
static int t4240qds_mdio_init(char *realbusname, u8 muxval) |
||||
{ |
||||
struct t4240qds_mdio *pmdio; |
||||
struct mii_dev *bus = mdio_alloc(); |
||||
|
||||
if (!bus) { |
||||
printf("Failed to allocate T4240QDS MDIO bus\n"); |
||||
return -1; |
||||
} |
||||
|
||||
pmdio = malloc(sizeof(*pmdio)); |
||||
if (!pmdio) { |
||||
printf("Failed to allocate T4240QDS private data\n"); |
||||
free(bus); |
||||
return -1; |
||||
} |
||||
|
||||
bus->read = t4240qds_mdio_read; |
||||
bus->write = t4240qds_mdio_write; |
||||
bus->reset = t4240qds_mdio_reset; |
||||
sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval)); |
||||
|
||||
pmdio->realbus = miiphy_get_dev_by_name(realbusname); |
||||
|
||||
if (!pmdio->realbus) { |
||||
printf("No bus with name %s\n", realbusname); |
||||
free(bus); |
||||
free(pmdio); |
||||
return -1; |
||||
} |
||||
|
||||
pmdio->muxval = muxval; |
||||
bus->priv = pmdio; |
||||
|
||||
return mdio_register(bus); |
||||
} |
||||
|
||||
void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, |
||||
enum fm_port port, int offset) |
||||
{ |
||||
if (mdio_mux[port] == EMI1_RGMII) |
||||
fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); |
||||
|
||||
/* TODO: will do with dts */ |
||||
} |
||||
|
||||
void fdt_fixup_board_enet(void *fdt) |
||||
{ |
||||
/* TODO: will do with dts */ |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
#if defined(CONFIG_FMAN_ENET) |
||||
int i; |
||||
struct memac_mdio_info dtsec_mdio_info; |
||||
struct memac_mdio_info tgec_mdio_info; |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 srds_prtcl_s1, srds_prtcl_s2; |
||||
|
||||
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL; |
||||
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; |
||||
srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS2_PRTCL; |
||||
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; |
||||
|
||||
/* Initialize the mdio_mux array so we can recognize empty elements */ |
||||
for (i = 0; i < NUM_FM_PORTS; i++) |
||||
mdio_mux[i] = EMI_NONE; |
||||
|
||||
dtsec_mdio_info.regs = |
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; |
||||
|
||||
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; |
||||
|
||||
/* Register the 1G MDIO bus */ |
||||
fm_memac_mdio_init(bis, &dtsec_mdio_info); |
||||
|
||||
tgec_mdio_info.regs = |
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; |
||||
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; |
||||
|
||||
/* Register the 10G MDIO bus */ |
||||
fm_memac_mdio_init(bis, &tgec_mdio_info); |
||||
|
||||
/* Register the muxing front-ends to the MDIO buses */ |
||||
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); |
||||
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); |
||||
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); |
||||
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); |
||||
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); |
||||
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); |
||||
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); |
||||
t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); |
||||
|
||||
|
||||
switch (srds_prtcl_s1) { |
||||
case 1: |
||||
case 2: |
||||
case 4: |
||||
/* XAUI/HiGig in Slot1 and Slot2 */ |
||||
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); |
||||
break; |
||||
case 28: |
||||
case 36: |
||||
/* SGMII in Slot1 and Slot2 */ |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); |
||||
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { |
||||
fm_info_set_phy_address(FM1_DTSEC9, |
||||
SGMII_CARD_PORT4_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC10, |
||||
SGMII_CARD_PORT3_PHY_ADDR); |
||||
} |
||||
break; |
||||
case 38: |
||||
fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR); |
||||
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { |
||||
fm_info_set_phy_address(FM1_DTSEC9, |
||||
QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC10, |
||||
QSGMII_CARD_PHY_ADDR); |
||||
} |
||||
break; |
||||
case 40: |
||||
case 46: |
||||
case 48: |
||||
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); |
||||
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { |
||||
fm_info_set_phy_address(FM1_DTSEC10, |
||||
SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC9, |
||||
SGMII_CARD_PORT4_PHY_ADDR); |
||||
} |
||||
fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR); |
||||
break; |
||||
default: |
||||
puts("Invalid SerDes1 protocol for T4240QDS\n"); |
||||
break; |
||||
} |
||||
|
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { |
||||
int idx = i - FM1_DTSEC1, lane, slot; |
||||
switch (fm_info_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_SGMII: |
||||
lane = serdes_get_first_lane(FSL_SRDS_1, |
||||
SGMII_FM1_DTSEC1 + idx); |
||||
if (lane < 0) |
||||
break; |
||||
slot = lane_to_slot_fsm1[lane]; |
||||
debug("FM1@DTSEC%u expects SGMII in slot %u\n", |
||||
idx + 1, slot); |
||||
if (QIXIS_READ(present2) & (1 << (slot - 1))) |
||||
fm_disable_port(i); |
||||
switch (slot) { |
||||
case 1: |
||||
mdio_mux[i] = EMI1_SLOT1; |
||||
fm_info_set_mdio(i, |
||||
mii_dev_for_muxval(mdio_mux[i])); |
||||
break; |
||||
case 2: |
||||
mdio_mux[i] = EMI1_SLOT2; |
||||
fm_info_set_mdio(i, |
||||
mii_dev_for_muxval(mdio_mux[i])); |
||||
break; |
||||
}; |
||||
break; |
||||
case PHY_INTERFACE_MODE_RGMII: |
||||
/* FM1 DTSEC5 routes to RGMII with EC2 */ |
||||
debug("FM1@DTSEC%u is RGMII at address %u\n", |
||||
idx + 1, 2); |
||||
if (i == FM1_DTSEC5) |
||||
fm_info_set_phy_address(i, 2); |
||||
mdio_mux[i] = EMI1_RGMII; |
||||
fm_info_set_mdio(i, |
||||
mii_dev_for_muxval(mdio_mux[i])); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { |
||||
switch (fm_info_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_XGMII: |
||||
mdio_mux[i] = EMI2; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
|
||||
#if (CONFIG_SYS_NUM_FMAN == 2) |
||||
switch (srds_prtcl_s2) { |
||||
case 1: |
||||
case 2: |
||||
case 4: |
||||
/* XAUI/HiGig in Slot3 and Slot4 */ |
||||
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR); |
||||
break; |
||||
case 7: |
||||
case 13: |
||||
case 14: |
||||
case 16: |
||||
case 22: |
||||
case 23: |
||||
case 25: |
||||
case 26: |
||||
/* XAUI/HiGig in Slot3, SGMII in Slot4 */ |
||||
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); |
||||
break; |
||||
case 28: |
||||
case 36: |
||||
/* SGMII in Slot3 and Slot4 */ |
||||
fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); |
||||
break; |
||||
case 38: |
||||
/* QSGMII in Slot3 and Slot4 */ |
||||
fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR); |
||||
break; |
||||
case 40: |
||||
case 46: |
||||
case 48: |
||||
/* SGMII in Slot3 */ |
||||
fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); |
||||
/* QSGMII in Slot4 */ |
||||
fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); |
||||
break; |
||||
case 50: |
||||
case 52: |
||||
case 54: |
||||
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); |
||||
break; |
||||
case 56: |
||||
case 57: |
||||
/* XFI in Slot3, SGMII in Slot4 */ |
||||
fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); |
||||
break; |
||||
default: |
||||
puts("Invalid SerDes2 protocol for T4240QDS\n"); |
||||
break; |
||||
} |
||||
|
||||
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { |
||||
int idx = i - FM2_DTSEC1, lane, slot; |
||||
switch (fm_info_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_SGMII: |
||||
lane = serdes_get_first_lane(FSL_SRDS_2, |
||||
SGMII_FM2_DTSEC1 + idx); |
||||
if (lane < 0) |
||||
break; |
||||
slot = lane_to_slot_fsm2[lane]; |
||||
debug("FM2@DTSEC%u expects SGMII in slot %u\n", |
||||
idx + 1, slot); |
||||
if (QIXIS_READ(present2) & (1 << (slot - 1))) |
||||
fm_disable_port(i); |
||||
switch (slot) { |
||||
case 3: |
||||
mdio_mux[i] = EMI1_SLOT3; |
||||
fm_info_set_mdio(i, |
||||
mii_dev_for_muxval(mdio_mux[i])); |
||||
break; |
||||
case 4: |
||||
mdio_mux[i] = EMI1_SLOT4; |
||||
fm_info_set_mdio(i, |
||||
mii_dev_for_muxval(mdio_mux[i])); |
||||
break; |
||||
}; |
||||
break; |
||||
case PHY_INTERFACE_MODE_RGMII: |
||||
/*
|
||||
* If DTSEC5 is RGMII, then it's routed via via EC1 to |
||||
* the first on-board RGMII port. If DTSEC6 is RGMII, |
||||
* then it's routed via via EC2 to the second on-board |
||||
* RGMII port. |
||||
*/ |
||||
debug("FM2@DTSEC%u is RGMII at address %u\n", |
||||
idx + 1, i == FM2_DTSEC5 ? 1 : 2); |
||||
fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2); |
||||
mdio_mux[i] = EMI1_RGMII; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { |
||||
switch (fm_info_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_XGMII: |
||||
mdio_mux[i] = EMI2; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
#endif /* CONFIG_SYS_NUM_FMAN */ |
||||
|
||||
cpu_eth_init(bis); |
||||
#endif /* CONFIG_FMAN_ENET */ |
||||
|
||||
return pci_eth_init(bis); |
||||
} |
@ -0,0 +1,47 @@ |
||||
/*
|
||||
* Copyright 2008-2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct law_entry law_table[] = { |
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), |
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
||||
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), |
||||
#endif |
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
||||
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), |
||||
#endif |
||||
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), |
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS |
||||
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), |
||||
#endif |
||||
#ifdef CONFIG_SYS_NAND_BASE_PHYS |
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), |
||||
#endif |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
@ -0,0 +1,39 @@ |
||||
/*
|
||||
* Copyright 2007-2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <pci.h> |
||||
#include <asm/fsl_pci.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
#include <asm/fsl_serdes.h> |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
fsl_pcie_init_board(0); |
||||
} |
||||
|
||||
void pci_of_setup(void *blob, bd_t *bd) |
||||
{ |
||||
FT_FSL_PCI_SETUP; |
||||
} |
@ -0,0 +1,56 @@ |
||||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __T4020QDS_QIXIS_H__ |
||||
#define __T4020QDS_QIXIS_H__ |
||||
|
||||
/* Definitions of QIXIS Registers for T4020QDS */ |
||||
|
||||
/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ |
||||
#define BRDCFG4_EMISEL_MASK 0xE0 |
||||
#define BRDCFG4_EMISEL_SHIFT 5 |
||||
|
||||
/* SYSCLK */ |
||||
#define QIXIS_SYSCLK_66 0x0 |
||||
#define QIXIS_SYSCLK_83 0x1 |
||||
#define QIXIS_SYSCLK_100 0x2 |
||||
#define QIXIS_SYSCLK_125 0x3 |
||||
#define QIXIS_SYSCLK_133 0x4 |
||||
#define QIXIS_SYSCLK_150 0x5 |
||||
#define QIXIS_SYSCLK_160 0x6 |
||||
#define QIXIS_SYSCLK_166 0x7 |
||||
|
||||
/* DDRCLK */ |
||||
#define QIXIS_DDRCLK_66 0x0 |
||||
#define QIXIS_DDRCLK_100 0x1 |
||||
#define QIXIS_DDRCLK_125 0x2 |
||||
#define QIXIS_DDRCLK_133 0x3 |
||||
|
||||
#define BRDCFG5_RESET 0x00 |
||||
|
||||
#define BRDCFG12_SD3EN_MASK 0x20 |
||||
#define BRDCFG12_SD3MX_MASK 0x08 |
||||
#define BRDCFG12_SD3MX_SLOT5 0x08 |
||||
#define BRDCFG12_SD3MX_SLOT6 0x00 |
||||
#define BRDCFG12_SD4EN_MASK 0x04 |
||||
#define BRDCFG12_SD4MX_MASK 0x03 |
||||
#define BRDCFG12_SD4MX_SLOT7 0x02 |
||||
#define BRDCFG12_SD4MX_SLOT8 0x01 |
||||
#define BRDCFG12_SD4MX_AURO_SATA 0x00 |
||||
#endif |
@ -0,0 +1,395 @@ |
||||
/*
|
||||
* Copyright 2009-2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <i2c.h> |
||||
#include <netdev.h> |
||||
#include <linux/compiler.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/fsl_portals.h> |
||||
#include <asm/fsl_liodn.h> |
||||
#include <fm_eth.h> |
||||
|
||||
#include "../common/qixis.h" |
||||
#include "../common/vsc3316_3308.h" |
||||
#include "t4qds.h" |
||||
#include "t4240qds_qixis.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
u8 sw; |
||||
struct cpu_type *cpu = gd->cpu; |
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
||||
unsigned int i; |
||||
|
||||
printf("Board: %sQDS, ", cpu->name); |
||||
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", |
||||
QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); |
||||
|
||||
sw = QIXIS_READ(brdcfg[0]); |
||||
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
||||
|
||||
if (sw < 0x8) |
||||
printf("vBank: %d\n", sw); |
||||
else if (sw == 0x8) |
||||
puts("Promjet\n"); |
||||
else if (sw == 0x9) |
||||
puts("NAND\n"); |
||||
else |
||||
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); |
||||
|
||||
/* Display the RCW, so that no one gets confused as to what RCW
|
||||
* we're actually using for this boot. |
||||
*/ |
||||
puts("Reset Configuration Word (RCW):"); |
||||
for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { |
||||
u32 rcw = in_be32(&gur->rcwsr[i]); |
||||
|
||||
if ((i % 4) == 0) |
||||
printf("\n %08x:", i * 4); |
||||
printf(" %08x", rcw); |
||||
} |
||||
puts("\n"); |
||||
|
||||
/*
|
||||
* Display the actual SERDES reference clocks as configured by the |
||||
* dip switches on the board. Note that the SWx registers could |
||||
* technically be set to force the reference clocks to match the |
||||
* values that the SERDES expects (or vice versa). For now, however, |
||||
* we just display both values and hope the user notices when they |
||||
* don't match. |
||||
*/ |
||||
puts("SERDES Reference Clocks: "); |
||||
sw = QIXIS_READ(brdcfg[2]); |
||||
for (i = 0; i < MAX_SERDES; i++) { |
||||
static const char *freq[] = { |
||||
"100", "125", "156.25", "161.1328125"}; |
||||
unsigned int clock = (sw >> (2 * i)) & 3; |
||||
|
||||
printf("SERDES%u=%sMHz ", i+1, freq[clock]); |
||||
} |
||||
puts("\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int select_i2c_ch_pca9547(u8 ch) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); |
||||
if (ret) { |
||||
puts("PCA: failed to select proper channel\n"); |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Configure Crossbar switches for Front-Side SerDes Ports */ |
||||
int config_frontside_crossbar_vsc3316(void) |
||||
{ |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 srds_prtcl_s1, srds_prtcl_s2; |
||||
int ret; |
||||
|
||||
ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL; |
||||
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; |
||||
if (srds_prtcl_s1) { |
||||
ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8); |
||||
if (ret) |
||||
return ret; |
||||
ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8); |
||||
if (ret) |
||||
return ret; |
||||
} |
||||
|
||||
srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS2_PRTCL; |
||||
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; |
||||
if (srds_prtcl_s2) { |
||||
ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8); |
||||
if (ret) |
||||
return ret; |
||||
ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8); |
||||
if (ret) |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int config_backside_crossbar_mux(void) |
||||
{ |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 srds_prtcl_s3, srds_prtcl_s4; |
||||
u8 brdcfg; |
||||
|
||||
srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS3_PRTCL; |
||||
srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; |
||||
switch (srds_prtcl_s3) { |
||||
case 0: |
||||
/* SerDes3 is not enabled */ |
||||
break; |
||||
case 2: |
||||
case 9: |
||||
case 10: |
||||
/* SD3(0:7) => SLOT5(0:7) */ |
||||
brdcfg = QIXIS_READ(brdcfg[12]); |
||||
brdcfg &= ~BRDCFG12_SD3MX_MASK; |
||||
brdcfg |= BRDCFG12_SD3MX_SLOT5; |
||||
QIXIS_WRITE(brdcfg[12], brdcfg); |
||||
break; |
||||
case 4: |
||||
case 6: |
||||
case 8: |
||||
case 12: |
||||
case 14: |
||||
case 16: |
||||
case 17: |
||||
case 19: |
||||
case 20: |
||||
/* SD3(4:7) => SLOT6(0:3) */ |
||||
brdcfg = QIXIS_READ(brdcfg[12]); |
||||
brdcfg &= ~BRDCFG12_SD3MX_MASK; |
||||
brdcfg |= BRDCFG12_SD3MX_SLOT6; |
||||
QIXIS_WRITE(brdcfg[12], brdcfg); |
||||
break; |
||||
default: |
||||
printf("WARNING: unsupported for SerDes3 Protocol %d\n", |
||||
srds_prtcl_s3); |
||||
return -1; |
||||
} |
||||
|
||||
srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS4_PRTCL; |
||||
srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; |
||||
switch (srds_prtcl_s4) { |
||||
case 0: |
||||
/* SerDes4 is not enabled */ |
||||
break; |
||||
case 2: |
||||
/* 10b, SD4(0:7) => SLOT7(0:7) */ |
||||
brdcfg = QIXIS_READ(brdcfg[12]); |
||||
brdcfg &= ~BRDCFG12_SD4MX_MASK; |
||||
brdcfg |= BRDCFG12_SD4MX_SLOT7; |
||||
QIXIS_WRITE(brdcfg[12], brdcfg); |
||||
break; |
||||
case 4: |
||||
case 6: |
||||
case 8: |
||||
/* x1b, SD4(4:7) => SLOT8(0:3) */ |
||||
brdcfg = QIXIS_READ(brdcfg[12]); |
||||
brdcfg &= ~BRDCFG12_SD4MX_MASK; |
||||
brdcfg |= BRDCFG12_SD4MX_SLOT8; |
||||
QIXIS_WRITE(brdcfg[12], brdcfg); |
||||
break; |
||||
case 10: |
||||
case 12: |
||||
case 14: |
||||
case 16: |
||||
case 18: |
||||
/* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ |
||||
brdcfg = QIXIS_READ(brdcfg[12]); |
||||
brdcfg &= ~BRDCFG12_SD4MX_MASK; |
||||
brdcfg |= BRDCFG12_SD4MX_AURO_SATA; |
||||
QIXIS_WRITE(brdcfg[12], brdcfg); |
||||
break; |
||||
default: |
||||
printf("WARNING: unsupported for SerDes4 Protocol %d\n", |
||||
srds_prtcl_s4); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_early_init_r(void) |
||||
{ |
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
||||
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); |
||||
|
||||
/*
|
||||
* Remap Boot flash + PROMJET region to caching-inhibited |
||||
* so that flash can be erased properly. |
||||
*/ |
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */ |
||||
flush_dcache(); |
||||
invalidate_icache(); |
||||
|
||||
/* invalidate existing TLB entry for flash + promjet */ |
||||
disable_tlb(flash_esel); |
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1); |
||||
|
||||
set_liodns(); |
||||
#ifdef CONFIG_SYS_DPAA_QBMAN |
||||
setup_portals(); |
||||
#endif |
||||
|
||||
/* Disable remote I2C connectoin */ |
||||
QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET); |
||||
|
||||
/* Configure board SERDES ports crossbar */ |
||||
config_frontside_crossbar_vsc3316(); |
||||
config_backside_crossbar_mux(); |
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
unsigned long get_board_sys_clk(void) |
||||
{ |
||||
u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
||||
|
||||
switch (sysclk_conf & 0x0F) { |
||||
case QIXIS_SYSCLK_83: |
||||
return 83333333; |
||||
case QIXIS_SYSCLK_100: |
||||
return 100000000; |
||||
case QIXIS_SYSCLK_125: |
||||
return 125000000; |
||||
case QIXIS_SYSCLK_133: |
||||
return 133333333; |
||||
case QIXIS_SYSCLK_150: |
||||
return 150000000; |
||||
case QIXIS_SYSCLK_160: |
||||
return 160000000; |
||||
case QIXIS_SYSCLK_166: |
||||
return 166666666; |
||||
} |
||||
return 66666666; |
||||
} |
||||
|
||||
unsigned long get_board_ddr_clk(void) |
||||
{ |
||||
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
||||
|
||||
switch ((ddrclk_conf & 0x30) >> 4) { |
||||
case QIXIS_DDRCLK_100: |
||||
return 100000000; |
||||
case QIXIS_DDRCLK_125: |
||||
return 125000000; |
||||
case QIXIS_DDRCLK_133: |
||||
return 133333333; |
||||
} |
||||
return 66666666; |
||||
} |
||||
|
||||
static const char *serdes_clock_to_string(u32 clock) |
||||
{ |
||||
switch (clock) { |
||||
case SRDS_PLLCR0_RFCK_SEL_100: |
||||
return "100"; |
||||
case SRDS_PLLCR0_RFCK_SEL_125: |
||||
return "125"; |
||||
case SRDS_PLLCR0_RFCK_SEL_156_25: |
||||
return "156.25"; |
||||
case SRDS_PLLCR0_RFCK_SEL_161_13: |
||||
return "161.1328125"; |
||||
default: |
||||
return "???"; |
||||
} |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
u8 sw; |
||||
serdes_corenet_t *srds_regs = |
||||
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; |
||||
u32 actual[MAX_SERDES]; |
||||
unsigned int i; |
||||
|
||||
sw = QIXIS_READ(brdcfg[2]); |
||||
for (i = 0; i < MAX_SERDES; i++) { |
||||
unsigned int clock = (sw >> (2 * i)) & 3; |
||||
switch (clock) { |
||||
case 0: |
||||
actual[i] = SRDS_PLLCR0_RFCK_SEL_100; |
||||
break; |
||||
case 1: |
||||
actual[i] = SRDS_PLLCR0_RFCK_SEL_125; |
||||
break; |
||||
case 2: |
||||
actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; |
||||
break; |
||||
case 3: |
||||
actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
for (i = 0; i < MAX_SERDES; i++) { |
||||
u32 pllcr0 = srds_regs->bank[i].pllcr0; |
||||
u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; |
||||
if (expected != actual[i]) { |
||||
printf("Warning: SERDES%u expects reference clock" |
||||
" %sMHz, but actual is %sMHz\n", i + 1, |
||||
serdes_clock_to_string(expected), |
||||
serdes_clock_to_string(actual[i])); |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
phys_addr_t base; |
||||
phys_size_t size; |
||||
|
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
base = getenv_bootm_low(); |
||||
size = getenv_bootm_size(); |
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size); |
||||
|
||||
#ifdef CONFIG_PCI |
||||
pci_of_setup(blob, bd); |
||||
#endif |
||||
|
||||
fdt_fixup_liodn(blob); |
||||
fdt_fixup_dr_usb(blob, bd); |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN |
||||
fdt_fixup_fman_ethernet(blob); |
||||
fdt_fixup_board_enet(blob); |
||||
#endif |
||||
} |
@ -0,0 +1,37 @@ |
||||
/*
|
||||
* Copyright 2011-2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CORENET_DS_H__ |
||||
#define __CORENET_DS_H__ |
||||
|
||||
void fdt_fixup_board_enet(void *blob); |
||||
void pci_of_setup(void *blob, bd_t *bd); |
||||
|
||||
static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7}, |
||||
{8, 8}, {9, 9}, {14, 14}, {15, 15} }; |
||||
|
||||
static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5}, |
||||
{10, 10}, {11, 11}, {12, 12}, {13, 13} }; |
||||
|
||||
static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4}, |
||||
{10, 11}, {11, 10}, {12, 2}, {13, 3} }; |
||||
|
||||
static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6}, |
||||
{8, 9}, {9, 8}, {14, 1}, {15, 0} }; |
||||
#endif |
@ -0,0 +1,136 @@ |
||||
/*
|
||||
* Copyright 2008-2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/* TLB 1 */ |
||||
/* *I*** - Covers boot page */ |
||||
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) |
||||
/*
|
||||
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the |
||||
* SRAM is at 0xfff00000, it covered the 0xfffff000. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_1M, 1), |
||||
#else |
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_4K, 1), |
||||
#endif |
||||
|
||||
/* *I*G* - CCSRBAR */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/* *I*G* - Flash, localbus */ |
||||
/* This will be changed to *I*G* after relocation to RAM. */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/* *I*G* - PCI */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_1G, 1), |
||||
|
||||
/* *I*G* - PCI */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, |
||||
CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, |
||||
CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/* *I*G* - PCI I/O */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_256K, 1), |
||||
|
||||
/* Bman/Qman */ |
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 9, BOOKE_PAGESZ_16M, 1), |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, |
||||
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 10, BOOKE_PAGESZ_16M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 11, BOOKE_PAGESZ_16M, 1), |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, |
||||
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 12, BOOKE_PAGESZ_16M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 13, BOOKE_PAGESZ_4M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_NAND_BASE |
||||
/*
|
||||
* *I*G - NAND |
||||
* entry 14 and 15 has been used hard coded, they will be disabled |
||||
* in cpu_init_f, so we use entry 16 for nand. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 16, BOOKE_PAGESZ_1M, 1), |
||||
#endif |
||||
SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 17, BOOKE_PAGESZ_4K, 1), |
||||
|
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
@ -0,0 +1,98 @@ |
||||
Overview |
||||
-------- |
||||
The T4240QDS is a high-performance computing evaluation, development and test |
||||
platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is |
||||
optimized to support the high-bandwidth DDR3 memory ports, as well as the |
||||
highly-configurable SerDes ports. The system is lead-free and RoHS-compliant. |
||||
|
||||
Board Features |
||||
SERDES Connections |
||||
32 lanes grouped into four 8-lane banks |
||||
Two “front side” banks dedicated to Ethernet |
||||
- High-speed crosspoint switch fabric on selected lanes |
||||
- Two PCI Express slots with side-band connector supporting |
||||
- SGMII |
||||
- XAUI |
||||
- HiGig |
||||
- I-pass connectors allow board-to-board and loopback support |
||||
Two “back side” banks dedicated to other protocols |
||||
- High-speed crosspoint switch fabric on all lanes |
||||
- Four PCI Express slots with side-band connector supporting |
||||
- PCI Express 3.0 |
||||
- SATA 2.0 |
||||
- SRIO 2.0 |
||||
- Supports 4X Aurora debug with two connectors |
||||
DDR Controllers |
||||
Three independant 64-bit DDR3 controllers |
||||
Supports rates of 1866 up to 2133 MHz data-rate |
||||
Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller |
||||
DDR power supplies 1.5V to all devices with automatic tracking of VTT. |
||||
Power software-switchable to 1.35V if software detects all DDR3LP devices. |
||||
MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and |
||||
2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time |
||||
increases by 1 clock. |
||||
|
||||
IFC/Local Bus |
||||
NAND flash: 8-bit, async or sync, up to 2GB. |
||||
NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB |
||||
NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB |
||||
- NOR devices support 16 virtual banks |
||||
GASIC: Minimal target within Qixis FPGA |
||||
PromJET rapid memory download support |
||||
Address demultiplexing handled within FPGA. |
||||
- Flexible demux allows 8 or 16 bit evaluation. |
||||
IFC Debug/Development card |
||||
- Support for 32-bit devices |
||||
Ethernet |
||||
Support two on-board RGMII 10/100/1G ethernet ports. |
||||
SGMII and XAUI support via SERDES block (see above). |
||||
1588 support via Symmetricom board. |
||||
QIXIS System Logic FPGA |
||||
Manages system power and reset sequencing |
||||
Manages DUT, board, clock, etc. configuration for dynamic shmoo |
||||
Collects V-I-T data in background for code/power profiling. |
||||
Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion) |
||||
General fault monitoring and logging |
||||
Runs from ATX “hot” power rails allowing operation while system is off. |
||||
Clocks |
||||
System and DDR clock (SYSCLK, “DDRCLK”) |
||||
- Switch selectable to one of 16 common settings in the interval 33MHz-166MHz. |
||||
- Software selectable in 1MHz increments from 1-200MHz. |
||||
SERDES clocks |
||||
- Provides clocks to all SerDes blocks and slots |
||||
- 100, 125 and 156.25 MHz |
||||
Power Supplies |
||||
Dedicated regulators for VDD |
||||
- Adjustable from (0.7V to 1.3V at 80A |
||||
- Regulators can be controlled by VID and/or software |
||||
Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A |
||||
- VTT/MVREF automatically track operating voltage |
||||
Dedicated regulators/filters for AVDD supplies |
||||
Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc. |
||||
USB |
||||
Supports two USB 2.0 ports with integrated PHYs |
||||
- One type A, one type micro-AB with 1.0A power per port. |
||||
Other IO |
||||
eSDHC/MMC |
||||
- SDHC card slot |
||||
eSPI port |
||||
- High-speed serial flash |
||||
Two Serial port |
||||
Four I2C ports |
||||
|
||||
Memory map |
||||
---------- |
||||
The addresses in brackets are physical addresses. |
||||
|
||||
0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB) |
||||
0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory |
||||
0x0_f000_0000 (0xf_0000_0000) - 0x0_f03f_ffff 4MB DCSR |
||||
0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan |
||||
0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan |
||||
0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO |
||||
0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash |
||||
0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR |
||||
0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS |
||||
0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores |
||||
|
||||
The physical address of the last (boot page translation) varies with the actual DDR size. |
@ -0,0 +1,35 @@ |
||||
/*
|
||||
* Copyright 2011-2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* T4240 QDS board configuration file |
||||
*/ |
||||
#define CONFIG_T4240QDS |
||||
#define CONFIG_PHYS_64BIT |
||||
#define CONFIG_PPC_T4240 |
||||
|
||||
#define CONFIG_FSL_SATA_V2 |
||||
#define CONFIG_PCIE4 |
||||
|
||||
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ |
||||
|
||||
#include "t4qds.h" |
@ -0,0 +1,875 @@ |
||||
/*
|
||||
* Copyright 2011-2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Corenet DS style board configuration file |
||||
*/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#ifdef CONFIG_RAMBOOT_PBL |
||||
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
||||
#endif |
||||
|
||||
#define CONFIG_CMD_REGINFO |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_BOOKE |
||||
#define CONFIG_E6500 |
||||
#define CONFIG_E500 /* BOOKE e500 family */ |
||||
#define CONFIG_E500MC /* BOOKE e500mc family */ |
||||
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
||||
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ |
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
||||
#define CONFIG_MP /* support multiple processors */ |
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_TEXT_BASE 0xeff80000 |
||||
#endif |
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS |
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS |
||||
#define CONFIG_FSL_IFC /* Enable IFC Support */ |
||||
#define CONFIG_PCI /* Enable PCI/PCIE */ |
||||
#define CONFIG_PCIE1 /* PCIE controler 1 */ |
||||
#define CONFIG_PCIE2 /* PCIE controler 2 */ |
||||
#define CONFIG_PCIE3 /* PCIE controler 3 */ |
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
||||
|
||||
#define CONFIG_SYS_SRIO |
||||
#define CONFIG_SRIO1 /* SRIO port 1 */ |
||||
#define CONFIG_SRIO2 /* SRIO port 2 */ |
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#ifdef CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
#else |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_NO_FLASH |
||||
#if defined(CONFIG_SPIFLASH) |
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_SPI_BUS 0 |
||||
#define CONFIG_ENV_SPI_CS 0 |
||||
#define CONFIG_ENV_SPI_MAX_HZ 10000000 |
||||
#define CONFIG_ENV_SPI_MODE 0 |
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
||||
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
#elif defined(CONFIG_SDCARD) |
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_OFFSET (512 * 1097) |
||||
#elif defined(CONFIG_NAND) |
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC |
||||
#define CONFIG_ENV_IS_IN_NAND |
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
||||
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) |
||||
#else |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
||||
#endif |
||||
#else /* CONFIG_SYS_NO_FLASH */ |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
||||
#endif |
||||
|
||||
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
unsigned long get_board_sys_clk(void); |
||||
unsigned long get_board_ddr_clk(void); |
||||
#endif |
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default. |
||||
*/ |
||||
#define CONFIG_SYS_CACHE_STASHING |
||||
#define CONFIG_BTB /* toggle branch predition */ |
||||
#define CONFIG_DDR_ECC |
||||
#ifdef CONFIG_DDR_ECC |
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
||||
#endif |
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS |
||||
|
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_ADDR_MAP |
||||
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ |
||||
#endif |
||||
|
||||
#if 0 |
||||
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ |
||||
#endif |
||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x00400000 |
||||
#define CONFIG_SYS_ALT_MEMTEST |
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */ |
||||
|
||||
/*
|
||||
* Config the L3 Cache as L3 SRAM |
||||
*/ |
||||
#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE |
||||
|
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_DCSRBAR 0xf0000000 |
||||
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull |
||||
#endif |
||||
|
||||
/* EEPROM */ |
||||
#define CONFIG_ID_EEPROM |
||||
#define CONFIG_SYS_I2C_EEPROM_NXID |
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CONFIG_VERY_BIG_RAM |
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
||||
|
||||
/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ |
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 2 |
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 4 |
||||
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE |
||||
|
||||
#define CONFIG_DDR_SPD |
||||
#define CONFIG_FSL_DDR3 |
||||
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0 |
||||
#define SPD_EEPROM_ADDRESS1 0x51 |
||||
#define SPD_EEPROM_ADDRESS2 0x52 |
||||
#define SPD_EEPROM_ADDRESS3 0x53 |
||||
#define SPD_EEPROM_ADDRESS4 0x54 |
||||
#define SPD_EEPROM_ADDRESS5 0x55 |
||||
#define SPD_EEPROM_ADDRESS6 0x56 |
||||
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ |
||||
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
||||
|
||||
/*
|
||||
* IFC Definitions |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_BASE 0xe0000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) |
||||
#else |
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) |
||||
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ |
||||
+ 0x8000000) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) |
||||
#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
||||
/* NOR Flash Timing Params */ |
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 |
||||
|
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ |
||||
FTIM0_NOR_TEADC(0x01) | \
|
||||
FTIM0_NOR_TEAHC(0x20)) |
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
||||
FTIM1_NOR_TRAD_NOR(0x1A) |\
|
||||
FTIM1_NOR_TSEQRAD_NOR(0x13)) |
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ |
||||
FTIM2_NOR_TCH(0x0E) | \
|
||||
FTIM2_NOR_TWPH(0x0E) | \
|
||||
FTIM2_NOR_TWP(0x1c)) |
||||
#define CONFIG_SYS_NOR_FTIM3 0x0 |
||||
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST |
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ |
||||
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
||||
|
||||
#define CONFIG_FSL_QIXIS /* use common QIXIS code */ |
||||
#define QIXIS_BASE 0xffdf0000 |
||||
#define QIXIS_LBMAP_SWITCH 6 |
||||
#define QIXIS_LBMAP_MASK 0x0f |
||||
#define QIXIS_LBMAP_SHIFT 0 |
||||
#define QIXIS_LBMAP_DFLTBANK 0x00 |
||||
#define QIXIS_LBMAP_ALTBANK 0x04 |
||||
#define QIXIS_RST_CTL_RESET 0x83 |
||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 |
||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) |
||||
#else |
||||
#define QIXIS_BASE_PHYS QIXIS_BASE |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_CSPR3_EXT (0xf) |
||||
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ |
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V) |
||||
#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) |
||||
#define CONFIG_SYS_CSOR3 0x0 |
||||
/* QIXIS Timing parameters for IFC CS3 */ |
||||
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
||||
FTIM0_GPCM_TEADC(0x0e) | \
|
||||
FTIM0_GPCM_TEAHC(0x0e)) |
||||
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
||||
FTIM1_GPCM_TRAD(0x3f)) |
||||
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ |
||||
FTIM2_GPCM_TCH(0x0) | \
|
||||
FTIM2_GPCM_TWP(0x1f)) |
||||
#define CONFIG_SYS_CS3_FTIM3 0x0 |
||||
|
||||
/* NAND Flash on IFC */ |
||||
#define CONFIG_NAND_FSL_IFC |
||||
#define CONFIG_SYS_NAND_BASE 0xff800000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) |
||||
#else |
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_NAND_CSPR_EXT (0xf) |
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
||||
| CSPR_V) |
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
||||
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
|
||||
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
|
||||
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
|
||||
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION |
||||
|
||||
/* ONFI NAND Flash mode0 Timing Params */ |
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ |
||||
FTIM0_NAND_TWP(0x18) | \
|
||||
FTIM0_NAND_TWCHT(0x07) | \
|
||||
FTIM0_NAND_TWH(0x0a)) |
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
||||
FTIM1_NAND_TWBE(0x39) | \
|
||||
FTIM1_NAND_TRR(0x0e) | \
|
||||
FTIM1_NAND_TRP(0x18)) |
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
||||
FTIM2_NAND_TREH(0x0a) | \
|
||||
FTIM2_NAND_TWHRE(0x1e)) |
||||
#define CONFIG_SYS_NAND_FTIM3 0x0 |
||||
|
||||
#define CONFIG_SYS_NAND_DDR_LAW 11 |
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||
#define CONFIG_CMD_NAND |
||||
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
||||
|
||||
#if defined(CONFIG_NAND) |
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR |
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK |
||||
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR |
||||
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||
#else |
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR |
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR |
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK |
||||
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR |
||||
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 |
||||
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 |
||||
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 |
||||
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 |
||||
#endif |
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR |
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||
|
||||
#if defined(CONFIG_RAMBOOT_PBL) |
||||
#define CONFIG_SYS_RAMBOOT |
||||
#endif |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_HWCONFIG |
||||
|
||||
/* define to use L1 as initial stack */ |
||||
#define CONFIG_L1_INIT_RAM |
||||
#define CONFIG_SYS_INIT_RAM_LOCK |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 |
||||
/* The assembler doesn't like typecast */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ |
||||
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
||||
#else |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS |
||||
#endif |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2 |
||||
* shorted - index 1 |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) |
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) |
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) |
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_OF_BOARD_SETUP |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS |
||||
|
||||
/* new uImage format support */ |
||||
#define CONFIG_FIT |
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_I2C_CMD_TREE |
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ |
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_I2C_OFFSET 0x118000 |
||||
#define CONFIG_SYS_I2C2_OFFSET 0x118100 |
||||
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ |
||||
#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ |
||||
|
||||
/* VSC Crossbar switches */ |
||||
#define CONFIG_VSC_CROSSBAR |
||||
#define I2C_MUX_CH_DEFAULT 0x8 |
||||
#define I2C_MUX_CH_VSC3316_FS 0xc |
||||
#define I2C_MUX_CH_VSC3316_BS 0xd |
||||
#define VSC3316_FSM_TX_ADDR 0x70 |
||||
#define VSC3316_FSM_RX_ADDR 0x71 |
||||
|
||||
/*
|
||||
* RapidIO |
||||
*/ |
||||
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull |
||||
#else |
||||
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 |
||||
#endif |
||||
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ |
||||
|
||||
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull |
||||
#else |
||||
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 |
||||
#endif |
||||
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ |
||||
|
||||
/*
|
||||
* for slave u-boot IMAGE instored in master memory space, |
||||
* PHYS must be aligned based on the SIZE |
||||
*/ |
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull |
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull |
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ |
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull |
||||
/*
|
||||
* for slave UCODE and ENV instored in master memory space, |
||||
* PHYS must be aligned based on the SIZE |
||||
*/ |
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull |
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ |
||||
|
||||
/* slave core release by master*/ |
||||
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 |
||||
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ |
||||
|
||||
/*
|
||||
* SRIO_PCIE_BOOT - SLAVE |
||||
*/ |
||||
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
||||
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 |
||||
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ |
||||
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) |
||||
#endif |
||||
/*
|
||||
* eSPI - Enhanced SPI |
||||
*/ |
||||
#define CONFIG_FSL_ESPI |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_SPANSION |
||||
#define CONFIG_CMD_SF |
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000 |
||||
#define CONFIG_SF_DEFAULT_MODE 0 |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Memory space is mapped 1-1, but I/O space must start from 0. |
||||
*/ |
||||
|
||||
/* controller 1, direct to uli, tgtid 3, Base address 20000 */ |
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ |
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ |
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 |
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
/* controller 4, Base address 203000 */ |
||||
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 |
||||
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull |
||||
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull |
||||
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
/* Qman/Bman */ |
||||
#ifndef CONFIG_NOBQFMAN |
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 50 |
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
||||
#else |
||||
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE |
||||
#endif |
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 |
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 50 |
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull |
||||
#else |
||||
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE |
||||
#endif |
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 |
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN |
||||
#define CONFIG_SYS_DPAA_PME |
||||
#define CONFIG_SYS_PMAN |
||||
#define CONFIG_SYS_DPAA_DCE |
||||
#define CONFIG_SYS_INTERLAKEN |
||||
|
||||
/* Default address of microcode for the Linux Fman driver */ |
||||
#if defined(CONFIG_SPIFLASH) |
||||
/*
|
||||
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after |
||||
* env, so we got 0x110000. |
||||
*/ |
||||
#define CONFIG_SYS_QE_FW_IN_SPIFLASH |
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 |
||||
#elif defined(CONFIG_SDCARD) |
||||
/*
|
||||
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is |
||||
* about 545KB (1089 blocks), Env is stored after the image, and the env size is |
||||
* 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. |
||||
*/ |
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC |
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) |
||||
#elif defined(CONFIG_NAND) |
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) |
||||
#else |
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 |
||||
#endif |
||||
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
||||
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
||||
#endif /* CONFIG_NOBQFMAN */ |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN |
||||
#define CONFIG_FMAN_ENET |
||||
#define CONFIG_PHYLIB_10G |
||||
#define CONFIG_PHY_VITESSE |
||||
#define CONFIG_PHY_TERANETICS |
||||
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C |
||||
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D |
||||
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E |
||||
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F |
||||
#define XFI_CARD_PORT1_PHY_ADDR 0x1 /* tmp, FIXME below addr */ |
||||
#define XFI_CARD_PORT2_PHY_ADDR 0x2 |
||||
#define XFI_CARD_PORT3_PHY_ADDR 0x3 |
||||
#define XFI_CARD_PORT4_PHY_ADDR 0x4 |
||||
#define QSGMII_CARD_PHY_ADDR 0x5 |
||||
#define FM1_10GEC1_PHY_ADDR 0x6 |
||||
#define FM1_10GEC2_PHY_ADDR 0x7 |
||||
#define FM2_10GEC1_PHY_ADDR 0x8 |
||||
#define FM2_10GEC2_PHY_ADDR 0x9 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_PCI |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CONFIG_E1000 |
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
/* SATA */ |
||||
#ifdef CONFIG_FSL_SATA_V2 |
||||
#define CONFIG_LIBATA |
||||
#define CONFIG_FSL_SATA |
||||
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 2 |
||||
#define CONFIG_SATA1 |
||||
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
||||
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
||||
#define CONFIG_SATA2 |
||||
#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
||||
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA |
||||
|
||||
#define CONFIG_LBA48 |
||||
#define CONFIG_CMD_SATA |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_CMD_EXT2 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FMAN_ENET |
||||
#define CONFIG_MII /* MII PHY management */ |
||||
#define CONFIG_ETHPRIME "FM1@DTSEC1" |
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_ERRATA |
||||
#define CONFIG_CMD_GREPENV |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SETEXPR |
||||
|
||||
#ifdef CONFIG_PCI |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_NET |
||||
#endif |
||||
|
||||
/*
|
||||
* USB |
||||
*/ |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_FSL |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_HAS_FSL_DR_USB |
||||
|
||||
#define CONFIG_MMC |
||||
|
||||
#ifdef CONFIG_MMC |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
||||
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 64 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ |
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
||||
|
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ROOTPATH "/opt/nfsroot" |
||||
#define CONFIG_BOOTFILE "uImage" |
||||
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ |
||||
|
||||
/* default location for tftp and bootm */ |
||||
#define CONFIG_LOADADDR 1000000 |
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define __USB_PHY_TYPE utmi |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"hwconfig=fsl_ddr:ctlr_intlv=3way_4KB," \
|
||||
"bank_intlv=auto;" \
|
||||
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot && " \
|
||||
"protect off $ubootaddr +$filesize && " \
|
||||
"erase $ubootaddr +$filesize && " \
|
||||
"cp.b $loadaddr $ubootaddr $filesize && " \
|
||||
"protect on $ubootaddr +$filesize && " \
|
||||
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=t4240qds/ramdisk.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=t4240qds/t4240qds.dtb\0" \
|
||||
"bdev=sda3\0" \
|
||||
"c=ffe\0" |
||||
|
||||
/* For emulation this causes u-boot to jump to the start of the proof point
|
||||
app code automatically */ |
||||
#define CONFIG_PROOF_POINTS \ |
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"cpu 1 release 0x29000000 - - -;" \
|
||||
"cpu 2 release 0x29000000 - - -;" \
|
||||
"cpu 3 release 0x29000000 - - -;" \
|
||||
"cpu 4 release 0x29000000 - - -;" \
|
||||
"cpu 5 release 0x29000000 - - -;" \
|
||||
"cpu 6 release 0x29000000 - - -;" \
|
||||
"cpu 7 release 0x29000000 - - -;" \
|
||||
"go 0x29000000" |
||||
|
||||
#define CONFIG_HVBOOT \ |
||||
"setenv bootargs config-addr=0x60000000; " \
|
||||
"bootm 0x01000000 - 0x00f00000" |
||||
|
||||
#define CONFIG_ALU \ |
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"cpu 1 release 0x01000000 - - -;" \
|
||||
"cpu 2 release 0x01000000 - - -;" \
|
||||
"cpu 3 release 0x01000000 - - -;" \
|
||||
"cpu 4 release 0x01000000 - - -;" \
|
||||
"cpu 5 release 0x01000000 - - -;" \
|
||||
"cpu 6 release 0x01000000 - - -;" \
|
||||
"cpu 7 release 0x01000000 - - -;" \
|
||||
"go 0x01000000" |
||||
|
||||
#define CONFIG_LINUX \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"setenv ramdiskaddr 0x02000000;" \
|
||||
"setenv fdtaddr 0x00c00000;" \
|
||||
"setenv loadaddr 0x1000000;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#define CONFIG_HDBOOT \ |
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_LINUX |
||||
|
||||
#ifdef CONFIG_SECURE_BOOT |
||||
#include <asm/fsl_secure_boot.h> |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue