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@ -44,8 +44,6 @@ int compare_to_true(char *str ); |
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char *remove_l_w_space(char *in_str ); |
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char *remove_t_w_space(char *in_str ); |
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int get_console_port(void); |
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unsigned long ppcMfcpr(unsigned long cpr_reg); |
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unsigned long ppcMfsdr(unsigned long sdr_reg); |
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int ppc440spe_init_pcie_rootport(int port); |
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void ppc440spe_setup_pcie(struct pci_controller *hose, int port); |
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@ -221,7 +219,7 @@ int board_early_init_f (void) |
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+-------------------------------------------------------------------*/ |
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/* Read Pin Strap Register in PPC440SP */ |
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sdr0_pinstp = ppcMfsdr(SDR0_PINSTP); |
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mfsdr(SDR0_PINSTP, sdr0_pinstp); |
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bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK; |
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switch (bootstrap_settings) { |
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@ -246,7 +244,7 @@ int board_early_init_f (void) |
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* Boot Settings in IIC EEprom address 0x50 or 0x54 |
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* Read Serial Device Strap Register1 in PPC440SPe |
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*/ |
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sdr0_sdstp1 = ppcMfsdr(SDR0_SDSTP1); |
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mfsdr(SDR0_SDSTP1, sdr0_sdstp1); |
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boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK; |
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ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK; |
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@ -564,277 +562,6 @@ int checkboard (void) |
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return 0; |
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} |
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static long int yucca_probe_for_dimms(void) |
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{ |
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int dimm_installed[MAXDIMMS]; |
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int dimm_num, result; |
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int dimms_found = 0; |
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uchar dimm_addr = IIC0_DIMM0_ADDR; |
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uchar dimm_spd_data[MAX_SPD_BYTES]; |
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for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { |
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/* check if there is a chip at the dimm address */ |
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switch (dimm_num) { |
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case 0: |
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dimm_addr = IIC0_DIMM0_ADDR; |
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break; |
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case 1: |
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dimm_addr = IIC0_DIMM1_ADDR; |
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break; |
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} |
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result = i2c_probe(dimm_addr); |
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memset(dimm_spd_data, 0, MAX_SPD_BYTES * sizeof(char)); |
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if (result == 0) { |
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/* read first byte of SPD data, if there is any data */ |
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result = i2c_read(dimm_addr, 0, 1, dimm_spd_data, 1); |
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if (result == 0) { |
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result = dimm_spd_data[0]; |
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result = result > MAX_SPD_BYTES ? |
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MAX_SPD_BYTES : result; |
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result = i2c_read(dimm_addr, 0, 1, |
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dimm_spd_data, result); |
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} |
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} |
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if ((result == 0) && |
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(dimm_spd_data[64] == MICRON_SPD_JEDEC_ID)) { |
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dimm_installed[dimm_num] = TRUE; |
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dimms_found++; |
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debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num); |
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} else { |
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dimm_installed[dimm_num] = FALSE; |
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debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num); |
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} |
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} |
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if (dimms_found == 0) { |
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printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); |
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hang(); |
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} |
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if (dimm_installed[0] != TRUE) { |
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printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n"); |
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printf(" Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n"); |
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hang(); |
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} |
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return dimms_found; |
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} |
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/*************************************************************************
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* init SDRAM controller with fixed value |
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* the initialization values are for 2x MICRON DDR2 |
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* PN: MT18HTF6472DY-53EB2 |
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* 512MB, DDR2, 533, CL4, ECC, REG |
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************************************************************************/ |
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static long int fixed_sdram(void) |
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{ |
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long int yucca_dimms = 0; |
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yucca_dimms = yucca_probe_for_dimms(); |
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/* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT */ |
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mtdcr( 0x10, 0x00000021 ); |
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mtdcr( 0x11, 0x84000000 ); |
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/* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2 */ |
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mtdcr( 0x10, 0x00000020 ); |
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mtdcr( 0x11, 0x2D122000 ); |
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/* SET MCIF0_CODT Die Termination On */ |
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mtdcr( 0x10, 0x00000026 ); |
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if (yucca_dimms == 2) |
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mtdcr( 0x11, 0x2A800021 ); |
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else if (yucca_dimms == 1) |
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mtdcr( 0x11, 0x02800021 ); |
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/* On-Die Termination for Bank 0 */ |
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mtdcr( 0x10, 0x00000022 ); |
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if (yucca_dimms == 2) |
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mtdcr( 0x11, 0x18000000 ); |
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else if (yucca_dimms == 1) |
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mtdcr( 0x11, 0x06000000 ); |
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/* On-Die Termination for Bank 1 */ |
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mtdcr( 0x10, 0x00000023 ); |
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if (yucca_dimms == 2) |
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mtdcr( 0x11, 0x18000000 ); |
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else if (yucca_dimms == 1) |
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mtdcr( 0x11, 0x01800000 ); |
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/* On-Die Termination for Bank 2 */ |
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mtdcr( 0x10, 0x00000024 ); |
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if (yucca_dimms == 2) |
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mtdcr( 0x11, 0x01800000 ); |
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else if (yucca_dimms == 1) |
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mtdcr( 0x11, 0x00000000 ); |
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/* On-Die Termination for Bank 3 */ |
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mtdcr( 0x10, 0x00000025 ); |
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if (yucca_dimms == 2) |
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mtdcr( 0x11, 0x01800000 ); |
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else if (yucca_dimms == 1) |
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mtdcr( 0x11, 0x00000000 ); |
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/* Refresh Time register (0x30) Refresh every 7.8125uS */ |
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mtdcr( 0x10, 0x00000030 ); |
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mtdcr( 0x11, 0x08200000 ); |
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/* SET MCIF0_MMODE CL 4 */ |
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mtdcr( 0x10, 0x00000088 ); |
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mtdcr( 0x11, 0x00000642 ); |
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/* MCIF0_MEMODE */ |
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mtdcr( 0x10, 0x00000089 ); |
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mtdcr( 0x11, 0x00000004 ); |
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/*SET MCIF0_MB0CF */ |
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mtdcr( 0x10, 0x00000040 ); |
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mtdcr( 0x11, 0x00000201 ); |
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/* SET MCIF0_MB1CF */ |
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mtdcr( 0x10, 0x00000044 ); |
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mtdcr( 0x11, 0x00000201 ); |
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/* SET MCIF0_MB2CF */ |
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mtdcr( 0x10, 0x00000048 ); |
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if (yucca_dimms == 2) |
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mtdcr( 0x11, 0x00000201 ); |
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else if (yucca_dimms == 1) |
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mtdcr( 0x11, 0x00000000 ); |
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/* SET MCIF0_MB3CF */ |
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mtdcr( 0x10, 0x0000004c ); |
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if (yucca_dimms == 2) |
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mtdcr( 0x11, 0x00000201 ); |
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else if (yucca_dimms == 1) |
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mtdcr( 0x11, 0x00000000 ); |
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/* SET MCIF0_INITPLR0 # NOP */ |
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mtdcr( 0x10, 0x00000050 ); |
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mtdcr( 0x11, 0xB5380000 ); |
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/* SET MCIF0_INITPLR1 # PRE */ |
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mtdcr( 0x10, 0x00000051 ); |
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mtdcr( 0x11, 0x82100400 ); |
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/* SET MCIF0_INITPLR2 # EMR2 */ |
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mtdcr( 0x10, 0x00000052 ); |
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mtdcr( 0x11, 0x80820000 ); |
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/* SET MCIF0_INITPLR3 # EMR3 */ |
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mtdcr( 0x10, 0x00000053 ); |
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mtdcr( 0x11, 0x80830000 ); |
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/* SET MCIF0_INITPLR4 # EMR DLL ENABLE */ |
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mtdcr( 0x10, 0x00000054 ); |
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mtdcr( 0x11, 0x80810000 ); |
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/* SET MCIF0_INITPLR5 # MR DLL RESET */ |
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mtdcr( 0x10, 0x00000055 ); |
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mtdcr( 0x11, 0x80800542 ); |
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/* SET MCIF0_INITPLR6 # PRE */ |
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mtdcr( 0x10, 0x00000056 ); |
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mtdcr( 0x11, 0x82100400 ); |
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/* SET MCIF0_INITPLR7 # Refresh */ |
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mtdcr( 0x10, 0x00000057 ); |
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mtdcr( 0x11, 0x8A080000 ); |
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/* SET MCIF0_INITPLR8 # Refresh */ |
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mtdcr( 0x10, 0x00000058 ); |
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mtdcr( 0x11, 0x8A080000 ); |
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/* SET MCIF0_INITPLR9 # Refresh */ |
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mtdcr( 0x10, 0x00000059 ); |
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mtdcr( 0x11, 0x8A080000 ); |
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/* SET MCIF0_INITPLR10 # Refresh */ |
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mtdcr( 0x10, 0x0000005A ); |
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mtdcr( 0x11, 0x8A080000 ); |
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/* SET MCIF0_INITPLR11 # MR */ |
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mtdcr( 0x10, 0x0000005B ); |
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mtdcr( 0x11, 0x80800442 ); |
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/* SET MCIF0_INITPLR12 # EMR OCD Default*/ |
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mtdcr( 0x10, 0x0000005C ); |
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mtdcr( 0x11, 0x80810380 ); |
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/* SET MCIF0_INITPLR13 # EMR OCD Exit */ |
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mtdcr( 0x10, 0x0000005D ); |
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mtdcr( 0x11, 0x80810000 ); |
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/* 0x80: Adv Addr clock by 180 deg */ |
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mtdcr( 0x10, 0x00000080 ); |
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mtdcr( 0x11, 0x80000000 ); |
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/* 0x21: Exit self refresh, set DC_EN */ |
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mtdcr( 0x10, 0x00000021 ); |
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mtdcr( 0x11, 0x28000000 ); |
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/* 0x81: Write DQS Adv 90 + Fractional DQS Delay */ |
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mtdcr( 0x10, 0x00000081 ); |
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mtdcr( 0x11, 0x80000800 ); |
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/* MCIF0_SDTR1 */ |
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mtdcr( 0x10, 0x00000085 ); |
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mtdcr( 0x11, 0x80201000 ); |
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/* MCIF0_SDTR2 */ |
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mtdcr( 0x10, 0x00000086 ); |
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mtdcr( 0x11, 0x42103242 ); |
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/* MCIF0_SDTR3 */ |
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mtdcr( 0x10, 0x00000087 ); |
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mtdcr( 0x11, 0x0C100D14 ); |
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/* SET MQ0_B0BAS base addr 00000000 / 256MB */ |
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mtdcr( 0x40, 0x0000F800 ); |
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/* SET MQ0_B1BAS base addr 10000000 / 256MB */ |
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mtdcr( 0x41, 0x0400F800 ); |
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/* SET MQ0_B2BAS base addr 20000000 / 256MB */ |
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if (yucca_dimms == 2) |
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mtdcr( 0x42, 0x0800F800 ); |
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else if (yucca_dimms == 1) |
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mtdcr( 0x42, 0x00000000 ); |
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/* SET MQ0_B3BAS base addr 30000000 / 256MB */ |
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if (yucca_dimms == 2) |
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mtdcr( 0x43, 0x0C00F800 ); |
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else if (yucca_dimms == 1) |
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mtdcr( 0x43, 0x00000000 ); |
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/* SDRAM_RQDC */ |
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mtdcr( 0x10, 0x00000070 ); |
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mtdcr( 0x11, 0x8000003F ); |
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/* SDRAM_RDCC */ |
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mtdcr( 0x10, 0x00000078 ); |
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mtdcr( 0x11, 0x80000000 ); |
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/* SDRAM_RFDC */ |
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mtdcr( 0x10, 0x00000074 ); |
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mtdcr( 0x11, 0x00000220 ); |
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return (yucca_dimms * 512) << 20; |
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} |
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long int initdram (int board_type) |
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{ |
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long dram_size = 0; |
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dram_size = fixed_sdram(); |
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return dram_size; |
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} |
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#if defined(CFG_DRAM_TEST) |
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|
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int testdram (void) |
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{ |
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|
@ -1267,42 +994,3 @@ int onboard_pci_arbiter_selected(int core_pci) |
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#endif |
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return (BOARD_OPTION_NOT_SELECTED); |
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} |
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|
|
/*---------------------------------------------------------------------------+
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|
| ppcMfcpr. |
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|
|
+---------------------------------------------------------------------------*/ |
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|
|
unsigned long ppcMfcpr(unsigned long cpr_reg) |
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|
|
{ |
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|
|
unsigned long msr; |
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|
|
unsigned long cpr_cfgaddr_temp; |
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|
|
unsigned long cpr_value; |
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msr = (mfmsr () & ~(MSR_EE)); |
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cpr_cfgaddr_temp = mfdcr(CPR0_CFGADDR); |
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|
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mtdcr(CPR0_CFGADDR, cpr_reg); |
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|
cpr_value = mfdcr(CPR0_CFGDATA); |
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|
|
mtdcr(CPR0_CFGADDR, cpr_cfgaddr_temp); |
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|
|
mtmsr(msr); |
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|
return (cpr_value); |
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|
|
} |
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/*----------------------------------------------------------------------------+
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| Indirect Access of the System DCR's (SDR) |
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| ppcMfsdr |
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+----------------------------------------------------------------------------*/ |
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unsigned long ppcMfsdr(unsigned long sdr_reg) |
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{ |
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unsigned long msr; |
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unsigned long sdr_cfgaddr_temp; |
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unsigned long sdr_value; |
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msr = (mfmsr () & ~(MSR_EE)); |
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sdr_cfgaddr_temp = mfdcr(SDR0_CFGADDR); |
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mtdcr(SDR0_CFGADDR, sdr_reg); |
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sdr_value = mfdcr(SDR0_CFGDATA); |
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mtdcr(SDR0_CFGADDR, sdr_cfgaddr_temp); |
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mtmsr(msr); |
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return (sdr_value); |
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} |
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Wolfgang Denk
18 years ago
committed by
Wolfgang Denk