@ -28,10 +28,10 @@
static u32 mx31_decode_pll ( u32 reg , u32 infreq )
{
u32 mfi = ( reg > > 10 ) & 0xf ;
u32 mfn = reg & 0x3ff ;
u32 mfd = ( reg > > 16 ) & 0x3ff ;
u32 pd = ( reg > > 26 ) & 0xf ;
u32 mfi = GET_PLL_MFI ( reg ) ;
u32 mfn = GET_PLL_MFN ( reg ) ;
u32 mfd = GET_PLL_MFD ( reg ) ;
u32 pd = GET_PLL_PD ( reg ) ;
mfi = mfi < = 5 ? 5 : mfi ;
mfd + = 1 ;
@ -45,12 +45,12 @@ static u32 mx31_get_mpl_dpdgck_clk(void)
{
u32 infreq ;
if ( ( __REG ( CCM_CCMR ) & CCMR_PRCS_MASK ) = = CCMR_FPM )
if ( ( readl ( CCM_CCMR ) & CCMR_PRCS_MASK ) = = CCMR_FPM )
infreq = CONFIG_MX31_CLK32 * 1024 ;
else
infreq = CONFIG_MX31_HCLK_FREQ ;
return mx31_decode_pll ( __REG ( CCM_MPCTL ) , infreq ) ;
return mx31_decode_pll ( readl ( CCM_MPCTL ) , infreq ) ;
}
static u32 mx31_get_mcu_main_clk ( void )
@ -64,10 +64,21 @@ static u32 mx31_get_mcu_main_clk(void)
static u32 mx31_get_ipg_clk ( void )
{
u32 freq = mx31_get_mcu_main_clk ( ) ;
u32 pdr0 = __REG ( CCM_PDR0 ) ;
u32 pdr0 = readl ( CCM_PDR0 ) ;
freq / = ( ( pdr0 > > 3 ) & 0x7 ) + 1 ;
freq / = ( ( pdr0 > > 6 ) & 0x3 ) + 1 ;
freq / = GET_PDR0_MAX_PODF ( pdr0 ) + 1 ;
freq / = GET_PDR0_IPG_PODF ( pdr0 ) + 1 ;
return freq ;
}
/* hsp is the clock for the ipu */
static u32 mx31_get_hsp_clk ( void )
{
u32 freq = mx31_get_mcu_main_clk ( ) ;
u32 pdr0 = readl ( CCM_PDR0 ) ;
freq / = GET_PDR0_HSP_PODF ( pdr0 ) + 1 ;
return freq ;
}
@ -77,6 +88,7 @@ void mx31_dump_clocks(void)
u32 cpufreq = mx31_get_mcu_main_clk ( ) ;
printf ( " mx31 cpu clock: %dMHz \n " , cpufreq / 1000000 ) ;
printf ( " ipg clock : %dHz \n " , mx31_get_ipg_clk ( ) ) ;
printf ( " hsp clock : %dHz \n " , mx31_get_hsp_clk ( ) ) ;
}
unsigned int mxc_get_clock ( enum mxc_clock clk )
@ -89,6 +101,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
case MXC_CSPI_CLK :
case MXC_UART_CLK :
return mx31_get_ipg_clk ( ) ;
case MXC_IPU_CLK :
return mx31_get_hsp_clk ( ) ;
}
return - 1 ;
}
@ -105,10 +119,10 @@ void mx31_gpio_mux(unsigned long mode)
reg = IOMUXC_BASE + ( mode & 0x1fc ) ;
shift = ( ~ mode & 0x3 ) * 8 ;
tmp = __REG ( reg ) ;
tmp = readl ( reg ) ;
tmp & = ~ ( 0xff < < shift ) ;
tmp | = ( ( mode > > IOMUX_MODE_POS ) & 0xff ) < < shift ;
__REG ( reg ) = tmp ;
writel ( tmp , reg ) ;
}
void mx31_set_pad ( enum iomux_pins pin , u32 config )
@ -119,10 +133,10 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
reg = ( IOMUXC_BASE + 0x154 ) + ( pin + 2 ) / 3 * 4 ;
field = ( pin + 2 ) % 3 ;
l = __REG ( reg ) ;
l = readl ( reg ) ;
l & = ~ ( 0x1ff < < ( field * 10 ) ) ;
l | = config < < ( field * 10 ) ;
__REG ( reg ) = l ;
writel ( l , reg ) ;
}