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@ -48,49 +48,49 @@ |
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/*
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* Set default values |
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*/ |
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#ifndef CFG_I2C_SPEED |
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#define CFG_I2C_SPEED 50000 |
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#ifndef CFG_I2C_SPEED |
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#define CFG_I2C_SPEED 50000 |
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#endif |
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#ifndef CFG_I2C_SLAVE |
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#define CFG_I2C_SLAVE 0xFE |
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#ifndef CFG_I2C_SLAVE |
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#define CFG_I2C_SLAVE 0xFE |
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#endif |
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#define ONE_BILLION 1000000000 |
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#define ONE_BILLION 1000000000 |
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#ifndef CONFIG_440 /* for 405 WALNUT/SYCAMORE/BUBINGA boards */ |
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#ifndef CONFIG_440 /* for 405 WALNUT/SYCAMORE/BUBINGA boards */ |
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#define SDRAM0_CFG_DCE 0x80000000 |
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#define SDRAM0_CFG_SRE 0x40000000 |
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#define SDRAM0_CFG_PME 0x20000000 |
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#define SDRAM0_CFG_MEMCHK 0x10000000 |
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#define SDRAM0_CFG_REGEN 0x08000000 |
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#define SDRAM0_CFG_ECCDD 0x00400000 |
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#define SDRAM0_CFG_EMDULR 0x00200000 |
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#define SDRAM0_CFG_DRW_SHIFT (31-6) |
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#define SDRAM0_CFG_BRPF_SHIFT (31-8) |
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#define SDRAM0_CFG_DCE 0x80000000 |
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#define SDRAM0_CFG_SRE 0x40000000 |
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#define SDRAM0_CFG_PME 0x20000000 |
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#define SDRAM0_CFG_MEMCHK 0x10000000 |
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#define SDRAM0_CFG_REGEN 0x08000000 |
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#define SDRAM0_CFG_ECCDD 0x00400000 |
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#define SDRAM0_CFG_EMDULR 0x00200000 |
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#define SDRAM0_CFG_DRW_SHIFT (31-6) |
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#define SDRAM0_CFG_BRPF_SHIFT (31-8) |
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#define SDRAM0_TR_CASL_SHIFT (31-8) |
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#define SDRAM0_TR_PTA_SHIFT (31-13) |
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#define SDRAM0_TR_CTP_SHIFT (31-15) |
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#define SDRAM0_TR_LDF_SHIFT (31-17) |
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#define SDRAM0_TR_RFTA_SHIFT (31-29) |
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#define SDRAM0_TR_RCD_SHIFT (31-31) |
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#define SDRAM0_TR_CASL_SHIFT (31-8) |
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#define SDRAM0_TR_PTA_SHIFT (31-13) |
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#define SDRAM0_TR_CTP_SHIFT (31-15) |
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#define SDRAM0_TR_LDF_SHIFT (31-17) |
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#define SDRAM0_TR_RFTA_SHIFT (31-29) |
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#define SDRAM0_TR_RCD_SHIFT (31-31) |
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#define SDRAM0_RTR_SHIFT (31-15) |
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#define SDRAM0_ECCCFG_SHIFT (31-11) |
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#define SDRAM0_RTR_SHIFT (31-15) |
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#define SDRAM0_ECCCFG_SHIFT (31-11) |
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/* SDRAM0_CFG enable macro */ |
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#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT ) |
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#define SDRAM0_BXCR_SZ_MASK 0x000e0000 |
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#define SDRAM0_BXCR_AM_MASK 0x0000e000 |
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#define SDRAM0_BXCR_SZ_MASK 0x000e0000 |
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#define SDRAM0_BXCR_AM_MASK 0x0000e000 |
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#define SDRAM0_BXCR_SZ_SHIFT (31-14) |
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#define SDRAM0_BXCR_AM_SHIFT (31-18) |
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#define SDRAM0_BXCR_SZ_SHIFT (31-14) |
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#define SDRAM0_BXCR_AM_SHIFT (31-18) |
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#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) ) |
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#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) ) |
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#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) ) |
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#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) ) |
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#ifdef CONFIG_SPDDRAM_SILENT |
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# define SPD_ERR(x) do { return 0; } while (0) |
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@ -175,7 +175,7 @@ long int spd_sdram(int(read_spd)(uint addr)) |
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* data from DIMM: |
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* 27 IN Row Precharge Time ( t RP) |
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* 29 MIN RAS to CAS Delay ( t RCD) |
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* 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS |
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* 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS |
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* -------------------------------------------------------------------*/ |
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/*
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@ -184,18 +184,18 @@ long int spd_sdram(int(read_spd)(uint addr)) |
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*/ |
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tmp = read_spd(127) & 0x6; |
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if (tmp == 0x02){ /* only cas = 2 supported */ |
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if (tmp == 0x02) { /* only cas = 2 supported */ |
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min_cas = 2; |
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/* t_ck = read_spd(9); */ |
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/* t_ac = read_spd(10); */ |
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} else if (tmp == 0x04) { /* only cas = 3 supported */ |
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/* t_ck = read_spd(9); */ |
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/* t_ac = read_spd(10); */ |
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} else if (tmp == 0x04) { /* only cas = 3 supported */ |
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min_cas = 3; |
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/* t_ck = read_spd(9); */ |
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/* t_ac = read_spd(10); */ |
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} else if (tmp == 0x06) { /* 2,3 supported, so use 2 */ |
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/* t_ck = read_spd(9); */ |
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/* t_ac = read_spd(10); */ |
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} else if (tmp == 0x06) { /* 2,3 supported, so use 2 */ |
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min_cas = 2; |
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/* t_ck = read_spd(23); */ |
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/* t_ac = read_spd(24); */ |
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/* t_ck = read_spd(23); */ |
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/* t_ac = read_spd(24); */ |
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} else { |
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SPD_ERR("SDRAM - unsupported CAS latency \n"); |
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} |
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@ -263,7 +263,7 @@ long int spd_sdram(int(read_spd)(uint addr)) |
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} |
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/* convert from nsec to bus cycles */ |
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tmp = (tmp * 10) / bus_period_x_10; |
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sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT; |
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sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT; |
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/*------------------------------------------------------------------
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* determine the number of banks used |
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@ -292,7 +292,7 @@ long int spd_sdram(int(read_spd)(uint addr)) |
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else if (tmp==4) |
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bank_cnt *= 4; |
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else |
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bank_cnt = 8; /* 8 is an error code */ |
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bank_cnt = 8; /* 8 is an error code */ |
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if (bank_cnt > 4) /* we only have 4 banks to work with */ |
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SPD_ERR("SDRAM - unsupported module rows for this width\n"); |
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@ -323,7 +323,7 @@ long int spd_sdram(int(read_spd)(uint addr)) |
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total_size *= read_spd(5); /* mult by module rows (dimm sides) */ |
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/*------------------------------------------------------------------
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* map rows * cols * banks to a mode |
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* map rows * cols * banks to a mode |
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* -------------------------------------------------------------------*/ |
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switch (row) { |
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@ -388,9 +388,9 @@ long int spd_sdram(int(read_spd)(uint addr)) |
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bank_size = total_size / bank_cnt; |
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/* convert bank size to bank size code for ppc4xx
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by takeing log2(bank_size) - 22 */ |
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tmp = bank_size; /* start with tmp = bank_size */ |
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tmp = bank_size; /* start with tmp = bank_size */ |
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bank_code = 0; /* and bank_code = 0 */ |
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while (tmp > 1) { /* this takes log2 of tmp */ |
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while (tmp > 1) { /* this takes log2 of tmp */ |
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bank_code++; /* and stores result in bank_code */ |
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tmp = tmp >> 1; |
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} /* bank_code is now log2(bank_size) */ |
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@ -444,7 +444,7 @@ long int spd_sdram(int(read_spd)(uint addr)) |
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#endif |
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mtsdram0( mem_sdtr1 , sdram0_tr ); |
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/* SDRAM have a power on delay, 500 micro should do */ |
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/* SDRAM have a power on delay, 500 micro should do */ |
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udelay(500); |
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sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; |
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if (ecc_on) |
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@ -464,172 +464,172 @@ int spd_read(uint addr) |
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return 0; |
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} |
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#else /* CONFIG_440 */ |
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#else /* CONFIG_440 */ |
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/*-----------------------------------------------------------------------------
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| Memory Controller Options 0 |
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+-----------------------------------------------------------------------------*/ |
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#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */ |
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#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */ |
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#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */ |
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#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */ |
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#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */ |
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#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */ |
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#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */ |
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#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */ |
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#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */ |
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#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */ |
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#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */ |
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#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */ |
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#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */ |
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#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */ |
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#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */ |
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#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */ |
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#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */ |
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#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */ |
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#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */ |
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#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */ |
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#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */ |
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#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */ |
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#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */ |
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#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */ |
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/*-----------------------------------------------------------------------------
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| Memory Controller Options 1 |
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+-----------------------------------------------------------------------------*/ |
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#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */ |
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#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */ |
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#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */ |
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#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */ |
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/*-----------------------------------------------------------------------------+
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| SDRAM DEVPOT Options |
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+-----------------------------------------------------------------------------*/ |
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#define SDRAM_DEVOPT_DLL 0x80000000 |
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#define SDRAM_DEVOPT_DS 0x40000000 |
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#define SDRAM_DEVOPT_DLL 0x80000000 |
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#define SDRAM_DEVOPT_DS 0x40000000 |
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/*-----------------------------------------------------------------------------+
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| SDRAM MCSTS Options |
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+-----------------------------------------------------------------------------*/ |
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#define SDRAM_MCSTS_MRSC 0x80000000 |
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#define SDRAM_MCSTS_SRMS 0x40000000 |
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#define SDRAM_MCSTS_CIS 0x20000000 |
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#define SDRAM_MCSTS_MRSC 0x80000000 |
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#define SDRAM_MCSTS_SRMS 0x40000000 |
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#define SDRAM_MCSTS_CIS 0x20000000 |
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/*-----------------------------------------------------------------------------
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| SDRAM Refresh Timer Register |
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+-----------------------------------------------------------------------------*/ |
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#define SDRAM_RTR_RINT_MASK 0xFFFF0000 |
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#define SDRAM_RTR_RINT_MASK 0xFFFF0000 |
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#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK) |
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#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) |
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#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) |
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/*-----------------------------------------------------------------------------+
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| SDRAM UABus Base Address Reg |
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+-----------------------------------------------------------------------------*/ |
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#define SDRAM_UABBA_UBBA_MASK 0x0000000F |
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#define SDRAM_UABBA_UBBA_MASK 0x0000000F |
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/*-----------------------------------------------------------------------------+
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| Memory Bank 0-7 configuration |
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+-----------------------------------------------------------------------------*/ |
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#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */ |
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#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */ |
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#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */ |
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#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */ |
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#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */ |
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#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */ |
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#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */ |
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#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */ |
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#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */ |
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#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */ |
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#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */ |
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#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */ |
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#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */ |
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#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */ |
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#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */ |
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#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */ |
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#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */ |
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#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */ |
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#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */ |
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#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */ |
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#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */ |
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#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */ |
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#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */ |
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#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */ |
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#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */ |
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#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */ |
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#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */ |
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#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */ |
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#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */ |
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#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */ |
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/*-----------------------------------------------------------------------------+
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| SDRAM TR0 Options |
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+-----------------------------------------------------------------------------*/ |
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#define SDRAM_TR0_SDWR_MASK 0x80000000 |
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#define SDRAM_TR0_SDWR_2_CLK 0x00000000 |
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#define SDRAM_TR0_SDWR_3_CLK 0x80000000 |
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#define SDRAM_TR0_SDWD_MASK 0x40000000 |
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#define SDRAM_TR0_SDWD_0_CLK 0x00000000 |
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#define SDRAM_TR0_SDWD_1_CLK 0x40000000 |
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#define SDRAM_TR0_SDCL_MASK 0x01800000 |
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#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000 |
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#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000 |
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#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000 |
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#define SDRAM_TR0_SDPA_MASK 0x000C0000 |
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#define SDRAM_TR0_SDPA_2_CLK 0x00040000 |
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#define SDRAM_TR0_SDPA_3_CLK 0x00080000 |
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#define SDRAM_TR0_SDPA_4_CLK 0x000C0000 |
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#define SDRAM_TR0_SDCP_MASK 0x00030000 |
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#define SDRAM_TR0_SDCP_2_CLK 0x00000000 |
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#define SDRAM_TR0_SDCP_3_CLK 0x00010000 |
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#define SDRAM_TR0_SDCP_4_CLK 0x00020000 |
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#define SDRAM_TR0_SDCP_5_CLK 0x00030000 |
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#define SDRAM_TR0_SDLD_MASK 0x0000C000 |
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#define SDRAM_TR0_SDLD_1_CLK 0x00000000 |
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#define SDRAM_TR0_SDLD_2_CLK 0x00004000 |
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#define SDRAM_TR0_SDRA_MASK 0x0000001C |
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#define SDRAM_TR0_SDRA_6_CLK 0x00000000 |
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#define SDRAM_TR0_SDRA_7_CLK 0x00000004 |
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#define SDRAM_TR0_SDRA_8_CLK 0x00000008 |
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#define SDRAM_TR0_SDRA_9_CLK 0x0000000C |
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#define SDRAM_TR0_SDRA_10_CLK 0x00000010 |
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#define SDRAM_TR0_SDRA_11_CLK 0x00000014 |
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#define SDRAM_TR0_SDRA_12_CLK 0x00000018 |
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#define SDRAM_TR0_SDRA_13_CLK 0x0000001C |
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#define SDRAM_TR0_SDRD_MASK 0x00000003 |
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#define SDRAM_TR0_SDRD_2_CLK 0x00000001 |
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#define SDRAM_TR0_SDRD_3_CLK 0x00000002 |
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#define SDRAM_TR0_SDRD_4_CLK 0x00000003 |
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#define SDRAM_TR0_SDWR_MASK 0x80000000 |
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#define SDRAM_TR0_SDWR_2_CLK 0x00000000 |
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#define SDRAM_TR0_SDWR_3_CLK 0x80000000 |
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#define SDRAM_TR0_SDWD_MASK 0x40000000 |
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#define SDRAM_TR0_SDWD_0_CLK 0x00000000 |
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#define SDRAM_TR0_SDWD_1_CLK 0x40000000 |
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#define SDRAM_TR0_SDCL_MASK 0x01800000 |
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#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000 |
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#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000 |
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#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000 |
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#define SDRAM_TR0_SDPA_MASK 0x000C0000 |
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#define SDRAM_TR0_SDPA_2_CLK 0x00040000 |
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#define SDRAM_TR0_SDPA_3_CLK 0x00080000 |
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#define SDRAM_TR0_SDPA_4_CLK 0x000C0000 |
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#define SDRAM_TR0_SDCP_MASK 0x00030000 |
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#define SDRAM_TR0_SDCP_2_CLK 0x00000000 |
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#define SDRAM_TR0_SDCP_3_CLK 0x00010000 |
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#define SDRAM_TR0_SDCP_4_CLK 0x00020000 |
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#define SDRAM_TR0_SDCP_5_CLK 0x00030000 |
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#define SDRAM_TR0_SDLD_MASK 0x0000C000 |
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#define SDRAM_TR0_SDLD_1_CLK 0x00000000 |
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#define SDRAM_TR0_SDLD_2_CLK 0x00004000 |
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#define SDRAM_TR0_SDRA_MASK 0x0000001C |
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#define SDRAM_TR0_SDRA_6_CLK 0x00000000 |
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#define SDRAM_TR0_SDRA_7_CLK 0x00000004 |
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#define SDRAM_TR0_SDRA_8_CLK 0x00000008 |
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#define SDRAM_TR0_SDRA_9_CLK 0x0000000C |
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#define SDRAM_TR0_SDRA_10_CLK 0x00000010 |
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#define SDRAM_TR0_SDRA_11_CLK 0x00000014 |
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#define SDRAM_TR0_SDRA_12_CLK 0x00000018 |
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#define SDRAM_TR0_SDRA_13_CLK 0x0000001C |
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#define SDRAM_TR0_SDRD_MASK 0x00000003 |
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#define SDRAM_TR0_SDRD_2_CLK 0x00000001 |
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#define SDRAM_TR0_SDRD_3_CLK 0x00000002 |
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#define SDRAM_TR0_SDRD_4_CLK 0x00000003 |
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/*-----------------------------------------------------------------------------+
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| SDRAM TR1 Options |
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+-----------------------------------------------------------------------------*/ |
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#define SDRAM_TR1_RDSS_MASK 0xC0000000 |
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#define SDRAM_TR1_RDSS_TR0 0x00000000 |
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#define SDRAM_TR1_RDSS_TR1 0x40000000 |
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#define SDRAM_TR1_RDSS_TR2 0x80000000 |
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#define SDRAM_TR1_RDSS_TR3 0xC0000000 |
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#define SDRAM_TR1_RDSL_MASK 0x00C00000 |
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#define SDRAM_TR1_RDSL_STAGE1 0x00000000 |
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#define SDRAM_TR1_RDSL_STAGE2 0x00400000 |
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#define SDRAM_TR1_RDSL_STAGE3 0x00800000 |
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#define SDRAM_TR1_RDCD_MASK 0x00000800 |
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#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000 |
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#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800 |
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#define SDRAM_TR1_RDCT_MASK 0x000001FF |
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#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK) |
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#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0) |
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#define SDRAM_TR1_RDCT_MIN 0x00000000 |
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#define SDRAM_TR1_RDCT_MAX 0x000001FF |
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#define SDRAM_TR1_RDSS_MASK 0xC0000000 |
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#define SDRAM_TR1_RDSS_TR0 0x00000000 |
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#define SDRAM_TR1_RDSS_TR1 0x40000000 |
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#define SDRAM_TR1_RDSS_TR2 0x80000000 |
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#define SDRAM_TR1_RDSS_TR3 0xC0000000 |
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#define SDRAM_TR1_RDSL_MASK 0x00C00000 |
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#define SDRAM_TR1_RDSL_STAGE1 0x00000000 |
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#define SDRAM_TR1_RDSL_STAGE2 0x00400000 |
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#define SDRAM_TR1_RDSL_STAGE3 0x00800000 |
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#define SDRAM_TR1_RDCD_MASK 0x00000800 |
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#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000 |
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#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800 |
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#define SDRAM_TR1_RDCT_MASK 0x000001FF |
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#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK) |
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#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0) |
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#define SDRAM_TR1_RDCT_MIN 0x00000000 |
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#define SDRAM_TR1_RDCT_MAX 0x000001FF |
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/*-----------------------------------------------------------------------------+
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| SDRAM WDDCTR Options |
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+-----------------------------------------------------------------------------*/ |
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#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000 |
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#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000 |
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#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000 |
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#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000 |
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#define SDRAM_WDDCTR_DCD_MASK 0x000001FF |
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#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000 |
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#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000 |
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#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000 |
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#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000 |
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#define SDRAM_WDDCTR_DCD_MASK 0x000001FF |
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/*-----------------------------------------------------------------------------+
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| SDRAM CLKTR Options |
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+-----------------------------------------------------------------------------*/ |
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#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 |
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#define SDRAM_CLKTR_CLKP_0DEG 0x00000000 |
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#define SDRAM_CLKTR_CLKP_90DEG 0x40000000 |
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#define SDRAM_CLKTR_CLKP_180DEG 0x80000000 |
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#define SDRAM_CLKTR_DCDT_MASK 0x000001FF |
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#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 |
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#define SDRAM_CLKTR_CLKP_0DEG 0x00000000 |
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#define SDRAM_CLKTR_CLKP_90DEG 0x40000000 |
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#define SDRAM_CLKTR_CLKP_180DEG 0x80000000 |
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#define SDRAM_CLKTR_DCDT_MASK 0x000001FF |
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/*-----------------------------------------------------------------------------+
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| SDRAM DLYCAL Options |
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+-----------------------------------------------------------------------------*/ |
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#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC |
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#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) |
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#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) |
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#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC |
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#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) |
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#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) |
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|
/*-----------------------------------------------------------------------------+
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|
|
| General Definition |
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|
+-----------------------------------------------------------------------------*/ |
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#define DEFAULT_SPD_ADDR1 0x53 |
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#define DEFAULT_SPD_ADDR2 0x52 |
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#define MAXBANKS 4 /* at most 4 dimm banks */ |
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#define MAX_SPD_BYTES 256 |
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#define NUMHALFCYCLES 4 |
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#define NUMMEMTESTS 8 |
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#define NUMMEMWORDS 8 |
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#define MAXBXCR 4 |
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#define TRUE 1 |
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#define FALSE 0 |
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#define DEFAULT_SPD_ADDR1 0x53 |
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#define DEFAULT_SPD_ADDR2 0x52 |
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#define MAXBANKS 4 /* at most 4 dimm banks */ |
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#define MAX_SPD_BYTES 256 |
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#define NUMHALFCYCLES 4 |
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#define NUMMEMTESTS 8 |
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#define NUMMEMWORDS 8 |
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#define MAXBXCR 4 |
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#define TRUE 1 |
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#define FALSE 0 |
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const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { |
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{0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, |
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@ -666,37 +666,37 @@ unsigned char spd_read(uchar chip, uint addr); |
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void get_spd_info(unsigned long* dimm_populated, |
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unsigned char* iic0_dimm_addr, |
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unsigned long num_dimm_banks); |
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unsigned long num_dimm_banks); |
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void check_mem_type |
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(unsigned long* dimm_populated, |
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unsigned char* iic0_dimm_addr, |
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unsigned long num_dimm_banks); |
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unsigned long num_dimm_banks); |
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void check_volt_type |
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(unsigned long* dimm_populated, |
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unsigned char* iic0_dimm_addr, |
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unsigned long num_dimm_banks); |
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unsigned long num_dimm_banks); |
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void program_cfg0(unsigned long* dimm_populated, |
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unsigned char* iic0_dimm_addr, |
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unsigned long num_dimm_banks); |
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unsigned long num_dimm_banks); |
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void program_cfg1(unsigned long* dimm_populated, |
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unsigned char* iic0_dimm_addr, |
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unsigned long num_dimm_banks); |
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unsigned long num_dimm_banks); |
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void program_rtr (unsigned long* dimm_populated, |
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unsigned char* iic0_dimm_addr, |
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|
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unsigned long num_dimm_banks); |
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unsigned long num_dimm_banks); |
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void program_tr0 (unsigned long* dimm_populated, |
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unsigned char* iic0_dimm_addr, |
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unsigned long num_dimm_banks); |
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unsigned long num_dimm_banks); |
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void program_tr1 (void); |
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void program_ecc (unsigned long num_bytes); |
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void program_ecc (unsigned long num_bytes); |
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unsigned |
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long program_bxcr(unsigned long* dimm_populated, |
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|
@ -719,7 +719,7 @@ long int spd_sdram(void) { |
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unsigned long total_size; |
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unsigned long cfg0; |
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unsigned long mcsts; |
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unsigned long num_dimm_banks; /* on board dimm banks */ |
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unsigned long num_dimm_banks; /* on board dimm banks */ |
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num_dimm_banks = sizeof(iic0_dimm_addr); |
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|
@ -841,7 +841,7 @@ unsigned char spd_read(uchar chip, uint addr) |
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void get_spd_info(unsigned long* dimm_populated, |
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unsigned char* iic0_dimm_addr, |
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|
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unsigned long num_dimm_banks) |
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|
unsigned long num_dimm_banks) |
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{ |
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|
unsigned long dimm_num; |
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|
unsigned long dimm_found; |
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|
@ -931,7 +931,7 @@ void check_volt_type(unsigned long* dimm_populated, |
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void program_cfg0(unsigned long* dimm_populated, |
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unsigned char* iic0_dimm_addr, |
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|
|
unsigned long num_dimm_banks) |
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|
unsigned long num_dimm_banks) |
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|
{ |
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|
|
unsigned long dimm_num; |
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|
|
unsigned long cfg0; |
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|
@ -1021,7 +1021,7 @@ void program_cfg0(unsigned long* dimm_populated, |
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void program_cfg1(unsigned long* dimm_populated, |
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|
|
unsigned char* iic0_dimm_addr, |
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|
|
unsigned long num_dimm_banks) |
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|
|
unsigned long num_dimm_banks) |
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|
{ |
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|
|
unsigned long cfg1; |
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|
|
mfsdram(mem_cfg1, cfg1); |
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|
@ -1039,7 +1039,7 @@ void program_cfg1(unsigned long* dimm_populated, |
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void program_rtr (unsigned long* dimm_populated, |
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|
|
unsigned char* iic0_dimm_addr, |
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|
|
unsigned long num_dimm_banks) |
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|
|
unsigned long num_dimm_banks) |
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|
{ |
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|
|
unsigned long dimm_num; |
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|
|
unsigned long bus_period_x_10; |
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|
@ -1100,7 +1100,7 @@ void program_rtr (unsigned long* dimm_populated, |
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void program_tr0 (unsigned long* dimm_populated, |
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|
|
unsigned char* iic0_dimm_addr, |
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|
|
unsigned long num_dimm_banks) |
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|
|
unsigned long num_dimm_banks) |
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|
|
{ |
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|
|
unsigned long dimm_num; |
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|
|
unsigned long tr0; |
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|
|
@ -1159,7 +1159,7 @@ void program_tr0 (unsigned long* dimm_populated, |
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|
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
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|
|
if (dimm_populated[dimm_num] == TRUE) { |
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|
|
wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15); |
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|
|
t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2; |
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|
t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2; |
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|
t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2; |
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|
t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30); |
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cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); |
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@ -1234,7 +1234,7 @@ void program_tr0 (unsigned long* dimm_populated, |
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/*
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* Program SD_WR and SD_WCSBC fields |
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*/ |
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tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */ |
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tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */ |
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switch (wcsbc) { |
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case 0: |
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tr0 |= SDRAM_TR0_SDWD_0_CLK; |
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@ -1623,8 +1623,8 @@ unsigned long program_bxcr(unsigned long* dimm_populated, |
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unsigned long ctrl_bank_num[MAXBANKS]; |
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unsigned long bx_cr_num; |
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unsigned long largest_size_index; |
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unsigned long largest_size; |
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unsigned long current_size_index; |
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unsigned long largest_size; |
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unsigned long current_size_index; |
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BANKPARMS bank_parms[MAXBXCR]; |
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unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */ |
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unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/ |
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@ -1785,7 +1785,7 @@ unsigned long program_bxcr(unsigned long* dimm_populated, |
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return(bank_base_addr); |
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} |
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void program_ecc (unsigned long num_bytes) |
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void program_ecc (unsigned long num_bytes) |
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{ |
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unsigned long bank_base_addr; |
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unsigned long current_address; |
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