trini: Update colibri-imx6ull to use Kconfig for mtdparts related options. Signed-off-by: Tom Rini <trini@konsulko.com>lime2-spi
Tom Rini
6 years ago
commit
f0306a145b
@ -0,0 +1,550 @@ |
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Copyright 2018 Toradex AG |
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*/ |
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|
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/dts-v1/; |
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#include <dt-bindings/gpio/gpio.h> |
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#include "imx6ull.dtsi" |
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|
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/ { |
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model = "Toradex Colibri iMX6ULL"; |
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compatible = "toradex,imx6ull-colibri", "fsl,imx6ull"; |
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|
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chosen { |
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stdout-path = &uart1; |
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}; |
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|
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reg_module_3v3: regulator-module-3v3 { |
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compatible = "regulator-fixed"; |
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regulator-always-on; |
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regulator-name = "+V3.3"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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}; |
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|
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reg_module_3v3_avdd: regulator-module-3v3-avdd { |
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compatible = "regulator-fixed"; |
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regulator-always-on; |
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regulator-name = "+V3.3_AVDD_AUDIO"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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}; |
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|
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reg_sd1_vmmc: regulator-sd1-vmmc { |
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compatible = "regulator-gpio"; |
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gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_snvs_reg_sd>; |
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regulator-always-on; |
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regulator-name = "+V3.3_1.8_SD"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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states = <1800000 0x1 3300000 0x0>; |
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vin-supply = <®_module_3v3>; |
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}; |
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}; |
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|
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&adc1 { |
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num-channels = <10>; |
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vref-supply = <®_module_3v3_avdd>; |
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}; |
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|
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/* Colibri SPI */ |
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&ecspi1 { |
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cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; |
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}; |
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|
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&fec2 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_enet2>; |
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phy-mode = "rmii"; |
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phy-handle = <ðphy1>; |
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status = "okay"; |
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|
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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|
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ethphy1: ethernet-phy@2 { |
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compatible = "ethernet-phy-ieee802.3-c22"; |
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max-speed = <100>; |
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reg = <2>; |
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}; |
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}; |
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}; |
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|
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&gpmi { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_gpmi_nand>; |
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nand-on-flash-bbt; |
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nand-ecc-mode = "hw"; |
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nand-ecc-strength = <8>; |
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nand-ecc-step-size = <512>; |
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status = "okay"; |
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}; |
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&i2c1 { |
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pinctrl-names = "default", "gpio"; |
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pinctrl-0 = <&pinctrl_i2c1>; |
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pinctrl-1 = <&pinctrl_i2c1_gpio>; |
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sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; |
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scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; |
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status = "okay"; |
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}; |
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|
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&i2c2 { |
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pinctrl-names = "default", "gpio"; |
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pinctrl-0 = <&pinctrl_i2c2>; |
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pinctrl-1 = <&pinctrl_i2c2_gpio>; |
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sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; |
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scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; |
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status = "okay"; |
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|
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ad7879@2c { |
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compatible = "adi,ad7879-1"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_snvs_ad7879_int>; |
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reg = <0x2c>; |
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interrupt-parent = <&gpio5>; |
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interrupts = <7 IRQ_TYPE_EDGE_FALLING>; |
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touchscreen-max-pressure = <4096>; |
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adi,resistance-plate-x = <120>; |
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adi,first-conversion-delay = /bits/ 8 <3>; |
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adi,acquisition-time = /bits/ 8 <1>; |
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adi,median-filter-size = /bits/ 8 <2>; |
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adi,averaging = /bits/ 8 <1>; |
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adi,conversion-interval = /bits/ 8 <255>; |
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}; |
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}; |
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|
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&lcdif { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_lcdif_dat |
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&pinctrl_lcdif_ctrl>; |
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}; |
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&pwm4 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_pwm4>; |
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#pwm-cells = <3>; |
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}; |
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&pwm5 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_pwm5>; |
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#pwm-cells = <3>; |
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}; |
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&pwm6 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_pwm6>; |
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#pwm-cells = <3>; |
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}; |
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&pwm7 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_pwm7>; |
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#pwm-cells = <3>; |
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}; |
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|
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&sdma { |
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status = "okay"; |
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}; |
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&snvs_pwrkey { |
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status = "disabled"; |
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}; |
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&uart1 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; |
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fsl,uart-has-rtscts; |
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fsl,dte-mode; |
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status = "okay"; |
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}; |
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&uart2 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart2>; |
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fsl,uart-has-rtscts; |
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fsl,dte-mode; |
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}; |
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&uart5 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart5>; |
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fsl,dte-mode; |
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}; |
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&usbotg1 { |
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dr_mode = "otg"; |
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srp-disable; |
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hnp-disable; |
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adp-disable; |
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}; |
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&usbotg2 { |
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dr_mode = "host"; |
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}; |
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&usdhc1 { |
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assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; |
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assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; |
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assigned-clock-rates = <0>, <198000000>; |
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}; |
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&iomuxc { |
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pinctrl_gpio1: gpio1-grp { |
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fsl,pins = < |
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MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */ |
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MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */ |
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MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */ |
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MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */ |
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MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */ |
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MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */ |
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MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */ |
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MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */ |
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MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */ |
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MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */ |
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>; |
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}; |
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|
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pinctrl_gpio2: gpio2-grp { /* Camera */ |
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fsl,pins = < |
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MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */ |
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MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */ |
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MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */ |
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MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */ |
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MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */ |
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>; |
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}; |
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pinctrl_gpio3: gpio3-grp { /* CAN2 */ |
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fsl,pins = < |
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MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */ |
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MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */ |
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>; |
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}; |
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pinctrl_gpio4: gpio4-grp { |
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fsl,pins = < |
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MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */ |
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>; |
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}; |
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pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */ |
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fsl,pins = < |
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MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */ |
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>; |
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}; |
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pinctrl_gpio6: gpio6-grp { /* Wifi pins */ |
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fsl,pins = < |
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MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */ |
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MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */ |
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MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */ |
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MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */ |
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MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */ |
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MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */ |
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MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */ |
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>; |
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}; |
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pinctrl_can_int: canint-grp { |
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fsl,pins = < |
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MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 /* SODIMM 73 */ |
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>; |
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}; |
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pinctrl_enet2: enet2-grp { |
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fsl,pins = < |
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 |
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 |
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 |
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 |
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 |
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 |
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MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 |
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 |
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 |
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 |
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>; |
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}; |
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pinctrl_ecspi1_cs: ecspi1-cs-grp { |
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fsl,pins = < |
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MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0 |
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>; |
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}; |
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pinctrl_ecspi1: ecspi1-grp { |
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fsl,pins = < |
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MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 |
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MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 |
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MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 |
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>; |
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}; |
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pinctrl_flexcan2: flexcan2-grp { |
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fsl,pins = < |
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MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 |
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MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 |
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>; |
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}; |
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pinctrl_gpio_bl_on: gpio-bl-on-grp { |
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fsl,pins = < |
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MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0 |
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>; |
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}; |
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pinctrl_gpmi_nand: gpmi-nand-grp { |
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fsl,pins = < |
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MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 |
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MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 |
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MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 |
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MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 |
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MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 |
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MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 |
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MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 |
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MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 |
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MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 |
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MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 |
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MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 |
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MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 |
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MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 |
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MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 |
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>; |
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}; |
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pinctrl_i2c1: i2c1-grp { |
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fsl,pins = < |
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MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 |
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MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 |
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>; |
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}; |
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|
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pinctrl_i2c1_gpio: i2c1-gpio-grp { |
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fsl,pins = < |
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MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 |
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MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 |
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>; |
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}; |
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pinctrl_i2c2: i2c2-grp { |
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fsl,pins = < |
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MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 |
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MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 |
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>; |
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}; |
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pinctrl_i2c2_gpio: i2c2-gpio-grp { |
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fsl,pins = < |
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MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 |
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MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 |
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>; |
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}; |
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|
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pinctrl_lcdif_dat: lcdif-dat-grp { |
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fsl,pins = < |
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MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 |
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MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 |
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MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 |
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MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 |
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MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 |
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MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 |
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MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 |
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MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 |
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MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 |
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MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 |
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MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 |
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MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 |
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MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 |
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MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 |
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MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 |
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MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 |
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MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 |
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MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 |
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>; |
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}; |
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|
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pinctrl_lcdif_ctrl: lcdif-ctrl-grp { |
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fsl,pins = < |
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MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 |
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MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 |
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MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 |
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MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 |
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>; |
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}; |
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|
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pinctrl_pwm4: pwm4-grp { |
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fsl,pins = < |
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MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 |
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>; |
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}; |
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|
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pinctrl_pwm5: pwm5-grp { |
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fsl,pins = < |
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MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 |
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>; |
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}; |
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|
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pinctrl_pwm6: pwm6-grp { |
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fsl,pins = < |
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MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 |
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>; |
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}; |
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|
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pinctrl_pwm7: pwm7-grp { |
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fsl,pins = < |
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MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 |
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>; |
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}; |
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|
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pinctrl_uart1: uart1-grp { |
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fsl,pins = < |
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MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 |
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MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 |
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MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 |
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MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 |
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>; |
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}; |
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|
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pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ |
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fsl,pins = < |
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MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */ |
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MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */ |
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MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */ |
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MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */ |
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>; |
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}; |
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|
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pinctrl_uart2: uart2-grp { |
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fsl,pins = < |
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MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 |
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MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 |
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MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 |
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MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 |
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>; |
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}; |
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pinctrl_uart5: uart5-grp { |
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fsl,pins = < |
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MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 |
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MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 |
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>; |
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}; |
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|
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pinctrl_usbh_reg: gpio-usbh-reg { |
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fsl,pins = < |
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MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */ |
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>; |
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}; |
||||
|
||||
pinctrl_usdhc1: usdhc1-grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 |
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 |
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 |
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 |
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 |
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 |
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 |
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 |
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 |
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 |
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 |
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 |
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 |
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 |
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 |
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_usdhc2: usdhc2-grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 |
||||
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 |
||||
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 |
||||
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 |
||||
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 |
||||
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059 |
||||
>; |
||||
}; |
||||
}; |
||||
|
||||
&iomuxc_snvs { |
||||
pinctrl_snvs_gpio1: snvs-gpio1-grp { |
||||
fsl,pins = < |
||||
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */ |
||||
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */ |
||||
MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */ |
||||
MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */ |
||||
MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */ |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */ |
||||
fsl,pins = < |
||||
MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */ |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ |
||||
fsl,pins = < |
||||
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */ |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_snvs_ad7879_int: snvs-ad7879-int { /* TOUCH Interrupt */ |
||||
fsl,pins = < |
||||
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_snvs_reg_sd: snvs-reg-sd-grp { |
||||
fsl,pins = < |
||||
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_snvs_usbc_det: snvs-usbc-det-grp { |
||||
fsl,pins = < |
||||
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { |
||||
fsl,pins = < |
||||
MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { |
||||
fsl,pins = < |
||||
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */ |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { |
||||
fsl,pins = < |
||||
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 |
||||
>; |
||||
}; |
||||
}; |
||||
|
||||
@ -1,60 +0,0 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0+ */ |
||||
/* |
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc. |
||||
* Copyright 2017 NXP |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <linux/linkage.h> |
||||
|
||||
#include <asm/armv7.h> |
||||
#include <asm/arch-armv7/generictimer.h> |
||||
#include <asm/psci.h> |
||||
|
||||
.pushsection ._secure.text, "ax" |
||||
|
||||
.arch_extension sec
|
||||
|
||||
.globl psci_cpu_on
|
||||
psci_cpu_on: |
||||
push {r4, r5, lr} |
||||
|
||||
mov r4, r0 |
||||
mov r5, r1 |
||||
mov r0, r1 |
||||
mov r1, r2 |
||||
mov r2, r3 |
||||
bl psci_save |
||||
|
||||
mov r0, r4 |
||||
mov r1, r5 |
||||
ldr r2, =psci_cpu_entry |
||||
bl imx_cpu_on |
||||
|
||||
pop {r4, r5, pc} |
||||
|
||||
.globl psci_cpu_off
|
||||
psci_cpu_off: |
||||
|
||||
bl psci_cpu_off_common |
||||
bl psci_get_cpu_id |
||||
bl imx_cpu_off |
||||
|
||||
1: wfi |
||||
b 1b |
||||
|
||||
.globl psci_system_reset
|
||||
psci_system_reset: |
||||
bl imx_system_reset |
||||
|
||||
2: wfi |
||||
b 2b |
||||
|
||||
.globl psci_system_off
|
||||
psci_system_off: |
||||
bl imx_system_off |
||||
|
||||
3: wfi |
||||
b 3b |
||||
|
||||
.popsection |
||||
@ -1,111 +0,0 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0+ */ |
||||
/* |
||||
* Copyright (C) 2017 Logic PD, Inc. |
||||
* Adam Ford <aford173@gmail.com> |
||||
* |
||||
* Refer doc/README.imximage for more details about how-to configure |
||||
* and create imximage boot image |
||||
* |
||||
* The syntax is taken as close as possible with the kwbimage |
||||
*/ |
||||
|
||||
#include <asm/mach-imx/imximage.cfg> |
||||
|
||||
/* image version */ |
||||
IMAGE_VERSION 2 |
||||
|
||||
BOOT_OFFSET FLASH_OFFSET_STANDARD |
||||
|
||||
/* |
||||
* Device Configuration Data (DCD) |
||||
* |
||||
* Each entry must have the format: |
||||
* Addr-type Address Value |
||||
* |
||||
* where: |
||||
* Addr-type register length (1,2 or 4 bytes) |
||||
* Address absolute address of the register |
||||
* value value to be stored in the register |
||||
*/ |
||||
|
||||
#define __ASSEMBLY__ |
||||
#include <config.h> |
||||
#include "asm/arch-mx6/mx6-ddr.h" |
||||
#include "asm/arch-mx6/iomux.h" |
||||
#include "asm/arch-mx6/crm_regs.h" |
||||
|
||||
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 |
||||
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 |
||||
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 |
||||
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 |
||||
DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 |
||||
DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 |
||||
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 |
||||
DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 |
||||
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 |
||||
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 |
||||
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 |
||||
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 |
||||
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 |
||||
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 |
||||
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 |
||||
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 |
||||
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 |
||||
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 |
||||
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 |
||||
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 |
||||
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 |
||||
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 |
||||
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 |
||||
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 |
||||
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 |
||||
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 |
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 |
||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 |
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A |
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B |
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338 |
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C |
||||
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C |
||||
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038 |
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 |
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 |
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 |
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 |
||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 |
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 |
||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 |
||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955 |
||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 |
||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB |
||||
DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740 |
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 |
||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 |
||||
DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023 |
||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 |
||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000 |
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032 |
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 |
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031 |
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030 |
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 |
||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 |
||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 |
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 |
||||
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 |
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 |
||||
|
||||
/* set the default clock gate to save power */ |
||||
DATA 4, CCM_CCGR0, 0x00C03F3F |
||||
DATA 4, CCM_CCGR1, 0x0030FC03 |
||||
DATA 4, CCM_CCGR2, 0x0FFFC000 |
||||
DATA 4, CCM_CCGR3, 0x3FF00000 |
||||
DATA 4, CCM_CCGR4, 0xFFFFF300 |
||||
DATA 4, CCM_CCGR5, 0x0F0000F3 |
||||
DATA 4, CCM_CCGR6, 0x00000FFF |
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */ |
||||
DATA 4 MX6_IOMUXC_GPR4 0xF00000CF |
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
||||
DATA 4 MX6_IOMUXC_GPR6 0x007F007F |
||||
DATA 4 MX6_IOMUXC_GPR7 0x007F007F |
||||
@ -1,4 +1,4 @@ |
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
# (C) Copyright 2017 NXP Semiconductors
|
||||
|
||||
obj-y := pico-imx7d.o
|
||||
obj-y := pico-imx7d.o spl.o
|
||||
|
||||
@ -1,97 +0,0 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0+ */ |
||||
/* |
||||
* Copyright (C) 2017 Freescale Semiconductor, Inc. |
||||
* |
||||
* Refer docs/README.imxmage for more details about how-to configure |
||||
* and create imximage boot image |
||||
* |
||||
* The syntax is taken as close as possible with the kwbimage |
||||
*/ |
||||
|
||||
#define __ASSEMBLY__ |
||||
#include <config.h> |
||||
|
||||
/* image version */ |
||||
|
||||
IMAGE_VERSION 2 |
||||
|
||||
BOOT_FROM sd |
||||
|
||||
/* Secure boot support */ |
||||
#ifdef CONFIG_SECURE_BOOT |
||||
CSF CONFIG_CSF_SIZE |
||||
#endif |
||||
|
||||
/* |
||||
* Device Configuration Data (DCD) |
||||
* |
||||
* Each entry must have the format: |
||||
* Addr-type Address Value |
||||
* |
||||
* where: |
||||
* Addr-type register length (1,2 or 4 bytes) |
||||
* Address absolute address of the register |
||||
* value value to be stored in the register |
||||
*/ |
||||
|
||||
DATA 4 0x30340004 0x4F400005 |
||||
/* Clear then set bit30 to ensure exit from DDR retention */ |
||||
DATA 4 0x30360388 0x40000000 |
||||
DATA 4 0x30360384 0x40000000 |
||||
|
||||
DATA 4 0x30391000 0x00000002 |
||||
DATA 4 0x307a0000 0x01040001 |
||||
DATA 4 0x307a01a0 0x80400003 |
||||
DATA 4 0x307a01a4 0x00100020 |
||||
DATA 4 0x307a01a8 0x80100004 |
||||
DATA 4 0x307a0064 0x00400046 |
||||
DATA 4 0x307a0490 0x00000001 |
||||
DATA 4 0x307a00d0 0x00020083 |
||||
DATA 4 0x307a00d4 0x00690000 |
||||
DATA 4 0x307a00dc 0x09300004 |
||||
DATA 4 0x307a00e0 0x04080000 |
||||
DATA 4 0x307a00e4 0x00100004 |
||||
DATA 4 0x307a00f4 0x0000033f |
||||
DATA 4 0x307a0100 0x09081109 |
||||
DATA 4 0x307a0104 0x0007020d |
||||
DATA 4 0x307a0108 0x03040407 |
||||
DATA 4 0x307a010c 0x00002006 |
||||
DATA 4 0x307a0110 0x04020205 |
||||
DATA 4 0x307a0114 0x03030202 |
||||
DATA 4 0x307a0120 0x00000803 |
||||
DATA 4 0x307a0180 0x00800020 |
||||
DATA 4 0x307a0184 0x02000100 |
||||
DATA 4 0x307a0190 0x02098204 |
||||
DATA 4 0x307a0194 0x00030303 |
||||
DATA 4 0x307a0200 0x00000016 |
||||
DATA 4 0x307a0204 0x00080808 |
||||
DATA 4 0x307a0210 0x00000f0f |
||||
DATA 4 0x307a0214 0x07070707 |
||||
DATA 4 0x307a0218 0x0f070707 |
||||
DATA 4 0x307a0240 0x06000604 |
||||
DATA 4 0x307a0244 0x00000001 |
||||
DATA 4 0x30391000 0x00000000 |
||||
DATA 4 0x30790000 0x17420f40 |
||||
DATA 4 0x30790004 0x10210100 |
||||
DATA 4 0x30790010 0x00060807 |
||||
DATA 4 0x307900b0 0x1010007e |
||||
DATA 4 0x3079009c 0x00000b24 |
||||
DATA 4 0x30790020 0x08080808 |
||||
DATA 4 0x30790030 0x08080808 |
||||
DATA 4 0x30790050 0x01000010 |
||||
DATA 4 0x30790050 0x00000010 |
||||
|
||||
DATA 4 0x307900c0 0x0e407304 |
||||
DATA 4 0x307900c0 0x0e447304 |
||||
DATA 4 0x307900c0 0x0e447306 |
||||
|
||||
CHECK_BITS_SET 4 0x307900c4 0x1 |
||||
|
||||
DATA 4 0x307900c0 0x0e407304 |
||||
|
||||
DATA 4 0x30384130 0x00000000 |
||||
DATA 4 0x30340020 0x00000178 |
||||
DATA 4 0x30384130 0x00000002 |
||||
DATA 4 0x30790018 0x0000000f |
||||
|
||||
CHECK_BITS_SET 4 0x307a0004 0x1 |
||||
@ -0,0 +1,122 @@ |
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Technexion Ltd. |
||||
* |
||||
* Author: Richard Hu <richard.hu@technexion.com> |
||||
*/ |
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/arch-mx7/mx7-ddr.h> |
||||
#include <asm/gpio.h> |
||||
#include <spl.h> |
||||
|
||||
#if defined(CONFIG_SPL_BUILD) |
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT |
||||
int spl_start_uboot(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
static struct ddrc ddrc_regs_val = { |
||||
.mstr = 0x01040001, |
||||
.rfshtmg = 0x00400046, |
||||
.init1 = 0x00690000, |
||||
.init0 = 0x00020083, |
||||
.init3 = 0x09300004, |
||||
.init4 = 0x04080000, |
||||
.init5 = 0x00100004, |
||||
.rankctl = 0x0000033F, |
||||
.dramtmg0 = 0x09081109, |
||||
.dramtmg1 = 0x0007020d, |
||||
.dramtmg2 = 0x03040407, |
||||
.dramtmg3 = 0x00002006, |
||||
.dramtmg4 = 0x04020205, |
||||
.dramtmg5 = 0x03030202, |
||||
.dramtmg8 = 0x00000803, |
||||
.zqctl0 = 0x00800020, |
||||
.dfitmg0 = 0x02098204, |
||||
.dfitmg1 = 0x00030303, |
||||
.dfiupd0 = 0x80400003, |
||||
.dfiupd1 = 0x00100020, |
||||
.dfiupd2 = 0x80100004, |
||||
.addrmap4 = 0x00000F0F, |
||||
.odtcfg = 0x06000604, |
||||
.odtmap = 0x00000001, |
||||
.rfshtmg = 0x00400046, |
||||
.dramtmg0 = 0x09081109, |
||||
.addrmap0 = 0x0000001f, |
||||
.addrmap1 = 0x00080808, |
||||
.addrmap4 = 0x00000f0f, |
||||
.addrmap5 = 0x07070707, |
||||
.addrmap6 = 0x0f0f0707, |
||||
}; |
||||
|
||||
static struct ddrc_mp ddrc_mp_val = { |
||||
.pctrl_0 = 0x00000001, |
||||
}; |
||||
|
||||
static struct ddr_phy ddr_phy_regs_val = { |
||||
.phy_con0 = 0x17420f40, |
||||
.phy_con1 = 0x10210100, |
||||
.phy_con4 = 0x00060807, |
||||
.mdll_con0 = 0x1010007e, |
||||
.drvds_con0 = 0x00000d6e, |
||||
.cmd_sdll_con0 = 0x00000010, |
||||
.offset_lp_con0 = 0x0000000f, |
||||
.offset_rd_con0 = 0x08080808, |
||||
.offset_wr_con0 = 0x08080808, |
||||
}; |
||||
|
||||
static struct mx7_calibration calib_param = { |
||||
.num_val = 5, |
||||
.values = { |
||||
0x0E407304, |
||||
0x0E447304, |
||||
0x0E447306, |
||||
0x0E447304, |
||||
0x0E447304, |
||||
}, |
||||
}; |
||||
|
||||
static void gpr_init(void) |
||||
{ |
||||
struct iomuxc_gpr_base_regs *gpr_regs = |
||||
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; |
||||
writel(0x4F400005, &gpr_regs->gpr[1]); |
||||
} |
||||
|
||||
static bool is_1g(void) |
||||
{ |
||||
gpio_direction_input(IMX_GPIO_NR(1, 12)); |
||||
return !gpio_get_value(IMX_GPIO_NR(1, 12)); |
||||
} |
||||
|
||||
static void ddr_init(void) |
||||
{ |
||||
if (is_1g()) |
||||
ddrc_regs_val.addrmap6 = 0x0f070707; |
||||
|
||||
mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val, |
||||
&calib_param); |
||||
} |
||||
|
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
arch_cpu_init(); |
||||
gpr_init(); |
||||
board_early_init_f(); |
||||
timer_init(); |
||||
preloader_console_init(); |
||||
ddr_init(); |
||||
memset(__bss_start, 0, __bss_end - __bss_start); |
||||
board_init_r(NULL, 0); |
||||
} |
||||
|
||||
void reset_cpu(ulong addr) |
||||
{ |
||||
} |
||||
#endif |
||||
@ -0,0 +1,29 @@ |
||||
if TARGET_COLIBRI_IMX6ULL |
||||
|
||||
config SYS_BOARD |
||||
default "colibri-imx6ull" |
||||
|
||||
config SYS_VENDOR |
||||
default "toradex" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "colibri-imx6ull" |
||||
|
||||
config TDX_CFG_BLOCK |
||||
default y |
||||
|
||||
config TDX_HAVE_NAND |
||||
default y |
||||
|
||||
config TDX_CFG_BLOCK_OFFSET |
||||
default "2048" |
||||
|
||||
config TDX_CFG_BLOCK_OFFSET2 |
||||
default "133120" |
||||
|
||||
config TDX_CFG_BLOCK_2ND_ETHADDR |
||||
default y |
||||
|
||||
source "board/toradex/common/Kconfig" |
||||
|
||||
endif |
||||
@ -0,0 +1,10 @@ |
||||
Colibri iMX6ULL |
||||
M: Stefan Agner <stefan.agner@toradex.com> |
||||
M: Toradex ARM Support <support.arm@toradex.com> |
||||
W: http://developer.toradex.com/software/linux/linux-software |
||||
W: https://www.toradex.com/community |
||||
S: Maintained |
||||
F: arch/arm/dts/imx6ull-colibri.dts |
||||
F: board/toradex/colibri-imx6ull/ |
||||
F: configs/colibri-imx6ull_defconfig |
||||
F: include/configs/colibri-imx6ull.h |
||||
@ -0,0 +1,4 @@ |
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
# Copyright (C) 2018 Toradex AG
|
||||
|
||||
obj-y := colibri-imx6ull.o
|
||||
@ -0,0 +1,408 @@ |
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Toradex AG |
||||
*/ |
||||
#include <common.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch-mx6/clock.h> |
||||
#include <asm/arch-mx6/imx-regs.h> |
||||
#include <asm/arch-mx6/mx6ull_pins.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/mach-imx/boot_mode.h> |
||||
#include <asm/mach-imx/iomux-v3.h> |
||||
#include <asm/io.h> |
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <dm/platform_data/serial_mxc.h> |
||||
#include <fdt_support.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <imx_thermal.h> |
||||
#include <jffs2/load_kernel.h> |
||||
#include <linux/sizes.h> |
||||
#include <mmc.h> |
||||
#include <miiphy.h> |
||||
#include <mtd_node.h> |
||||
#include <netdev.h> |
||||
#include <usb.h> |
||||
#include <usb/ehci-ci.h> |
||||
#include "../common/tdx-common.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
||||
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
||||
#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_40ohm) |
||||
|
||||
#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm) |
||||
|
||||
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ |
||||
PAD_CTL_DSE_48ohm) |
||||
|
||||
#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) |
||||
|
||||
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP) |
||||
|
||||
#define USB_CDET_GPIO IMX_GPIO_NR(7, 14) |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static iomux_v3_cfg_t const uart1_pads[] = { |
||||
MX6_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_UART1_RTS_B__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_UART1_CTS_B__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
}; |
||||
|
||||
#ifdef CONFIG_FSL_ESDHC |
||||
static iomux_v3_cfg_t const usdhc1_pads[] = { |
||||
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
|
||||
MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
#endif |
||||
|
||||
static iomux_v3_cfg_t const usb_cdet_pads[] = { |
||||
MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
|
||||
#ifdef CONFIG_NAND_MXS |
||||
static iomux_v3_cfg_t const gpmi_pads[] = { |
||||
MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), |
||||
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), |
||||
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), |
||||
MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), |
||||
MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), |
||||
MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), |
||||
MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), |
||||
}; |
||||
|
||||
static void setup_gpmi_nand(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); |
||||
|
||||
setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | |
||||
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_VIDEO_MXS |
||||
static iomux_v3_cfg_t const lcd_pads[] = { |
||||
MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
||||
}; |
||||
|
||||
static iomux_v3_cfg_t const backlight_pads[] = { |
||||
/* Backlight On */ |
||||
MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
/* Backlight PWM<A> (multiplexed pin) */ |
||||
MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
|
||||
#define GPIO_BL_ON IMX_GPIO_NR(1, 11) |
||||
#define GPIO_PWM_A IMX_GPIO_NR(4, 11) |
||||
|
||||
static int setup_lcd(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); |
||||
|
||||
/* Set BL_ON */ |
||||
gpio_request(GPIO_BL_ON, "BL_ON"); |
||||
gpio_direction_output(GPIO_BL_ON, 1); |
||||
|
||||
/* Set PWM<A> to full brightness (assuming inversed polarity) */ |
||||
gpio_request(GPIO_PWM_A, "PWM<A>"); |
||||
gpio_direction_output(GPIO_PWM_A, 0); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FEC_MXC |
||||
static iomux_v3_cfg_t const fec2_pads[] = { |
||||
MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, |
||||
MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), |
||||
MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), |
||||
MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
||||
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
||||
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
||||
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
||||
MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
}; |
||||
|
||||
static void setup_iomux_fec(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); |
||||
} |
||||
#endif |
||||
|
||||
static void setup_iomux_uart(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
||||
} |
||||
|
||||
#ifdef CONFIG_FSL_ESDHC |
||||
|
||||
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) |
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[] = { |
||||
{USDHC1_BASE_ADDR, 0, 4}, |
||||
}; |
||||
|
||||
int board_mmc_getcd(struct mmc *mmc) |
||||
{ |
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
||||
int ret = 0; |
||||
|
||||
switch (cfg->esdhc_base) { |
||||
case USDHC1_BASE_ADDR: |
||||
ret = !gpio_get_value(USDHC1_CD_GPIO); |
||||
break; |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
int i, ret; |
||||
|
||||
/* USDHC1 is mmc0 */ |
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
||||
switch (i) { |
||||
case 0: |
||||
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, |
||||
ARRAY_SIZE(usdhc1_pads)); |
||||
gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); |
||||
gpio_direction_input(USDHC1_CD_GPIO); |
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
||||
break; |
||||
default: |
||||
printf("Warning: you configured more USDHC controllers" |
||||
"(%d) than supported by the board\n", i + 1); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
||||
if (ret) |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FEC_MXC |
||||
|
||||
static int setup_fec(void) |
||||
{ |
||||
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; |
||||
int ret; |
||||
|
||||
setup_iomux_fec(); |
||||
|
||||
/* provide the PHY clock from the i.MX 6 */ |
||||
ret = enable_fec_anatop_clock(1, ENET_50MHZ); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
/* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */ |
||||
clrsetbits_le32(&iomuxc_regs->gpr[1], |
||||
IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK, |
||||
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_phy_config(struct phy_device *phydev) |
||||
{ |
||||
if (phydev->drv->config) |
||||
phydev->drv->config(phydev); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
setup_iomux_uart(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* address of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
||||
|
||||
#ifdef CONFIG_FEC_MXC |
||||
setup_fec(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_NAND_MXS |
||||
setup_gpmi_nand(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_VIDEO_MXS |
||||
setup_lcd(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6 |
||||
imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); |
||||
gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_CMD_BMODE |
||||
/* TODO */ |
||||
static const struct boot_mode board_boot_modes[] = { |
||||
/* 4 bit bus width */ |
||||
{"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)}, |
||||
{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, |
||||
{NULL, 0}, |
||||
}; |
||||
#endif |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
int minc, maxc; |
||||
|
||||
if (get_cpu_temp_grade(&minc, &maxc) != TEMP_COMMERCIAL) |
||||
env_set("variant", "-wifi"); |
||||
|
||||
#ifdef CONFIG_CMD_BMODE |
||||
add_board_boot_modes(board_boot_modes); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_CMD_USB_SDP |
||||
if (is_boot_from_usb()) { |
||||
printf("Serial Downloader recovery mode, using sdp command\n"); |
||||
env_set("bootdelay", "0"); |
||||
env_set("bootcmd", "sdp 0"); |
||||
} |
||||
#endif /* CONFIG_CMD_USB_SDP */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
printf("Model: Toradex Colibri iMX6ULL\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
#if defined(CONFIG_FDT_FIXUP_PARTITIONS) |
||||
static struct node_info nodes[] = { |
||||
{ "fsl,imx6ull-gpmi-nand", MTD_DEV_TYPE_NAND, }, |
||||
{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, |
||||
}; |
||||
|
||||
/* Update partition nodes using info from mtdparts env var */ |
||||
puts(" Updating MTD partitions...\n"); |
||||
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); |
||||
#endif |
||||
|
||||
return ft_common_board_setup(blob, bd); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6 |
||||
static iomux_v3_cfg_t const usb_otg2_pads[] = { |
||||
MX6_PAD_GPIO1_IO02__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
|
||||
int board_ehci_hcd_init(int port) |
||||
{ |
||||
switch (port) { |
||||
case 0: |
||||
break; |
||||
case 1: |
||||
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, |
||||
ARRAY_SIZE(usb_otg2_pads)); |
||||
break; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
int board_usb_phy_mode(int port) |
||||
{ |
||||
switch (port) { |
||||
case 0: |
||||
if (gpio_get_value(USB_CDET_GPIO)) |
||||
return USB_INIT_DEVICE; |
||||
else |
||||
return USB_INIT_HOST; |
||||
case 1: |
||||
default: |
||||
return USB_INIT_HOST; |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
static struct mxc_serial_platdata mxc_serial_plat = { |
||||
.reg = (struct mxc_uart *)UART1_BASE, |
||||
.use_dte = 1, |
||||
}; |
||||
|
||||
U_BOOT_DEVICE(mxc_serial) = { |
||||
.name = "serial_mxc", |
||||
.platdata = &mxc_serial_plat, |
||||
}; |
||||
@ -0,0 +1,106 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0+ */ |
||||
/* |
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc. |
||||
* Copyright (C) 2018 Toradex AG |
||||
* |
||||
* Refer doc/README.imximage for more details about how-to configure |
||||
* and create imximage boot image |
||||
* |
||||
* The syntax is taken as close as possible with the kwbimage |
||||
*/ |
||||
|
||||
#define __ASSEMBLY__ |
||||
#include <config.h> |
||||
|
||||
/* image version */ |
||||
|
||||
IMAGE_VERSION 2 |
||||
|
||||
/* |
||||
* Boot Device : nand |
||||
*/ |
||||
|
||||
BOOT_FROM nand |
||||
|
||||
/* |
||||
* Secure boot support |
||||
*/ |
||||
#ifdef CONFIG_SECURE_BOOT |
||||
CSF CONFIG_CSF_SIZE |
||||
#endif |
||||
|
||||
/* |
||||
* Device Configuration Data (DCD) |
||||
* |
||||
* Each entry must have the format: |
||||
* Addr-type Address Value |
||||
* |
||||
* where: |
||||
* Addr-type register length (1,2 or 4 bytes) |
||||
* Address absolute address of the register |
||||
* value value to be stored in the register |
||||
*/ |
||||
|
||||
/* Enable all clocks */ |
||||
DATA 4 0x020c4068 0xffffffff |
||||
DATA 4 0x020c406c 0xffffffff |
||||
DATA 4 0x020c4070 0xffffffff |
||||
DATA 4 0x020c4074 0xffffffff |
||||
DATA 4 0x020c4078 0xffffffff |
||||
DATA 4 0x020c407c 0xffffffff |
||||
DATA 4 0x020c4080 0xffffffff |
||||
|
||||
DATA 4 0x020E04B4 0x000C0000 |
||||
DATA 4 0x020E04AC 0x00000000 |
||||
DATA 4 0x020E027C 0x00000030 |
||||
DATA 4 0x020E0250 0x00000030 |
||||
DATA 4 0x020E024C 0x00000030 |
||||
DATA 4 0x020E0490 0x00000030 |
||||
DATA 4 0x020E0288 0x000C0030 |
||||
DATA 4 0x020E0270 0x00000000 |
||||
DATA 4 0x020E0260 0x00000030 |
||||
DATA 4 0x020E0264 0x00000030 |
||||
DATA 4 0x020E04A0 0x00000030 |
||||
DATA 4 0x020E0494 0x00020000 |
||||
DATA 4 0x020E0280 0x00000030 |
||||
DATA 4 0x020E0284 0x00000030 |
||||
DATA 4 0x020E04B0 0x00020000 |
||||
DATA 4 0x020E0498 0x00000030 |
||||
DATA 4 0x020E04A4 0x00000030 |
||||
DATA 4 0x020E0244 0x00000030 |
||||
DATA 4 0x020E0248 0x00000030 |
||||
DATA 4 0x021B001C 0x00008000 |
||||
DATA 4 0x021B0800 0xA1390003 |
||||
DATA 4 0x021B080C 0x00000004 |
||||
DATA 4 0x021B083C 0x41640158 |
||||
DATA 4 0x021B0848 0x40403237 |
||||
DATA 4 0x021B0850 0x40403C33 |
||||
DATA 4 0x021B081C 0x33333333 |
||||
DATA 4 0x021B0820 0x33333333 |
||||
DATA 4 0x021B082C 0xf3333333 |
||||
DATA 4 0x021B0830 0xf3333333 |
||||
DATA 4 0x021B08C0 0x00944009 |
||||
DATA 4 0x021B08b8 0x00000800 |
||||
DATA 4 0x021B0004 0x0002002D |
||||
DATA 4 0x021B0008 0x1B333030 |
||||
DATA 4 0x021B000C 0x676B52F3 |
||||
DATA 4 0x021B0010 0xB66D0B63 |
||||
DATA 4 0x021B0014 0x01FF00DB |
||||
DATA 4 0x021B0018 0x00201740 |
||||
DATA 4 0x021B001C 0x00008000 |
||||
DATA 4 0x021B002C 0x000026D2 |
||||
DATA 4 0x021B0030 0x006B1023 |
||||
DATA 4 0x021B0040 0x0000004F |
||||
DATA 4 0x021B0000 0x84180000 |
||||
DATA 4 0x021B0890 0x00400000 |
||||
DATA 4 0x021B001C 0x02008032 |
||||
DATA 4 0x021B001C 0x00008033 |
||||
DATA 4 0x021B001C 0x00048031 |
||||
DATA 4 0x021B001C 0x15208030 |
||||
DATA 4 0x021B001C 0x04008040 |
||||
DATA 4 0x021B0020 0x00000800 |
||||
DATA 4 0x021B0818 0x00000227 |
||||
DATA 4 0x021B0004 0x0002552D |
||||
DATA 4 0x021B0404 0x00011006 |
||||
DATA 4 0x021B001C 0x00000000 |
||||
|
||||
@ -0,0 +1,78 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_SYS_THUMB_BUILD=y |
||||
# CONFIG_SPL_SYS_THUMB_BUILD is not set |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_SYS_TEXT_BASE=0x87800000 |
||||
CONFIG_TARGET_COLIBRI_IMX6ULL=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri" |
||||
CONFIG_DISTRO_DEFAULTS=y |
||||
CONFIG_FIT=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx6ull/imximage.cfg,MX6ULL,IMX_NAND" |
||||
CONFIG_BOOTDELAY=1 |
||||
# CONFIG_USE_BOOTCOMMAND is not set |
||||
# CONFIG_CONSOLE_MUX is not set |
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y |
||||
CONFIG_VERSION_VARIABLE=y |
||||
# CONFIG_DISPLAY_BOARDINFO is not set |
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y |
||||
CONFIG_BOARD_EARLY_INIT_F=y |
||||
CONFIG_SYS_PROMPT="Colibri iMX6ULL # " |
||||
# CONFIG_CMD_IMI is not set |
||||
# CONFIG_CMD_XIMG is not set |
||||
CONFIG_CMD_ASKENV=y |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_DFU=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_GPT=y |
||||
# CONFIG_RANDOM_UUID is not set |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_NAND_TRIMFFS=y |
||||
CONFIG_CMD_NAND_TORTURE=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_USB_MASS_STORAGE=y |
||||
CONFIG_CMD_BMP=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" |
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:512k(mx6ull-bcb),1536k(u-boot1)ro,1536k(u-boot2)ro,512k(u-boot-env),-(ubi)" |
||||
CONFIG_CMD_UBI=y |
||||
# CONFIG_ISO_PARTITION is not set |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_ENV_IS_IN_NAND=y |
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
||||
CONFIG_DFU_MMC=y |
||||
CONFIG_DFU_NAND=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_DM_I2C=y |
||||
CONFIG_SYS_I2C_MXC=y |
||||
CONFIG_FSL_ESDHC=y |
||||
CONFIG_MTD=y |
||||
CONFIG_NAND=y |
||||
CONFIG_NAND_MXS=y |
||||
CONFIG_NAND_MXS_DT=y |
||||
CONFIG_MTD_UBI_FASTMAP=y |
||||
CONFIG_PHYLIB=y |
||||
CONFIG_PHY_ADDR_ENABLE=y |
||||
CONFIG_PHY_MICREL=y |
||||
CONFIG_PHY_MICREL_KSZ90X1=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_FEC_MXC=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_PINCTRL_IMX6=y |
||||
CONFIG_DM_REGULATOR=y |
||||
# CONFIG_SPL_SERIAL_PRESENT is not set |
||||
CONFIG_DM_SERIAL=y |
||||
CONFIG_MXC_UART=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_USB_GADGET=y |
||||
CONFIG_USB_GADGET_MANUFACTURER="Toradex" |
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 |
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 |
||||
CONFIG_CI_UDC=y |
||||
CONFIG_USB_GADGET_DOWNLOAD=y |
||||
CONFIG_USB_FUNCTION_SDP=y |
||||
CONFIG_VIDEO=y |
||||
CONFIG_OF_LIBFDT_OVERLAY=y |
||||
CONFIG_FDT_FIXUP_PARTITIONS=y |
||||
# CONFIG_EFI_LOADER is not set |
||||
@ -1,40 +1,75 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_SYS_TEXT_BASE=0x17800000 |
||||
CONFIG_SPL_GPIO_SUPPORT=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000 |
||||
CONFIG_TARGET_MX6LOGICPD=y |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 |
||||
CONFIG_SPL=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd" |
||||
CONFIG_DISTRO_DEFAULTS=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg,MX6Q" |
||||
CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" |
||||
CONFIG_BOOTDELAY=3 |
||||
# CONFIG_USE_BOOTCOMMAND is not set |
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y |
||||
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y |
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
||||
CONFIG_SPL_SEPARATE_BSS=y |
||||
CONFIG_SPL_DMA_SUPPORT=y |
||||
CONFIG_SPL_I2C_SUPPORT=y |
||||
CONFIG_SPL_NAND_SUPPORT=y |
||||
CONFIG_SPL_OS_BOOT=y |
||||
CONFIG_SPL_USB_HOST_SUPPORT=y |
||||
CONFIG_SPL_USB_GADGET_SUPPORT=y |
||||
CONFIG_SPL_USB_SDP_SUPPORT=y |
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y |
||||
CONFIG_SYS_PROMPT="i.MX6 Logic # " |
||||
CONFIG_CMD_SPL=y |
||||
CONFIG_CMD_SPL_WRITE_SIZE=0x20000 |
||||
CONFIG_CMD_MEMTEST=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_NAND_TRIMFFS=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_USB_SDP=y |
||||
CONFIG_CMD_USB_MASS_STORAGE=y |
||||
CONFIG_CMD_CACHE=y |
||||
# CONFIG_CMD_LED is not set |
||||
CONFIG_CMD_PMIC=y |
||||
CONFIG_CMD_REGULATOR=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_MTDPARTS=y |
||||
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" |
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:4m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)" |
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)" |
||||
CONFIG_CMD_UBI=y |
||||
CONFIG_SPL_OF_CONTROL=y |
||||
CONFIG_ENV_IS_IN_NAND=y |
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
||||
CONFIG_SPL_DM=y |
||||
CONFIG_PCF8575_GPIO=y |
||||
CONFIG_SYS_I2C_MXC=y |
||||
CONFIG_LED=y |
||||
CONFIG_LED_GPIO=y |
||||
CONFIG_FSL_ESDHC=y |
||||
CONFIG_MTD_PARTITIONS=y |
||||
CONFIG_NAND=y |
||||
CONFIG_NAND_MXS=y |
||||
CONFIG_PHYLIB=y |
||||
CONFIG_PHY_SMSC=y |
||||
CONFIG_PHY_ATHEROS=y |
||||
CONFIG_FEC_MXC=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_SPL_PINCTRL=y |
||||
CONFIG_PINCTRL_IMX6=y |
||||
CONFIG_DM_PMIC_PFUZE100=y |
||||
CONFIG_DM_REGULATOR_PFUZE100=y |
||||
CONFIG_MXC_UART=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_GADGET=y |
||||
CONFIG_USB_GADGET_MANUFACTURER="FSL" |
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
||||
CONFIG_CI_UDC=y |
||||
CONFIG_USB_GADGET_DOWNLOAD=y |
||||
|
||||
@ -0,0 +1,59 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX7=y |
||||
CONFIG_SYS_TEXT_BASE=0x87800000 |
||||
CONFIG_SPL_GPIO_SUPPORT=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_TARGET_PICO_IMX7D=y |
||||
CONFIG_SPL_MMC_SUPPORT=y |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_LIBDISK_SUPPORT=y |
||||
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y |
||||
CONFIG_IMX_RDC=y |
||||
CONFIG_IMX_BOOTAUX=y |
||||
CONFIG_DISTRO_DEFAULTS=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" |
||||
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" |
||||
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb" |
||||
CONFIG_SPL_I2C_SUPPORT=y |
||||
CONFIG_SPL_USB_HOST_SUPPORT=y |
||||
CONFIG_SPL_USB_GADGET_SUPPORT=y |
||||
CONFIG_SPL_USB_SDP_SUPPORT=y |
||||
# CONFIG_CMD_BOOTD is not set |
||||
CONFIG_CMD_BOOTMENU=y |
||||
# CONFIG_CMD_IMI is not set |
||||
# CONFIG_CMD_XIMG is not set |
||||
CONFIG_CMD_SPL=y |
||||
CONFIG_CMD_SPL_WRITE_SIZE=0x20000 |
||||
CONFIG_CMD_DFU=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_GPT=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_USB_SDP=y |
||||
CONFIG_CMD_USB_MASS_STORAGE=y |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
# CONFIG_CMD_MII is not set |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_DFU_MMC=y |
||||
CONFIG_USB_FUNCTION_FASTBOOT=y |
||||
CONFIG_FASTBOOT_BUF_ADDR=0x82000000 |
||||
CONFIG_FASTBOOT_BUF_SIZE=0x10000000 |
||||
CONFIG_FASTBOOT_FLASH=y |
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y |
||||
CONFIG_FSL_ESDHC=y |
||||
CONFIG_PHYLIB=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_EHCI_HCD=y |
||||
CONFIG_MXC_USB_OTG_HACTIVE=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_USB_GADGET=y |
||||
CONFIG_USB_GADGET_MANUFACTURER="FSL" |
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
||||
CONFIG_CI_UDC=y |
||||
CONFIG_OF_LIBFDT=y |
||||
@ -0,0 +1,188 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0+ */ |
||||
/*
|
||||
* Copyright 2018 Toradex AG |
||||
* |
||||
* Configuration settings for the Colibri iMX6ULL module. |
||||
* |
||||
* based on colibri_imx7.h |
||||
*/ |
||||
|
||||
#ifndef __COLIBRI_IMX6ULL_CONFIG_H |
||||
#define __COLIBRI_IMX6ULL_CONFIG_H |
||||
|
||||
#include "mx6_common.h" |
||||
#define CONFIG_IOMUX_LPSR |
||||
|
||||
/* #define CONFIG_DBG_MONITOR*/ |
||||
#define PHYS_SDRAM_SIZE SZ_512M |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) |
||||
|
||||
/* Network */ |
||||
#define CONFIG_MII |
||||
#define CONFIG_FEC_XCV_TYPE RMII |
||||
#define CONFIG_ETHPRIME "FEC" |
||||
#define CONFIG_FEC_MXC_PHYADDR 0 |
||||
|
||||
#define CONFIG_IP_DEFRAG |
||||
#define CONFIG_TFTP_BLOCKSIZE 16352 |
||||
#define CONFIG_TFTP_TSIZE |
||||
|
||||
/* ENET1 */ |
||||
#define IMX_FEC_BASE ENET2_BASE_ADDR |
||||
|
||||
/* MMC Config*/ |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1 |
||||
|
||||
#undef CONFIG_BOOTM_PLAN9 |
||||
#undef CONFIG_BOOTM_RTEMS |
||||
|
||||
/* I2C configs */ |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
|
||||
#define CONFIG_IPADDR 192.168.10.2 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_SERVERIP 192.168.10.1 |
||||
|
||||
#define FDT_FILE "imx6ull-colibri${variant}-${fdt_board}.dtb" |
||||
|
||||
#define MEM_LAYOUT_ENV_SETTINGS \ |
||||
"bootm_size=0x10000000\0" \
|
||||
"fdt_addr_r=0x82000000\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"kernel_addr_r=0x81000000\0" \
|
||||
"pxefile_addr_r=0x87100000\0" \
|
||||
"ramdisk_addr_r=0x82100000\0" \
|
||||
"scriptaddr=0x87000000\0" |
||||
|
||||
#define NFS_BOOTCMD \ |
||||
"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
|
||||
"nfsboot=run setup; " \
|
||||
"setenv bootargs ${defargs} ${nfsargs} " \
|
||||
"${setupargs} ${vidargs}; echo Booting from NFS...;" \
|
||||
"dhcp ${kernel_addr_r} && " \
|
||||
"tftp ${fdt_addr_r} " FDT_FILE " && " \
|
||||
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||
|
||||
#define SD_BOOTCMD \ |
||||
"sdargs=root=/dev/mmcblk0p2 ro rootwait\0" \
|
||||
"sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \
|
||||
"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
|
||||
"load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \
|
||||
"load mmc 0:1 ${fdt_addr_r} " FDT_FILE " && " \
|
||||
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||
|
||||
#define UBI_BOOTCMD \ |
||||
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \
|
||||
"ubi.fm_autoconvert=1\0" \
|
||||
"ubiboot=run setup; " \
|
||||
"setenv bootargs ${defargs} ${ubiargs} " \
|
||||
"${setupargs} ${vidargs}; echo Booting from NAND...; " \
|
||||
"ubi part ubi &&" \
|
||||
"ubi read ${kernel_addr_r} kernel && " \
|
||||
"ubi read ${fdt_addr_r} dtb && " \
|
||||
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run ubiboot; " \ |
||||
"setenv fdtfile " FDT_FILE " && run distro_bootcmd;" |
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \ |
||||
func(MMC, mmc, 0) \
|
||||
func(USB, usb, 0) \
|
||||
func(DHCP, dhcp, na) |
||||
#include <config_distro_bootcmd.h> |
||||
|
||||
#define DFU_ALT_NAND_INFO "imx6ull-bcb part 0,1;u-boot1 part 0,2;u-boot2 part 0,3;u-boot-env part 0,4;ubi partubi 0,5" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
BOOTENV \
|
||||
MEM_LAYOUT_ENV_SETTINGS \
|
||||
NFS_BOOTCMD \
|
||||
SD_BOOTCMD \
|
||||
UBI_BOOTCMD \
|
||||
"console=ttymxc0\0" \
|
||||
"defargs=user_debug=30\0" \
|
||||
"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
|
||||
"fdt_board=eval-v3\0" \
|
||||
"fdt_fixup=;\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"kernel_file=zImage\0" \
|
||||
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
|
||||
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
|
||||
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
|
||||
"${board}/flash_eth.img && source ${loadaddr}\0" \
|
||||
"setsdupdate=mmc rescan && setenv interface mmc && " \
|
||||
"fatload ${interface} 0:1 ${loadaddr} " \
|
||||
"${board}/flash_blk.img && source ${loadaddr}\0" \
|
||||
"setup=setenv setupargs " \
|
||||
"console=tty1 console=${console}" \
|
||||
",${baudrate}n8 ${memargs} consoleblank=0\0" \
|
||||
"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
|
||||
"setusbupdate=usb start && setenv interface usb && " \
|
||||
"fatload ${interface} 0:1 ${loadaddr} " \
|
||||
"${board}/flash_blk.img && source ${loadaddr}\0" \
|
||||
"splashpos=m,m\0" \
|
||||
"videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \
|
||||
"vidargs=video=mxsfb:640x480-16@60" |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000 |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x08000000) |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_NAND) |
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024) |
||||
#define CONFIG_ENV_OFFSET (28 * CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
||||
#endif |
||||
|
||||
/* NAND stuff */ |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */ |
||||
#define CONFIG_SYS_NAND_BASE -1 |
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION |
||||
#define CONFIG_SYS_NAND_USE_FLASH_BBT |
||||
|
||||
/* USB Configs */ |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
||||
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
||||
#define CONFIG_MXC_USB_FLAGS 0 |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
||||
|
||||
#define CONFIG_IMX_THERMAL |
||||
|
||||
#define CONFIG_USBD_HS |
||||
|
||||
/* USB Device Firmware Update support */ |
||||
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M |
||||
#define DFU_DEFAULT_POLL_TIMEOUT 300 |
||||
|
||||
#ifdef CONFIG_VIDEO |
||||
#define CONFIG_VIDEO_MXS |
||||
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR |
||||
#define CONFIG_VIDEO_LOGO |
||||
#define CONFIG_SPLASH_SCREEN |
||||
#define CONFIG_SPLASH_SCREEN_ALIGN |
||||
#define CONFIG_BMP_16BPP |
||||
#define CONFIG_VIDEO_BMP_RLE8 |
||||
#define CONFIG_VIDEO_BMP_LOGO |
||||
#endif |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue