Tom Rini
8 years ago
commit
f19955a014
@ -1,42 +0,0 @@ |
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/*
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* Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect |
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* |
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* Copyright (C) 2016 Socionext Inc. |
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/io.h> |
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#include <linux/sizes.h> |
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#include "../init.h" |
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#define CCI500_BASE 0x5FD00000 |
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#define CCI500_SLAVE_OFFSET 0x1000 |
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#define CCI500_SNOOP_CTRL |
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#define CCI500_SNOOP_CTRL_EN_DVM BIT(1) |
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#define CCI500_SNOOP_CTRL_EN_SNOOP BIT(0) |
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void cci500_init(unsigned int nr_slaves) |
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{ |
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unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET; |
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int i; |
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for (i = 0; i < nr_slaves; i++) { |
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void __iomem *base; |
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u32 tmp; |
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base = ioremap(slave_base, SZ_4K); |
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tmp = readl(base); |
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tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP; |
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writel(tmp, base); |
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iounmap(base); |
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slave_base += CCI500_SLAVE_OFFSET; |
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} |
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} |
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@ -1,19 +0,0 @@ |
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/* |
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* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/linkage.h> |
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ENTRY(uniphier_smp_setup) |
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mrs x0, s3_1_c15_c2_1 /* CPUECTLR_EL1 */ |
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orr x0, x0, #(1 << 6) /* SMPEN */ |
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msr s3_1_c15_c2_1, x0 |
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ret |
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ENDPROC(uniphier_smp_setup) |
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ENTRY(uniphier_secondary_startup) |
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bl uniphier_smp_setup |
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b _start |
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ENDPROC(uniphier_secondary_startup) |
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@ -1,32 +0,0 @@ |
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/*
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* Copyright (C) 2016 Socionext Inc. |
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/io.h> |
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#include <linux/sizes.h> |
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#include "../init.h" |
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#define UNIPHIER_SMPCTRL_ROM_RSV0 0x59801200 |
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void uniphier_smp_setup(void); |
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void uniphier_secondary_startup(void); |
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void uniphier_smp_kick_all_cpus(void) |
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{ |
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void __iomem *rom_boot_rsv0; |
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rom_boot_rsv0 = ioremap(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8); |
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writeq((u64)uniphier_secondary_startup, rom_boot_rsv0); |
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iounmap(rom_boot_rsv0); |
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uniphier_smp_setup(); |
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asm("dsb ishst\n" /* Ensure the write to ROM_RSV0 is visible */ |
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"sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ |
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} |
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@ -1,37 +0,0 @@ |
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/*
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* Copyright (C) 2016 Socionext Inc. |
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/io.h> |
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#include <linux/sizes.h> |
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#define CNT_CONTROL_BASE 0x60E00000 |
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#define CNTCR 0x000 |
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#define CNTCR_EN BIT(0) |
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/* setup ARMv8 Generic Timer */ |
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int timer_init(void) |
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{ |
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void __iomem *base; |
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u32 tmp; |
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base = ioremap(CNT_CONTROL_BASE, SZ_4K); |
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/*
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* Note: |
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* In a system that implements both Secure and Non-secure states, |
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* this register is only writable in Secure state. |
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*/ |
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tmp = readl(base + CNTCR); |
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tmp |= CNTCR_EN; |
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writel(tmp, base + CNTCR); |
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iounmap(base); |
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return 0; |
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} |
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@ -1,262 +0,0 @@ |
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/*
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* Copyright (C) 2017 Socionext Inc. |
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <spl.h> |
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#include <linux/bitops.h> |
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#include <linux/compat.h> |
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#include <linux/io.h> |
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#include <asm/processor.h> |
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#include "../soc-info.h" |
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#define MMC_CMD_SWITCH 6 |
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#define MMC_CMD_SELECT_CARD 7 |
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#define MMC_CMD_SEND_CSD 9 |
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#define MMC_CMD_READ_MULTIPLE_BLOCK 18 |
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#define EXT_CSD_PART_CONF 179 /* R/W */ |
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#define MMC_RSP_PRESENT BIT(0) |
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#define MMC_RSP_136 BIT(1) /* 136 bit response */ |
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#define MMC_RSP_CRC BIT(2) /* expect valid crc */ |
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#define MMC_RSP_BUSY BIT(3) /* card may send busy */ |
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#define MMC_RSP_OPCODE BIT(4) /* response contains opcode */ |
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#define MMC_RSP_NONE (0) |
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#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) |
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#define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | \ |
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MMC_RSP_BUSY) |
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#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC) |
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#define MMC_RSP_R3 (MMC_RSP_PRESENT) |
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#define MMC_RSP_R4 (MMC_RSP_PRESENT) |
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#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) |
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#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) |
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#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) |
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#define SDHCI_DMA_ADDRESS 0x00 |
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#define SDHCI_BLOCK_SIZE 0x04 |
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#define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF)) |
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#define SDHCI_BLOCK_COUNT 0x06 |
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#define SDHCI_ARGUMENT 0x08 |
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#define SDHCI_TRANSFER_MODE 0x0C |
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#define SDHCI_TRNS_DMA BIT(0) |
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#define SDHCI_TRNS_BLK_CNT_EN BIT(1) |
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#define SDHCI_TRNS_ACMD12 BIT(2) |
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#define SDHCI_TRNS_READ BIT(4) |
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#define SDHCI_TRNS_MULTI BIT(5) |
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#define SDHCI_COMMAND 0x0E |
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#define SDHCI_CMD_RESP_MASK 0x03 |
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#define SDHCI_CMD_CRC 0x08 |
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#define SDHCI_CMD_INDEX 0x10 |
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#define SDHCI_CMD_DATA 0x20 |
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#define SDHCI_CMD_ABORTCMD 0xC0 |
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#define SDHCI_CMD_RESP_NONE 0x00 |
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#define SDHCI_CMD_RESP_LONG 0x01 |
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#define SDHCI_CMD_RESP_SHORT 0x02 |
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#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 |
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#define SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff)) |
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#define SDHCI_RESPONSE 0x10 |
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#define SDHCI_HOST_CONTROL 0x28 |
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#define SDHCI_CTRL_DMA_MASK 0x18 |
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#define SDHCI_CTRL_SDMA 0x00 |
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#define SDHCI_BLOCK_GAP_CONTROL 0x2A |
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#define SDHCI_SOFTWARE_RESET 0x2F |
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#define SDHCI_RESET_CMD 0x02 |
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#define SDHCI_RESET_DATA 0x04 |
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#define SDHCI_INT_STATUS 0x30 |
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#define SDHCI_INT_RESPONSE BIT(0) |
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#define SDHCI_INT_DATA_END BIT(1) |
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#define SDHCI_INT_ERROR BIT(15) |
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#define SDHCI_SIGNAL_ENABLE 0x38 |
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/* RCA assigned by Boot ROM */ |
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#define UNIPHIER_EMMC_RCA 0x1000 |
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struct uniphier_mmc_cmd { |
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unsigned int cmdidx; |
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unsigned int resp_type; |
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unsigned int cmdarg; |
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unsigned int is_data; |
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}; |
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static int uniphier_emmc_send_cmd(void __iomem *host_base, |
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struct uniphier_mmc_cmd *cmd) |
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{ |
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u32 mode = 0; |
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u32 mask = SDHCI_INT_RESPONSE; |
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u32 stat, flags; |
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writel(U32_MAX, host_base + SDHCI_INT_STATUS); |
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writel(0, host_base + SDHCI_SIGNAL_ENABLE); |
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writel(cmd->cmdarg, host_base + SDHCI_ARGUMENT); |
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if (cmd->is_data) |
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mode = SDHCI_TRNS_DMA | SDHCI_TRNS_BLK_CNT_EN | |
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SDHCI_TRNS_ACMD12 | SDHCI_TRNS_READ | |
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SDHCI_TRNS_MULTI; |
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writew(mode, host_base + SDHCI_TRANSFER_MODE); |
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if (!(cmd->resp_type & MMC_RSP_PRESENT)) |
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flags = SDHCI_CMD_RESP_NONE; |
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else if (cmd->resp_type & MMC_RSP_136) |
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flags = SDHCI_CMD_RESP_LONG; |
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else if (cmd->resp_type & MMC_RSP_BUSY) |
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flags = SDHCI_CMD_RESP_SHORT_BUSY; |
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else |
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flags = SDHCI_CMD_RESP_SHORT; |
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if (cmd->resp_type & MMC_RSP_CRC) |
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flags |= SDHCI_CMD_CRC; |
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if (cmd->resp_type & MMC_RSP_OPCODE) |
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flags |= SDHCI_CMD_INDEX; |
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if (cmd->is_data) |
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flags |= SDHCI_CMD_DATA; |
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if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data) |
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mask |= SDHCI_INT_DATA_END; |
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writew(SDHCI_MAKE_CMD(cmd->cmdidx, flags), host_base + SDHCI_COMMAND); |
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do { |
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stat = readl(host_base + SDHCI_INT_STATUS); |
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if (stat & SDHCI_INT_ERROR) |
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return -EIO; |
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} while ((stat & mask) != mask); |
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return 0; |
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} |
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static int uniphier_emmc_switch_part(void __iomem *host_base, int part_num) |
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{ |
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struct uniphier_mmc_cmd cmd = {}; |
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cmd.cmdidx = MMC_CMD_SWITCH; |
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cmd.resp_type = MMC_RSP_R1b; |
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cmd.cmdarg = (EXT_CSD_PART_CONF << 16) | (part_num << 8) | (3 << 24); |
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return uniphier_emmc_send_cmd(host_base, &cmd); |
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} |
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static int uniphier_emmc_is_over_2gb(void __iomem *host_base) |
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{ |
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struct uniphier_mmc_cmd cmd = {}; |
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u32 csd40, csd72; /* CSD[71:40], CSD[103:72] */ |
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int ret; |
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cmd.cmdidx = MMC_CMD_SEND_CSD; |
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cmd.resp_type = MMC_RSP_R2; |
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cmd.cmdarg = UNIPHIER_EMMC_RCA << 16; |
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ret = uniphier_emmc_send_cmd(host_base, &cmd); |
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if (ret) |
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return ret; |
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csd40 = readl(host_base + SDHCI_RESPONSE + 4); |
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csd72 = readl(host_base + SDHCI_RESPONSE + 8); |
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return !(~csd40 & 0xffc00380) && !(~csd72 & 0x3); |
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} |
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static int uniphier_emmc_load_image(void __iomem *host_base, u32 dev_addr, |
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unsigned long load_addr, u32 block_cnt) |
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{ |
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struct uniphier_mmc_cmd cmd = {}; |
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u8 tmp; |
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WARN_ON(load_addr >> 32); |
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writel(load_addr, host_base + SDHCI_DMA_ADDRESS); |
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writew(SDHCI_MAKE_BLKSZ(7, 512), host_base + SDHCI_BLOCK_SIZE); |
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writew(block_cnt, host_base + SDHCI_BLOCK_COUNT); |
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tmp = readb(host_base + SDHCI_HOST_CONTROL); |
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tmp &= ~SDHCI_CTRL_DMA_MASK; |
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tmp |= SDHCI_CTRL_SDMA; |
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writeb(tmp, host_base + SDHCI_HOST_CONTROL); |
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tmp = readb(host_base + SDHCI_BLOCK_GAP_CONTROL); |
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tmp &= ~1; /* clear Stop At Block Gap Request */ |
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writeb(tmp, host_base + SDHCI_BLOCK_GAP_CONTROL); |
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cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; |
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cmd.resp_type = MMC_RSP_R1; |
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cmd.cmdarg = dev_addr; |
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cmd.is_data = 1; |
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return uniphier_emmc_send_cmd(host_base, &cmd); |
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} |
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static int spl_board_load_image(struct spl_image_info *spl_image, |
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struct spl_boot_device *bootdev) |
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{ |
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u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; |
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void __iomem *host_base = (void __iomem *)0x5a000200; |
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struct uniphier_mmc_cmd cmd = {}; |
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int ret; |
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/*
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* deselect card before SEND_CSD command. |
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* Do not check the return code. It fails, but it is OK. |
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*/ |
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cmd.cmdidx = MMC_CMD_SELECT_CARD; |
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cmd.resp_type = MMC_RSP_R1; |
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uniphier_emmc_send_cmd(host_base, &cmd); /* CMD7 (arg=0) */ |
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/* reset CMD Line */ |
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writeb(SDHCI_RESET_CMD | SDHCI_RESET_DATA, |
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host_base + SDHCI_SOFTWARE_RESET); |
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while (readb(host_base + SDHCI_SOFTWARE_RESET)) |
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cpu_relax(); |
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ret = uniphier_emmc_is_over_2gb(host_base); |
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if (ret < 0) |
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return ret; |
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if (ret) { |
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debug("card is block addressing\n"); |
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} else { |
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debug("card is byte addressing\n"); |
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dev_addr *= 512; |
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} |
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cmd.cmdarg = UNIPHIER_EMMC_RCA << 16; |
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/* select card again */ |
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ret = uniphier_emmc_send_cmd(host_base, &cmd); |
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if (ret) |
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printf("failed to select card\n"); |
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/* Switch to Boot Partition 1 */ |
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ret = uniphier_emmc_switch_part(host_base, 1); |
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if (ret) |
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printf("failed to switch partition\n"); |
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ret = uniphier_emmc_load_image(host_base, dev_addr, |
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CONFIG_SYS_TEXT_BASE, 1); |
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if (ret) { |
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printf("failed to load image\n"); |
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return ret; |
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} |
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ret = spl_parse_image_header(spl_image, (void *)CONFIG_SYS_TEXT_BASE); |
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if (ret) |
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return ret; |
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ret = uniphier_emmc_load_image(host_base, dev_addr, |
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spl_image->load_addr, |
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spl_image->size / 512); |
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if (ret) { |
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printf("failed to load image\n"); |
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return ret; |
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} |
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return 0; |
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} |
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SPL_LOAD_IMAGE_METHOD("eMMC", 0, BOOT_DEVICE_BOARD, spl_board_load_image); |
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@ -1,25 +0,0 @@ |
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/*
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* Copyright (C) 2016-2017 Socionext Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/io.h> |
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#include "../init.h" |
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#include "../sc64-regs.h" |
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void uniphier_ld11_dram_clk_init(void) |
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{ |
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u32 tmp; |
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/* deassert reset */ |
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tmp = readl(SC_RSTCTRL7); |
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tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30; |
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writel(tmp, SC_RSTCTRL7); |
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/* provide clocks */ |
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tmp = readl(SC_CLKCTRL7); |
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tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30; |
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writel(tmp, SC_CLKCTRL7); |
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} |
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@ -1,28 +0,0 @@ |
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/*
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* Copyright (C) 2016-2017 Socionext Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/io.h> |
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#include "../init.h" |
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#include "../sc64-regs.h" |
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void uniphier_ld20_dram_clk_init(void) |
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{ |
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u32 tmp; |
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/* deassert reset */ |
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tmp = readl(SC_RSTCTRL7); |
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tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 | |
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SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 | |
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SC_RSTCTRL7_UMC30; |
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writel(tmp, SC_RSTCTRL7); |
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|
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/* provide clocks */ |
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tmp = readl(SC_CLKCTRL7); |
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tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 | |
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SC_CLKCTRL7_UMC30; |
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writel(tmp, SC_CLKCTRL7); |
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} |
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@ -1,20 +0,0 @@ |
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/*
|
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* Copyright (C) 2016-2017 Socionext Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/io.h> |
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#include "../init.h" |
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#include "../sc64-regs.h" |
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void uniphier_ld11_early_clk_init(void) |
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{ |
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u32 tmp; |
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/* provide clocks */ |
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tmp = readl(SC_CLKCTRL4); |
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tmp |= SC_CLKCTRL4_PERI; |
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writel(tmp, SC_CLKCTRL4); |
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} |
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@ -1,16 +0,0 @@ |
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/*
|
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* Copyright (C) 2016 Socionext Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include "../init.h" |
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#include "../sc64-regs.h" |
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#include "pll.h" |
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|
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int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd) |
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{ |
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uniphier_ld20_sscpll_init(SC_DPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); |
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return 0; |
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} |
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@ -1,19 +0,0 @@ |
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/*
|
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* Copyright (C) 2016 Socionext Inc. |
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include "../init.h" |
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#include "../sc64-regs.h" |
||||
#include "pll.h" |
||||
|
||||
int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
uniphier_ld20_sscpll_init(SC_DPLL0CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); |
||||
uniphier_ld20_sscpll_init(SC_DPLL1CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); |
||||
uniphier_ld20_sscpll_init(SC_DPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); |
||||
|
||||
return 0; |
||||
} |
||||
@ -1,79 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _DDRUQPHY_REGS_H |
||||
#define _DDRUQPHY_REGS_H |
||||
|
||||
#include <linux/bitops.h> |
||||
|
||||
#define PHY_REG_SHIFT 2 |
||||
#define PHY_SLV_DLY_WIDTH 6 |
||||
#define PHY_BITLVL_DLY_WIDTH 6 |
||||
#define PHY_MAS_DLY_WIDTH 8 |
||||
|
||||
#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_START_GO_DONE BIT(28) |
||||
#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_CONFIG_1 (0x46 << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT)) |
||||
#define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_RECALIB_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0) |
||||
#define PHY_DLL_RECALIB_INCR BIT(27) |
||||
#define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_ADRCTRL_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0) |
||||
#define PHY_DLL_ADRCTRL_INCR BIT(9) |
||||
#define PHY_DLL_ADRCTRL_MDL_SHIFT 24 |
||||
#define PHY_DLL_ADRCTRL_MDL_MASK (GENMASK(PHY_MAS_DLY_WIDTH - 1, 0) << \ |
||||
PHY_DLL_ADRCTRL_MDL_SHIFT) |
||||
#define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT)) |
||||
#define PHY_LANE_SEL_LANE_SHIFT 0 |
||||
#define PHY_LANE_SEL_LANE_WIDTH 8 |
||||
#define PHY_LANE_SEL_BIT_SHIFT 8 |
||||
#define PHY_LANE_SEL_BIT_WIDTH 4 |
||||
#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_MAIN_CLK_DELTA (0x50 << (PHY_REG_SHIFT)) |
||||
#define PHY_WRLVL_AUTOINC_TRIM (0x53 << (PHY_REG_SHIFT)) |
||||
#define PHY_WRLVL_DYN_ODT (0x54 << (PHY_REG_SHIFT)) |
||||
#define PHY_WRLVL_ON_OFF (0x55 << (PHY_REG_SHIFT)) |
||||
#define PHY_UNQ_ANALOG_DLL_1 (0x57 << (PHY_REG_SHIFT)) |
||||
#define PHY_UNQ_ANALOG_DLL_2 (0x58 << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_INCR_TRIM_1 (0x59 << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_INCR_TRIM_3 (0x5A << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_CONFIG_3 (0x5B << (PHY_REG_SHIFT)) |
||||
#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT)) |
||||
#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT)) |
||||
#define PHY_IP_DQ_DQS_BITWISE_TRIM_MASK \ |
||||
GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0) |
||||
#define PHY_IP_DQ_DQS_BITWISE_TRIM_INC \ |
||||
BIT(PHY_BITLVL_DLY_WIDTH) |
||||
#define PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE \ |
||||
BIT(PHY_BITLVL_DLY_WIDTH + 1) |
||||
#define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT)) |
||||
#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT)) |
||||
#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK \ |
||||
GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0) |
||||
#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC \ |
||||
BIT(PHY_BITLVL_DLY_WIDTH) |
||||
#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE \ |
||||
BIT(PHY_BITLVL_DLY_WIDTH + 1) |
||||
#define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_TRIM_CLK_MASK GENMASK(PHY_SLV_DLY_WIDTH, 0) |
||||
#define PHY_DLL_TRIM_CLK_INCR BIT(PHY_SLV_DLY_WIDTH + 1) |
||||
#define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT)) |
||||
#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_CONFIG_4 (0x6F << (PHY_REG_SHIFT)) |
||||
#define PHY_DYNAMIC_WRITE_BIT_LVL (0x70 << (PHY_REG_SHIFT)) |
||||
#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT)) |
||||
|
||||
#endif /* _DDRUQPHY_REGS_H */ |
||||
@ -1,491 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/io.h> |
||||
#include <linux/sizes.h> |
||||
#include <asm/processor.h> |
||||
|
||||
#include "../init.h" |
||||
#include "ddrphy-regs.h" |
||||
#include "umc64-regs.h" |
||||
|
||||
#define DDR_FREQ 1600 |
||||
|
||||
#define DRAM_CH_NR 2 |
||||
#define RANK_BLOCKS_TR 2 |
||||
|
||||
enum dram_freq { |
||||
DRAM_FREQ_1600M, |
||||
DRAM_FREQ_NR, |
||||
}; |
||||
|
||||
enum dram_size { |
||||
DRAM_SZ_256M, |
||||
DRAM_SZ_512M, |
||||
DRAM_SZ_NR, |
||||
}; |
||||
|
||||
/* PHY */ |
||||
static const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} }; |
||||
static const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} }; |
||||
static const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} }; |
||||
static const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} }; |
||||
static const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} }; |
||||
|
||||
/* Register address */ |
||||
#define PHY_ZQ0CR1 0x00000184 |
||||
#define PHY_ZQ1CR1 0x00000194 |
||||
#define PHY_ZQ2CR1 0x000001A4 |
||||
#define PHY_DX0GCR 0x000001C0 |
||||
#define PHY_DX0GTR 0x000001F0 |
||||
#define PHY_DX1GCR 0x00000200 |
||||
#define PHY_DX1GTR 0x00000230 |
||||
#define PHY_DX2GCR 0x00000240 |
||||
#define PHY_DX2GTR 0x00000270 |
||||
#define PHY_DX3GCR 0x00000280 |
||||
#define PHY_DX3GTR 0x000002B0 |
||||
|
||||
#define PHY_DXMDLR(dx) (0x000001EC + 0x40 * (dx)) |
||||
#define PHY_DXLCDLR0(dx) (0x000001E0 + 0x40 * (dx)) |
||||
#define PHY_DXLCDLR1(dx) (0x000001E4 + 0x40 * (dx)) |
||||
#define PHY_DXLCDLR2(dx) (0x000001E8 + 0x40 * (dx)) |
||||
#define PHY_DXBDLR1(dx) (0x000001D0 + 0x40 * (dx)) |
||||
#define PHY_DXBDLR2(dx) (0x000001D4 + 0x40 * (dx)) |
||||
|
||||
/* MASK */ |
||||
#define PHY_ACBD_MASK 0x00FC0000 |
||||
#define PHY_CK0BD_MASK 0x0000003F |
||||
#define PHY_CK1BD_MASK 0x00000FC0 |
||||
#define PHY_IPRD_MASK 0x000000FF |
||||
#define PHY_WLD_MASK(rank) (0xFF << (8 * (rank))) |
||||
#define PHY_DQSGD_MASK(rank) (0xFF << (8 * (rank))) |
||||
#define PHY_DQSGX_MASK BIT(6) |
||||
#define PHY_DSWBD_MASK 0x3F000000 /* bit[29:24] */ |
||||
#define PHY_DSDQOE_MASK 0x00000FFF |
||||
|
||||
static void ddrphy_maskwritel(u32 data, u32 mask, void __iomem *addr) |
||||
{ |
||||
u32 value; |
||||
|
||||
value = (readl(addr) & ~(mask)) | (data & mask); |
||||
writel(value, addr); |
||||
} |
||||
|
||||
static u32 ddrphy_maskreadl(u32 mask, void __iomem *addr) |
||||
{ |
||||
return readl(addr) & mask; |
||||
} |
||||
|
||||
/* step of 0.5T for PUB-byte */ |
||||
static u8 ddrphy_get_mdl(int dx, void __iomem *phy_base) |
||||
{ |
||||
return ddrphy_maskreadl(PHY_IPRD_MASK, phy_base + PHY_DXMDLR(dx)); |
||||
} |
||||
|
||||
/* Calculating step for PUB-byte */ |
||||
static int ddrphy_hpstep(int delay, int dx, void __iomem *phy_base) |
||||
{ |
||||
return delay * ddrphy_get_mdl(dx, phy_base) * DDR_FREQ / 1000000; |
||||
} |
||||
|
||||
static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
tmp = readl(phy_base + PHY_PGCR1); |
||||
|
||||
if (enable) |
||||
tmp &= ~PHY_PGCR1_INHVT; |
||||
else |
||||
tmp |= PHY_PGCR1_INHVT; |
||||
|
||||
writel(tmp, phy_base + PHY_PGCR1); |
||||
|
||||
if (!enable) { |
||||
while (!(readl(phy_base + PHY_PGSR1) & PHY_PGSR1_VTSTOP)) |
||||
cpu_relax(); |
||||
} |
||||
} |
||||
|
||||
static void ddrphy_set_ckoffset_qoffset(int delay_ckoffset0, int delay_ckoffset1, |
||||
int delay_qoffset, int enable, |
||||
void __iomem *phy_base) |
||||
{ |
||||
u8 ck_step0, ck_step1; /* ckoffset_step for clock */ |
||||
u8 q_step; /* qoffset_step for clock */ |
||||
int dx; |
||||
|
||||
dx = 2; /* use dx2 in sLD11 */ |
||||
|
||||
ck_step0 = ddrphy_hpstep(delay_ckoffset0, dx, phy_base); /* CK-Offset */ |
||||
ck_step1 = ddrphy_hpstep(delay_ckoffset1, dx, phy_base); /* CK-Offset */ |
||||
q_step = ddrphy_hpstep(delay_qoffset, dx, phy_base); /* Q-Offset */ |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 0); |
||||
|
||||
/* Q->[23:18], CK1->[11:6], CK0->bit[5:0] */ |
||||
if (enable == 1) |
||||
ddrphy_maskwritel((q_step << 18) + (ck_step1 << 6) + ck_step0, |
||||
PHY_ACBD_MASK | PHY_CK1BD_MASK | PHY_CK0BD_MASK, |
||||
phy_base + PHY_ACBDLR); |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 1); |
||||
} |
||||
|
||||
static void ddrphy_set_wl_delay_dx(int dx, int r0_delay, int r1_delay, |
||||
int enable, void __iomem *phy_base) |
||||
{ |
||||
int rank; |
||||
int delay_wl[4]; |
||||
u32 wl_mask = 0; /* WriteLeveling's Mask */ |
||||
u32 wl_value = 0; /* WriteLeveling's Value */ |
||||
|
||||
delay_wl[0] = r0_delay & 0xfff; |
||||
delay_wl[1] = r1_delay & 0xfff; |
||||
delay_wl[2] = 0; |
||||
delay_wl[3] = 0; |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 0); |
||||
|
||||
for (rank = 0; rank < 4; rank++) { |
||||
wl_mask |= PHY_WLD_MASK(rank); |
||||
/* WriteLeveling's delay */ |
||||
wl_value |= ddrphy_hpstep(delay_wl[rank], dx, phy_base) << (8 * rank); |
||||
} |
||||
|
||||
if (enable == 1) |
||||
ddrphy_maskwritel(wl_value, wl_mask, phy_base + PHY_DXLCDLR0(dx)); |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 1); |
||||
} |
||||
|
||||
static void ddrphy_set_dqsg_delay_dx(int dx, int r0_delay, int r1_delay, |
||||
int enable, void __iomem *phy_base) |
||||
{ |
||||
int rank; |
||||
int delay_dqsg[4]; |
||||
u32 dqsg_mask = 0; /* DQSGating_LCDL_delay's Mask */ |
||||
u32 dqsg_value = 0; /* DQSGating_LCDL_delay's Value */ |
||||
|
||||
delay_dqsg[0] = r0_delay; |
||||
delay_dqsg[1] = r1_delay; |
||||
delay_dqsg[2] = 0; |
||||
delay_dqsg[3] = 0; |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 0); |
||||
|
||||
for (rank = 0; rank < 4; rank++) { |
||||
dqsg_mask |= PHY_DQSGD_MASK(rank); |
||||
/* DQSGating's delay */ |
||||
dqsg_value |= ddrphy_hpstep(delay_dqsg[rank], dx, phy_base) << (8 * rank); |
||||
} |
||||
|
||||
if (enable == 1) |
||||
ddrphy_maskwritel(dqsg_value, dqsg_mask, phy_base + PHY_DXLCDLR2(dx)); |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 1); |
||||
} |
||||
|
||||
static void ddrphy_set_dswb_delay_dx(int dx, int delay, int enable, void __iomem *phy_base) |
||||
{ |
||||
u8 dswb_step; |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 0); |
||||
|
||||
dswb_step = ddrphy_hpstep(delay, dx, phy_base); /* DQS-BDL's delay */ |
||||
|
||||
if (enable == 1) |
||||
ddrphy_maskwritel(dswb_step << 24, PHY_DSWBD_MASK, phy_base + PHY_DXBDLR1(dx)); |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 1); |
||||
} |
||||
|
||||
static void ddrphy_set_oe_delay_dx(int dx, int dqs_delay, int dq_delay, |
||||
int enable, void __iomem *phy_base) |
||||
{ |
||||
u8 dqs_oe_step, dq_oe_step; |
||||
u32 wdata; |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 0); |
||||
|
||||
/* OE(DQS,DQ) */ |
||||
dqs_oe_step = ddrphy_hpstep(dqs_delay, dx, phy_base); /* DQS-oe's delay */ |
||||
dq_oe_step = ddrphy_hpstep(dq_delay, dx, phy_base); /* DQ-oe's delay */ |
||||
wdata = ((dq_oe_step<<6) + dqs_oe_step) & 0xFFF; |
||||
|
||||
if (enable == 1) |
||||
ddrphy_maskwritel(wdata, PHY_DSDQOE_MASK, phy_base + PHY_DXBDLR2(dx)); |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 1); |
||||
} |
||||
|
||||
static void ddrphy_ext_dqsgt(void __iomem *phy_base) |
||||
{ |
||||
/* Extend DQSGating_window min:+1T max:+1T */ |
||||
ddrphy_maskwritel(PHY_DQSGX_MASK, PHY_DQSGX_MASK, phy_base + PHY_DSGCR); |
||||
} |
||||
|
||||
static void ddrphy_shift_tof_hws(void __iomem *phy_base, const int shift[][2]) |
||||
{ |
||||
int dx, block, byte; |
||||
u32 lcdlr1, wdqd; |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 0); |
||||
|
||||
for (block = 0; block < RANK_BLOCKS_TR; block++) { |
||||
for (byte = 0; byte < 2; byte++) { |
||||
dx = block * 2 + byte; |
||||
lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx)); |
||||
wdqd = lcdlr1 & 0xff; |
||||
wdqd = clamp(wdqd + ddrphy_hpstep(shift[block][byte], dx, phy_base), |
||||
0U, 0xffU); |
||||
lcdlr1 = (lcdlr1 & ~0xff) | wdqd; |
||||
writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx)); |
||||
readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */ |
||||
} |
||||
} |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 1); |
||||
} |
||||
|
||||
static void ddrphy_shift_rof_hws(void __iomem *phy_base, const int pos_shift[][2], |
||||
const int neg_shift[][2]) |
||||
{ |
||||
int dx, block, byte; |
||||
u32 lcdlr1, rdqsd, rdqnsd; |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 0); |
||||
|
||||
for (block = 0; block < RANK_BLOCKS_TR; block++) { |
||||
for (byte = 0; byte < 2; byte++) { |
||||
dx = block * 2 + byte; |
||||
lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx)); |
||||
|
||||
/* DQS LCDL RDQNSD->[23:16] RDQSD->[15:8] */ |
||||
rdqsd = (lcdlr1 >> 8) & 0xff; |
||||
rdqnsd = (lcdlr1 >> 16) & 0xff; |
||||
rdqsd = clamp(rdqsd + ddrphy_hpstep(pos_shift[block][byte], dx, phy_base), |
||||
0U, 0xffU); |
||||
rdqnsd = clamp(rdqnsd + ddrphy_hpstep(neg_shift[block][byte], dx, phy_base), |
||||
0U, 0xffU); |
||||
lcdlr1 = (lcdlr1 & ~(0xffff << 8)) | (rdqsd << 8) | (rdqnsd << 16); |
||||
writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx)); |
||||
readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */ |
||||
} |
||||
} |
||||
|
||||
ddrphy_vt_ctrl(phy_base, 1); |
||||
} |
||||
|
||||
static void ddrphy_boot_run_hws(void __iomem *phy_base) |
||||
{ |
||||
/* Hard Training for DIO */ |
||||
writel(0x0000f401, phy_base + PHY_PIR); |
||||
while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE)) |
||||
cpu_relax(); |
||||
} |
||||
|
||||
static void ddrphy_training(void __iomem *phy_base) |
||||
{ |
||||
/* DIO roffset shift before hard training */ |
||||
ddrphy_shift_rof_hws(phy_base, rof_pos_shift_pre, rof_neg_shift_pre); |
||||
|
||||
/* Hard Training for each CH */ |
||||
ddrphy_boot_run_hws(phy_base); |
||||
|
||||
/* DIO toffset shift after training */ |
||||
ddrphy_shift_tof_hws(phy_base, tof_shift); |
||||
|
||||
/* DIO roffset shift after training */ |
||||
ddrphy_shift_rof_hws(phy_base, rof_pos_shift, rof_neg_shift); |
||||
|
||||
/* Extend DQSGating window min:+1T max:+1T */ |
||||
ddrphy_ext_dqsgt(phy_base); |
||||
} |
||||
|
||||
static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq) |
||||
{ |
||||
writel(0x40000000, phy_base + PHY_PIR); |
||||
writel(0x0300C4F1, phy_base + PHY_PGCR1); |
||||
writel(0x0C807D04, phy_base + PHY_PTR0); |
||||
writel(0x27100578, phy_base + PHY_PTR1); |
||||
writel(0x00083DEF, phy_base + PHY_PTR2); |
||||
writel(0x12061A80, phy_base + PHY_PTR3); |
||||
writel(0x08027100, phy_base + PHY_PTR4); |
||||
writel(0x9D9CBB66, phy_base + PHY_DTPR0); |
||||
writel(0x1a878400, phy_base + PHY_DTPR1); |
||||
writel(0x50025200, phy_base + PHY_DTPR2); |
||||
writel(0xF004641A, phy_base + PHY_DSGCR); |
||||
writel(0x0000040B, phy_base + PHY_DCR); |
||||
writel(0x00000d71, phy_base + PHY_MR0); |
||||
writel(0x00000006, phy_base + PHY_MR1); |
||||
writel(0x00000098, phy_base + PHY_MR2); |
||||
writel(0x00000000, phy_base + PHY_MR3); |
||||
|
||||
while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE)) |
||||
cpu_relax(); |
||||
|
||||
writel(0x00000059, phy_base + PHY_ZQ0CR1); |
||||
writel(0x00000019, phy_base + PHY_ZQ1CR1); |
||||
writel(0x00000019, phy_base + PHY_ZQ2CR1); |
||||
writel(0x30FC6C20, phy_base + PHY_PGCR2); |
||||
|
||||
ddrphy_set_ckoffset_qoffset(119, 0, 0, 1, phy_base); |
||||
ddrphy_set_wl_delay_dx(0, 220, 220, 1, phy_base); |
||||
ddrphy_set_wl_delay_dx(1, 160, 160, 1, phy_base); |
||||
ddrphy_set_wl_delay_dx(2, 190, 190, 1, phy_base); |
||||
ddrphy_set_wl_delay_dx(3, 150, 150, 1, phy_base); |
||||
ddrphy_set_dqsg_delay_dx(0, 750, 750, 1, phy_base); |
||||
ddrphy_set_dqsg_delay_dx(1, 750, 750, 1, phy_base); |
||||
ddrphy_set_dqsg_delay_dx(2, 750, 750, 1, phy_base); |
||||
ddrphy_set_dqsg_delay_dx(3, 750, 750, 1, phy_base); |
||||
ddrphy_set_dswb_delay_dx(0, 0, 1, phy_base); |
||||
ddrphy_set_dswb_delay_dx(1, 0, 1, phy_base); |
||||
ddrphy_set_dswb_delay_dx(2, 0, 1, phy_base); |
||||
ddrphy_set_dswb_delay_dx(3, 0, 1, phy_base); |
||||
ddrphy_set_oe_delay_dx(0, 0, 0, 1, phy_base); |
||||
ddrphy_set_oe_delay_dx(1, 0, 0, 1, phy_base); |
||||
ddrphy_set_oe_delay_dx(2, 0, 0, 1, phy_base); |
||||
ddrphy_set_oe_delay_dx(3, 0, 0, 1, phy_base); |
||||
|
||||
writel(0x44000E81, phy_base + PHY_DX0GCR); |
||||
writel(0x44000E81, phy_base + PHY_DX1GCR); |
||||
writel(0x44000E81, phy_base + PHY_DX2GCR); |
||||
writel(0x44000E81, phy_base + PHY_DX3GCR); |
||||
writel(0x00055002, phy_base + PHY_DX0GTR); |
||||
writel(0x00055002, phy_base + PHY_DX1GTR); |
||||
writel(0x00055010, phy_base + PHY_DX2GTR); |
||||
writel(0x00055010, phy_base + PHY_DX3GTR); |
||||
writel(0x930035C7, phy_base + PHY_DTCR); |
||||
writel(0x00000003, phy_base + PHY_PIR); |
||||
readl(phy_base + PHY_PIR); |
||||
while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE)) |
||||
cpu_relax(); |
||||
|
||||
writel(0x00000181, phy_base + PHY_PIR); |
||||
readl(phy_base + PHY_PIR); |
||||
while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE)) |
||||
cpu_relax(); |
||||
|
||||
writel(0x44181884, phy_base + PHY_DXCCR); |
||||
writel(0x00000001, phy_base + PHY_GPR1); |
||||
} |
||||
|
||||
/* UMC */ |
||||
static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060B0B1C}; |
||||
static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x27201806}; |
||||
static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00120B04}; |
||||
static const u32 umc_cmdctle[DRAM_FREQ_NR] = {0x00680607}; |
||||
static const u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200}; |
||||
static const u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808}; |
||||
|
||||
static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000810}; |
||||
static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000004}; |
||||
static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002}; |
||||
static const u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203}; |
||||
|
||||
static const u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605}; |
||||
|
||||
static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, |
||||
unsigned long size, int ch) |
||||
{ |
||||
/* Wait for PHY Init Complete */ |
||||
writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA); |
||||
writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB); |
||||
writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC); |
||||
writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE); |
||||
writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF); |
||||
writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG); |
||||
|
||||
writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D0); |
||||
writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D1); |
||||
|
||||
writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D0); |
||||
writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D1); |
||||
|
||||
writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D0); |
||||
writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D1); |
||||
|
||||
writel(0x00000003, dc_base + UMC_ACSSETA); |
||||
writel(0x00000103, dc_base + UMC_FLOWCTLG); |
||||
writel(umc_acssetb[ch], dc_base + UMC_ACSSETB); |
||||
writel(0x02020200, dc_base + UMC_SPCSETB); |
||||
writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH); |
||||
writel(0x00000002, dc_base + UMC_ACFETCHCTRL); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int umc_ch_init(void __iomem *umc_ch_base, |
||||
enum dram_freq freq, unsigned long size, int ch) |
||||
{ |
||||
void __iomem *dc_base = umc_ch_base; |
||||
|
||||
return umc_dc_init(dc_base, freq, size, ch); |
||||
} |
||||
|
||||
static void um_init(void __iomem *um_base) |
||||
{ |
||||
writel(0x00000001, um_base + UMC_SIORST); |
||||
writel(0x00000001, um_base + UMC_VO0RST); |
||||
writel(0x00000001, um_base + UMC_VPERST); |
||||
writel(0x00000001, um_base + UMC_RGLRST); |
||||
writel(0x00000001, um_base + UMC_A2DRST); |
||||
writel(0x00000001, um_base + UMC_DMDRST); |
||||
} |
||||
|
||||
int uniphier_ld11_umc_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
void __iomem *um_base = (void __iomem *)0x5B800000; |
||||
void __iomem *umc_ch_base = (void __iomem *)0x5BC00000; |
||||
void __iomem *phy_base = (void __iomem *)0x5BC01000; |
||||
enum dram_freq freq; |
||||
int ch, ret; |
||||
|
||||
switch (bd->dram_freq) { |
||||
case 1600: |
||||
freq = DRAM_FREQ_1600M; |
||||
break; |
||||
default: |
||||
pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
writel(0x00000101, umc_ch_base + UMC_DIOCTLA); |
||||
while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE)) |
||||
cpu_relax(); |
||||
|
||||
writel(0x00000000, umc_ch_base + UMC_DIOCTLA); |
||||
writel(0x00000001, umc_ch_base + UMC_DEBUGC); |
||||
writel(0x00000101, umc_ch_base + UMC_DIOCTLA); |
||||
|
||||
writel(0x00000100, umc_ch_base + UMC_INITSET); |
||||
while (readl(umc_ch_base + UMC_INITSTAT) & BIT(8)) |
||||
cpu_relax(); |
||||
|
||||
writel(0x00000100, umc_ch_base + 0x00200000 + UMC_INITSET); |
||||
while (readl(umc_ch_base + 0x00200000 + UMC_INITSTAT) & BIT(8)) |
||||
cpu_relax(); |
||||
|
||||
ddrphy_init(phy_base, freq); |
||||
|
||||
for (ch = 0; ch < DRAM_CH_NR; ch++) { |
||||
unsigned long size = bd->dram_ch[ch].size; |
||||
unsigned int width = bd->dram_ch[ch].width; |
||||
|
||||
ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch); |
||||
if (ret) { |
||||
pr_err("failed to initialize UMC ch%d\n", ch); |
||||
return ret; |
||||
} |
||||
|
||||
umc_ch_base += 0x00200000; |
||||
} |
||||
ddrphy_training(phy_base); |
||||
|
||||
um_init(um_base); |
||||
|
||||
return 0; |
||||
} |
||||
@ -1,636 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2016-2017 Socionext Inc. |
||||
* |
||||
* based on commit 5ffd75ecd4929f22361ef65a35f0331d2fbc0f35 of Diag |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/bitops.h> |
||||
#include <linux/compat.h> |
||||
#include <linux/errno.h> |
||||
#include <linux/io.h> |
||||
#include <linux/sizes.h> |
||||
#include <asm/processor.h> |
||||
|
||||
#include "../init.h" |
||||
#include "ddruqphy-regs.h" |
||||
#include "umc64-regs.h" |
||||
|
||||
#define DRAM_CH_NR 3 |
||||
|
||||
enum dram_freq { |
||||
DRAM_FREQ_1866M, |
||||
DRAM_FREQ_NR, |
||||
}; |
||||
|
||||
enum dram_size { |
||||
DRAM_SZ_256M, |
||||
DRAM_SZ_512M, |
||||
DRAM_SZ_NR, |
||||
}; |
||||
|
||||
enum dram_board { /* board type */ |
||||
DRAM_BOARD_LD20_REF, /* LD20 reference */ |
||||
DRAM_BOARD_LD20_GLOBAL, /* LD20 TV */ |
||||
DRAM_BOARD_LD20_C1, /* LD20 TV C1 */ |
||||
DRAM_BOARD_LD21_REF, /* LD21 reference */ |
||||
DRAM_BOARD_LD21_GLOBAL, /* LD21 TV */ |
||||
DRAM_BOARD_NR, |
||||
}; |
||||
|
||||
/* PHY */ |
||||
static const int ddrphy_adrctrl[DRAM_BOARD_NR][DRAM_CH_NR] = { |
||||
{268 - 262, 268 - 263, 268 - 378}, /* LD20 reference */ |
||||
{268 - 262, 268 - 263, 268 - 378}, /* LD20 TV */ |
||||
{268 - 262, 268 - 263, 268 - 378}, /* LD20 TV C1 */ |
||||
{268 - 212, 268 - 268, /* No CH2 */}, /* LD21 reference */ |
||||
{268 - 212, 268 - 268, /* No CH2 */}, /* LD21 TV */ |
||||
}; |
||||
|
||||
static const int ddrphy_dlltrimclk[DRAM_BOARD_NR][DRAM_CH_NR] = { |
||||
{268, 268, 268}, /* LD20 reference */ |
||||
{268, 268, 268}, /* LD20 TV */ |
||||
{189, 189, 189}, /* LD20 TV C1 */ |
||||
{268, 268 + 252, /* No CH2 */}, /* LD21 reference */ |
||||
{268, 268 + 202, /* No CH2 */}, /* LD21 TV */ |
||||
}; |
||||
|
||||
static const int ddrphy_dllrecalib[DRAM_BOARD_NR][DRAM_CH_NR] = { |
||||
{268 - 378, 268 - 263, 268 - 378}, /* LD20 reference */ |
||||
{268 - 378, 268 - 263, 268 - 378}, /* LD20 TV */ |
||||
{268 - 378, 268 - 263, 268 - 378}, /* LD20 TV C1 */ |
||||
{268 - 212, 268 - 536, /* No CH2 */}, /* LD21 reference */ |
||||
{268 - 212, 268 - 536, /* No CH2 */}, /* LD21 TV */ |
||||
}; |
||||
|
||||
static const u32 ddrphy_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = { |
||||
{0x50B840B1, 0x50B840B1, 0x50B840B1}, /* LD20 reference */ |
||||
{0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV */ |
||||
{0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV C1 */ |
||||
{0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 reference */ |
||||
{0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 TV */ |
||||
}; |
||||
|
||||
static const u32 ddrphy_scl_gate_timing[DRAM_CH_NR] = { |
||||
0x00000140, 0x00000180, 0x00000140 |
||||
}; |
||||
|
||||
static const short ddrphy_op_dq_shift_val_ld20[DRAM_CH_NR][32] = { |
||||
{ |
||||
2, 1, 0, 1, 2, 1, 1, 1, |
||||
2, 1, 1, 2, 1, 1, 1, 1, |
||||
1, 2, 1, 1, 1, 2, 1, 1, |
||||
2, 2, 0, 1, 1, 2, 2, 1, |
||||
}, |
||||
{ |
||||
1, 1, 0, 1, 2, 2, 1, 1, |
||||
1, 1, 1, 1, 1, 1, 1, 1, |
||||
1, 1, 0, 0, 1, 1, 0, 0, |
||||
0, 1, 1, 1, 2, 1, 2, 1, |
||||
}, |
||||
{ |
||||
2, 2, 0, 2, 1, 1, 2, 1, |
||||
1, 1, 0, 1, 1, -1, 1, 1, |
||||
2, 2, 2, 2, 1, 1, 1, 1, |
||||
1, 1, 1, 0, 2, 2, 1, 2, |
||||
}, |
||||
}; |
||||
|
||||
static const short ddrphy_op_dq_shift_val_ld21[DRAM_CH_NR][32] = { |
||||
{ |
||||
1, 1, 0, 1, 1, 1, 1, 1, |
||||
1, 0, 0, 0, 1, 1, 0, 2, |
||||
1, 1, 0, 0, 1, 1, 1, 1, |
||||
1, 0, 0, 0, 1, 0, 0, 1, |
||||
}, |
||||
{ 1, 0, 2, 1, 1, 1, 1, 0, |
||||
1, 0, 0, 1, 0, 1, 0, 0, |
||||
1, 0, 1, 0, 1, 1, 1, 0, |
||||
1, 1, 1, 1, 0, 1, 0, 0, |
||||
}, |
||||
/* No CH2 */ |
||||
}; |
||||
|
||||
static const short (* const ddrphy_op_dq_shift_val[DRAM_BOARD_NR])[32] = { |
||||
ddrphy_op_dq_shift_val_ld20, /* LD20 reference */ |
||||
ddrphy_op_dq_shift_val_ld20, /* LD20 TV */ |
||||
ddrphy_op_dq_shift_val_ld20, /* LD20 TV C */ |
||||
ddrphy_op_dq_shift_val_ld21, /* LD21 reference */ |
||||
ddrphy_op_dq_shift_val_ld21, /* LD21 TV */ |
||||
}; |
||||
|
||||
static const short ddrphy_ip_dq_shift_val_ld20[DRAM_CH_NR][32] = { |
||||
{ |
||||
3, 3, 3, 2, 3, 2, 0, 2, |
||||
2, 3, 3, 1, 2, 2, 2, 2, |
||||
2, 2, 2, 2, 0, 1, 1, 1, |
||||
2, 2, 2, 2, 3, 0, 2, 2, |
||||
}, |
||||
{ |
||||
2, 2, 1, 1, -1, 1, 1, 1, |
||||
2, 0, 2, 2, 2, 1, 0, 2, |
||||
2, 1, 2, 1, 0, 1, 1, 1, |
||||
2, 2, 2, 2, 2, 2, 2, 2, |
||||
}, |
||||
{ |
||||
2, 2, 3, 2, 1, 2, 2, 2, |
||||
2, 3, 4, 2, 3, 4, 3, 3, |
||||
2, 2, 1, 2, 1, 1, 1, 1, |
||||
2, 2, 2, 2, 1, 2, 2, 1, |
||||
}, |
||||
}; |
||||
|
||||
static const short ddrphy_ip_dq_shift_val_ld21[DRAM_CH_NR][32] = { |
||||
{ |
||||
2, 2, 2, 2, 1, 2, 2, 2, |
||||
2, 3, 3, 2, 2, 2, 2, 2, |
||||
2, 1, 2, 2, 1, 1, 1, 1, |
||||
2, 2, 2, 3, 1, 2, 2, 2, |
||||
}, |
||||
{ |
||||
3, 4, 4, 1, 0, 1, 1, 1, |
||||
1, 2, 1, 2, 2, 3, 3, 2, |
||||
1, 0, 2, 1, 1, 0, 1, 0, |
||||
0, 1, 0, 0, 1, 1, 0, 1, |
||||
}, |
||||
/* No CH2 */ |
||||
}; |
||||
|
||||
static const short (* const ddrphy_ip_dq_shift_val[DRAM_BOARD_NR])[32] = { |
||||
ddrphy_ip_dq_shift_val_ld20, /* LD20 reference */ |
||||
ddrphy_ip_dq_shift_val_ld20, /* LD20 TV */ |
||||
ddrphy_ip_dq_shift_val_ld20, /* LD20 TV C */ |
||||
ddrphy_ip_dq_shift_val_ld21, /* LD21 reference */ |
||||
ddrphy_ip_dq_shift_val_ld21, /* LD21 TV */ |
||||
}; |
||||
|
||||
static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane, |
||||
unsigned int bit) |
||||
{ |
||||
WARN_ON(lane >= 1 << PHY_LANE_SEL_LANE_WIDTH); |
||||
WARN_ON(bit >= 1 << PHY_LANE_SEL_BIT_WIDTH); |
||||
|
||||
writel((bit << PHY_LANE_SEL_BIT_SHIFT) | |
||||
(lane << PHY_LANE_SEL_LANE_SHIFT), |
||||
phy_base + PHY_LANE_SEL); |
||||
} |
||||
|
||||
#define DDRPHY_EFUSEMON (void *)0x5f900118 |
||||
|
||||
static void ddrphy_init(void __iomem *phy_base, enum dram_board board, int ch) |
||||
{ |
||||
writel(0x0C001001, phy_base + PHY_UNIQUIFY_TSMC_IO_1); |
||||
while (!(readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1))) |
||||
cpu_relax(); |
||||
|
||||
if (readl(DDRPHY_EFUSEMON) & BIT(ch)) |
||||
writel(0x00000000, phy_base + PHY_UNIQUIFY_TSMC_IO_1); |
||||
else |
||||
writel(0x0C001000, phy_base + PHY_UNIQUIFY_TSMC_IO_1); |
||||
|
||||
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3); |
||||
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1); |
||||
ddrphy_select_lane(phy_base, 0, 0); |
||||
writel(0x00000005, phy_base + PHY_DLL_TRIM_1); |
||||
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); |
||||
ddrphy_select_lane(phy_base, 6, 0); |
||||
writel(0x00000005, phy_base + PHY_DLL_TRIM_1); |
||||
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); |
||||
ddrphy_select_lane(phy_base, 12, 0); |
||||
writel(0x00000005, phy_base + PHY_DLL_TRIM_1); |
||||
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); |
||||
ddrphy_select_lane(phy_base, 18, 0); |
||||
writel(0x00000005, phy_base + PHY_DLL_TRIM_1); |
||||
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); |
||||
writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM); |
||||
writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1); |
||||
writel(ddrphy_phy_pad_ctrl[board][ch], phy_base + PHY_PAD_CTRL); |
||||
writel(0x00000070, phy_base + PHY_VREF_TRAINING); |
||||
writel(0x01000075, phy_base + PHY_SCL_CONFIG_1); |
||||
writel(0x00000501, phy_base + PHY_SCL_CONFIG_2); |
||||
writel(0x00000000, phy_base + PHY_SCL_CONFIG_3); |
||||
writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL); |
||||
writel(0x00000000, phy_base + PHY_SCL_CONFIG_4); |
||||
writel(ddrphy_scl_gate_timing[ch], phy_base + PHY_SCL_GATE_TIMING); |
||||
writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT); |
||||
writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF); |
||||
writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL); |
||||
ddrphy_select_lane(phy_base, 0, 0); |
||||
writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK); |
||||
writel(0xa800100d, phy_base + PHY_DLL_RECALIB); |
||||
writel(0x00005076, phy_base + PHY_SCL_LATENCY); |
||||
} |
||||
|
||||
static int ddrphy_to_dly_step(void __iomem *phy_base, unsigned int freq, |
||||
int delay) |
||||
{ |
||||
int mdl; |
||||
|
||||
mdl = (readl(phy_base + PHY_DLL_ADRCTRL) & PHY_DLL_ADRCTRL_MDL_MASK) >> |
||||
PHY_DLL_ADRCTRL_MDL_SHIFT; |
||||
|
||||
return DIV_ROUND_CLOSEST((long)freq * delay * mdl, 2 * 1000000L); |
||||
} |
||||
|
||||
static void ddrphy_set_delay(void __iomem *phy_base, unsigned int reg, |
||||
u32 mask, u32 incr, int dly_step) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
tmp = readl(phy_base + reg); |
||||
tmp &= ~mask; |
||||
tmp |= min_t(u32, abs(dly_step), mask); |
||||
|
||||
if (dly_step >= 0) |
||||
tmp |= incr; |
||||
else |
||||
tmp &= ~incr; |
||||
|
||||
writel(tmp, phy_base + reg); |
||||
} |
||||
|
||||
static void ddrphy_set_dll_recalib(void __iomem *phy_base, int dly_step) |
||||
{ |
||||
ddrphy_set_delay(phy_base, PHY_DLL_RECALIB, |
||||
PHY_DLL_RECALIB_TRIM_MASK, PHY_DLL_RECALIB_INCR, |
||||
dly_step); |
||||
} |
||||
|
||||
static void ddrphy_set_dll_adrctrl(void __iomem *phy_base, int dly_step) |
||||
{ |
||||
ddrphy_set_delay(phy_base, PHY_DLL_ADRCTRL, |
||||
PHY_DLL_ADRCTRL_TRIM_MASK, PHY_DLL_ADRCTRL_INCR, |
||||
dly_step); |
||||
} |
||||
|
||||
static void ddrphy_set_dll_trim_clk(void __iomem *phy_base, int dly_step) |
||||
{ |
||||
ddrphy_select_lane(phy_base, 0, 0); |
||||
|
||||
ddrphy_set_delay(phy_base, PHY_DLL_TRIM_CLK, |
||||
PHY_DLL_TRIM_CLK_MASK, PHY_DLL_TRIM_CLK_INCR, |
||||
dly_step); |
||||
} |
||||
|
||||
static void ddrphy_init_tail(void __iomem *phy_base, enum dram_board board, |
||||
unsigned int freq, int ch) |
||||
{ |
||||
int step; |
||||
|
||||
step = ddrphy_to_dly_step(phy_base, freq, ddrphy_adrctrl[board][ch]); |
||||
ddrphy_set_dll_adrctrl(phy_base, step); |
||||
|
||||
step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dlltrimclk[board][ch]); |
||||
ddrphy_set_dll_trim_clk(phy_base, step); |
||||
|
||||
step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dllrecalib[board][ch]); |
||||
ddrphy_set_dll_recalib(phy_base, step); |
||||
} |
||||
|
||||
static void ddrphy_shift_one_dq(void __iomem *phy_base, unsigned int reg, |
||||
u32 mask, u32 incr, short shift_val) |
||||
{ |
||||
u32 tmp; |
||||
int val; |
||||
|
||||
tmp = readl(phy_base + reg); |
||||
|
||||
val = tmp & mask; |
||||
if (!(tmp & incr)) |
||||
val = -val; |
||||
|
||||
val += shift_val; |
||||
|
||||
tmp &= ~(incr | mask); |
||||
tmp |= min_t(u32, abs(val), mask); |
||||
if (val >= 0) |
||||
tmp |= incr; |
||||
|
||||
writel(tmp, phy_base + reg); |
||||
} |
||||
|
||||
static void ddrphy_shift_dq(void __iomem *phy_base, unsigned int reg, |
||||
u32 mask, u32 incr, u32 override, |
||||
const short *shift_val_array) |
||||
{ |
||||
u32 tmp; |
||||
int dx, bit; |
||||
|
||||
tmp = readl(phy_base + reg); |
||||
tmp |= override; |
||||
writel(tmp, phy_base + reg); |
||||
|
||||
for (dx = 0; dx < 4; dx++) { |
||||
for (bit = 0; bit < 8; bit++) { |
||||
ddrphy_select_lane(phy_base, |
||||
(PHY_BITLVL_DLY_WIDTH + 1) * dx, |
||||
bit); |
||||
|
||||
ddrphy_shift_one_dq(phy_base, reg, mask, incr, |
||||
shift_val_array[dx * 8 + bit]); |
||||
} |
||||
} |
||||
|
||||
ddrphy_select_lane(phy_base, 0, 0); |
||||
} |
||||
|
||||
static int ddrphy_training(void __iomem *phy_base, enum dram_board board, |
||||
int ch) |
||||
{ |
||||
writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM); |
||||
writel(0x00010000, phy_base + PHY_DLL_TRIM_2); |
||||
writel(0x50000000, phy_base + PHY_SCL_START); |
||||
|
||||
while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE) |
||||
cpu_relax(); |
||||
|
||||
writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL); |
||||
writel(0xff00ff00, phy_base + PHY_SCL_DATA_0); |
||||
writel(0xff00ff00, phy_base + PHY_SCL_DATA_1); |
||||
writel(0xFBF8FFFF, phy_base + PHY_SCL_START_ADDR); |
||||
writel(0x11000000, phy_base + PHY_SCL_START); |
||||
|
||||
while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE) |
||||
cpu_relax(); |
||||
|
||||
writel(0xFBF0FFFF, phy_base + PHY_SCL_START_ADDR); |
||||
writel(0x30500000, phy_base + PHY_SCL_START); |
||||
|
||||
while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE) |
||||
cpu_relax(); |
||||
|
||||
writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL); |
||||
writel(0x00000010, phy_base + PHY_SCL_MAIN_CLK_DELTA); |
||||
writel(0x789b3de0, phy_base + PHY_SCL_DATA_0); |
||||
writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1); |
||||
writel(0x11000000, phy_base + PHY_SCL_START); |
||||
|
||||
while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE) |
||||
cpu_relax(); |
||||
|
||||
writel(0x34000000, phy_base + PHY_SCL_START); |
||||
|
||||
while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE) |
||||
cpu_relax(); |
||||
|
||||
writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL); |
||||
|
||||
writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL); |
||||
writel(0x00003270, phy_base + PHY_DYNAMIC_BIT_LVL); |
||||
writel(0x011BD0C4, phy_base + PHY_DSCL_CNT); |
||||
|
||||
/* shift ip_dq trim */ |
||||
ddrphy_shift_dq(phy_base, |
||||
PHY_IP_DQ_DQS_BITWISE_TRIM, |
||||
PHY_IP_DQ_DQS_BITWISE_TRIM_MASK, |
||||
PHY_IP_DQ_DQS_BITWISE_TRIM_INC, |
||||
PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE, |
||||
ddrphy_ip_dq_shift_val[board][ch]); |
||||
|
||||
/* shift op_dq trim */ |
||||
ddrphy_shift_dq(phy_base, |
||||
PHY_OP_DQ_DM_DQS_BITWISE_TRIM, |
||||
PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK, |
||||
PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC, |
||||
PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE, |
||||
ddrphy_op_dq_shift_val[board][ch]); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* UMC */ |
||||
static const u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11}; |
||||
static const u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC}; |
||||
static const u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF}; |
||||
static const u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114}; |
||||
static const u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0}; |
||||
|
||||
static const u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = { |
||||
/* 256MB 512MB */ |
||||
{0x00000601, 0x00000801}, /* 1866 MHz */ |
||||
}; |
||||
|
||||
static const u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = { |
||||
/* 256MB 512MB */ |
||||
{0x00000120, 0x00000130}, /* 1866 MHz */ |
||||
}; |
||||
|
||||
static const u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = { |
||||
/* 256MB 512MB */ |
||||
{0x00033603, 0x00033803}, /* 1866 MHz */ |
||||
}; |
||||
|
||||
static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20}; |
||||
static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08}; |
||||
static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04}; |
||||
static const u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = { |
||||
/* 256MB 512MB */ |
||||
{0x0049071D, 0x0078071D}, /* 1866 MHz */ |
||||
}; |
||||
|
||||
static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000610}; |
||||
static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000204}; |
||||
static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002}; |
||||
static const u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000}; |
||||
|
||||
static const u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E}; |
||||
static const u32 umc_directbusctrla[DRAM_CH_NR] = { |
||||
0x00000000, 0x00000001, 0x00000001 |
||||
}; |
||||
|
||||
static void umc_poll_phy_init_complete(void __iomem *dc_base) |
||||
{ |
||||
/* Wait for PHY Init Complete */ |
||||
while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0))) |
||||
cpu_relax(); |
||||
} |
||||
|
||||
static int umc_dc_init(void __iomem *dc_base, unsigned int freq, |
||||
unsigned long size, int ch) |
||||
{ |
||||
enum dram_freq freq_e; |
||||
enum dram_size size_e; |
||||
|
||||
switch (freq) { |
||||
case 1866: |
||||
freq_e = DRAM_FREQ_1866M; |
||||
break; |
||||
default: |
||||
pr_err("unsupported DRAM frequency %ud MHz\n", freq); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
switch (size) { |
||||
case 0: |
||||
return 0; |
||||
case SZ_256M: |
||||
size_e = DRAM_SZ_256M; |
||||
break; |
||||
case SZ_512M: |
||||
size_e = DRAM_SZ_512M; |
||||
break; |
||||
default: |
||||
pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n", |
||||
size, ch); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
writel(0x00000001, dc_base + UMC_DFICSOVRRD); |
||||
writel(0x00000000, dc_base + UMC_DFITURNOFF); |
||||
|
||||
writel(umc_initctla[freq_e], dc_base + UMC_INITCTLA); |
||||
writel(umc_initctlb[freq_e], dc_base + UMC_INITCTLB); |
||||
writel(umc_initctlc[freq_e], dc_base + UMC_INITCTLC); |
||||
|
||||
writel(umc_drmmr0[freq_e], dc_base + UMC_DRMMR0); |
||||
writel(0x00000004, dc_base + UMC_DRMMR1); |
||||
writel(umc_drmmr2[freq_e], dc_base + UMC_DRMMR2); |
||||
writel(0x00000000, dc_base + UMC_DRMMR3); |
||||
|
||||
writel(umc_memconf0a[freq_e][size_e], dc_base + UMC_MEMCONF0A); |
||||
writel(umc_memconf0b[freq_e][size_e], dc_base + UMC_MEMCONF0B); |
||||
writel(umc_memconfch[freq_e][size_e], dc_base + UMC_MEMCONFCH); |
||||
writel(0x00000000, dc_base + UMC_MEMMAPSET); |
||||
|
||||
writel(umc_cmdctla[freq_e], dc_base + UMC_CMDCTLA); |
||||
writel(umc_cmdctlb[freq_e], dc_base + UMC_CMDCTLB); |
||||
writel(umc_cmdctlc[freq_e], dc_base + UMC_CMDCTLC); |
||||
writel(umc_cmdctle[freq_e][size_e], dc_base + UMC_CMDCTLE); |
||||
|
||||
writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0); |
||||
writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D1); |
||||
|
||||
writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D0); |
||||
writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D1); |
||||
writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D0); |
||||
writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D1); |
||||
writel(umc_dataset[freq_e], dc_base + UMC_DATASET); |
||||
|
||||
writel(0x00400020, dc_base + UMC_DCCGCTL); |
||||
writel(0x00000003, dc_base + UMC_ACSSETA); |
||||
writel(0x00000103, dc_base + UMC_FLOWCTLG); |
||||
writel(0x00010200, dc_base + UMC_ACSSETB); |
||||
|
||||
writel(umc_flowctla[freq_e], dc_base + UMC_FLOWCTLA); |
||||
writel(0x00004444, dc_base + UMC_FLOWCTLC); |
||||
writel(0x00000000, dc_base + UMC_DFICUPDCTLA); |
||||
|
||||
writel(0x00202000, dc_base + UMC_FLOWCTLB); |
||||
writel(0x00000000, dc_base + UMC_BSICMAPSET); |
||||
writel(0x00000000, dc_base + UMC_ERRMASKA); |
||||
writel(0x00000000, dc_base + UMC_ERRMASKB); |
||||
|
||||
writel(umc_directbusctrla[ch], dc_base + UMC_DIRECTBUSCTRLA); |
||||
|
||||
writel(0x00000001, dc_base + UMC_INITSET); |
||||
/* Wait for PHY Init Complete */ |
||||
while (readl(dc_base + UMC_INITSTAT) & BIT(0)) |
||||
cpu_relax(); |
||||
|
||||
writel(0x2A0A0A00, dc_base + UMC_SPCSETB); |
||||
writel(0x00000000, dc_base + UMC_DFICSOVRRD); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base, |
||||
enum dram_board board, unsigned int freq, |
||||
unsigned long size, int ch) |
||||
{ |
||||
void __iomem *dc_base = umc_ch_base + 0x00011000; |
||||
void __iomem *phy_base = phy_ch_base; |
||||
int ret; |
||||
|
||||
/* PHY Update Mode (ON) */ |
||||
writel(0x8000003f, dc_base + UMC_DFIPUPDCTLA); |
||||
|
||||
/* deassert PHY reset signals */ |
||||
writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST, |
||||
dc_base + UMC_DIOCTLA); |
||||
|
||||
ddrphy_init(phy_base, board, ch); |
||||
|
||||
umc_poll_phy_init_complete(dc_base); |
||||
|
||||
ddrphy_init_tail(phy_base, board, freq, ch); |
||||
|
||||
ret = umc_dc_init(dc_base, freq, size, ch); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
ret = ddrphy_training(phy_base, board, ch); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void um_init(void __iomem *um_base) |
||||
{ |
||||
writel(0x000000ff, um_base + UMC_MBUS0); |
||||
writel(0x000000ff, um_base + UMC_MBUS1); |
||||
writel(0x000000ff, um_base + UMC_MBUS2); |
||||
writel(0x00000001, um_base + UMC_MBUS3); |
||||
writel(0x00000001, um_base + UMC_MBUS4); |
||||
writel(0x00000001, um_base + UMC_MBUS5); |
||||
writel(0x00000001, um_base + UMC_MBUS6); |
||||
writel(0x00000001, um_base + UMC_MBUS7); |
||||
writel(0x00000001, um_base + UMC_MBUS8); |
||||
writel(0x00000001, um_base + UMC_MBUS9); |
||||
writel(0x00000001, um_base + UMC_MBUS10); |
||||
} |
||||
|
||||
int uniphier_ld20_umc_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
void __iomem *um_base = (void __iomem *)0x5b600000; |
||||
void __iomem *umc_ch_base = (void __iomem *)0x5b800000; |
||||
void __iomem *phy_ch_base = (void __iomem *)0x6e200000; |
||||
enum dram_board board; |
||||
int ch, ret; |
||||
|
||||
switch (UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)) { |
||||
case UNIPHIER_BD_BOARD_LD20_REF: |
||||
board = DRAM_BOARD_LD20_REF; |
||||
break; |
||||
case UNIPHIER_BD_BOARD_LD20_GLOBAL: |
||||
board = DRAM_BOARD_LD20_GLOBAL; |
||||
break; |
||||
case UNIPHIER_BD_BOARD_LD20_C1: |
||||
board = DRAM_BOARD_LD20_C1; |
||||
break; |
||||
case UNIPHIER_BD_BOARD_LD21_REF: |
||||
board = DRAM_BOARD_LD21_REF; |
||||
break; |
||||
case UNIPHIER_BD_BOARD_LD21_GLOBAL: |
||||
board = DRAM_BOARD_LD21_GLOBAL; |
||||
break; |
||||
default: |
||||
pr_err("unsupported board type %d\n", |
||||
UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
for (ch = 0; ch < DRAM_CH_NR; ch++) { |
||||
unsigned long size = bd->dram_ch[ch].size; |
||||
unsigned int width = bd->dram_ch[ch].width; |
||||
|
||||
if (size) { |
||||
ret = umc_ch_init(umc_ch_base, phy_ch_base, board, |
||||
bd->dram_freq, size / (width / 16), |
||||
ch); |
||||
if (ret) { |
||||
pr_err("failed to initialize UMC ch%d\n", ch); |
||||
return ret; |
||||
} |
||||
} |
||||
|
||||
umc_ch_base += 0x00200000; |
||||
phy_ch_base += 0x00004000; |
||||
} |
||||
|
||||
um_init(um_base); |
||||
|
||||
return 0; |
||||
} |
||||
@ -1,85 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
*/ |
||||
|
||||
#ifndef UMC_LD20_REGS_H |
||||
#define UMC_LD20_REGS_H |
||||
|
||||
#define UMC_CMDCTLA 0x00000000 |
||||
#define UMC_CMDCTLB 0x00000004 |
||||
#define UMC_CMDCTLC 0x00000008 |
||||
#define UMC_INITCTLA 0x00000020 |
||||
#define UMC_INITCTLB 0x00000024 |
||||
#define UMC_INITCTLC 0x00000028 |
||||
#define UMC_DRMMR0 0x00000030 |
||||
#define UMC_DRMMR1 0x00000034 |
||||
#define UMC_DRMMR2 0x00000038 |
||||
#define UMC_DRMMR3 0x0000003C |
||||
#define UMC_INITSET 0x00000040 |
||||
#define UMC_INITSTAT 0x00000044 |
||||
#define UMC_CMDCTLE 0x00000050 |
||||
#define UMC_CMDCTLF 0x00000054 |
||||
#define UMC_CMDCTLG 0x00000058 |
||||
#define UMC_SPCSETB 0x00000084 |
||||
#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ |
||||
#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ |
||||
#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ |
||||
#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ |
||||
#define UMC_ACSSETA 0x000000C0 |
||||
#define UMC_ACSSETB 0x000000C4 |
||||
#define UMC_MEMCONF0A 0x00000200 |
||||
#define UMC_MEMCONF0B 0x00000204 |
||||
#define UMC_MEMCONFCH 0x00000240 |
||||
#define UMC_MEMMAPSET 0x00000250 |
||||
#define UMC_FLOWCTLA 0x00000400 |
||||
#define UMC_FLOWCTLB 0x00000404 |
||||
#define UMC_FLOWCTLC 0x00000408 |
||||
#define UMC_ACFETCHCTRL 0x00000460 |
||||
#define UMC_FLOWCTLG 0x00000508 |
||||
#define UMC_RDATACTL_D0 0x00000600 |
||||
#define UMC_WDATACTL_D0 0x00000604 |
||||
#define UMC_RDATACTL_D1 0x00000608 |
||||
#define UMC_WDATACTL_D1 0x0000060C |
||||
#define UMC_DATASET 0x00000610 |
||||
#define UMC_ODTCTL_D0 0x00000618 |
||||
#define UMC_ODTCTL_D1 0x0000061C |
||||
#define UMC_RESPCTL 0x00000624 |
||||
#define UMC_DIRECTBUSCTRLA 0x00000680 |
||||
#define UMC_DEBUGC 0x00000718 |
||||
#define UMC_DCCGCTL 0x00000720 |
||||
#define UMC_DICGCTLA 0x00000724 |
||||
#define UMC_DICGCTLB 0x00000728 |
||||
#define UMC_ERRMASKA 0x00000958 |
||||
#define UMC_ERRMASKB 0x0000095C |
||||
#define UMC_BSICMAPSET 0x00000988 |
||||
#define UMC_DIOCTLA 0x00000C00 |
||||
#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ |
||||
#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ |
||||
#define UMC_DFISTCTLC 0x00000C18 |
||||
#define UMC_DFICUPDCTLA 0x00000C20 |
||||
#define UMC_DFIPUPDCTLA 0x00000C30 |
||||
#define UMC_DFICSOVRRD 0x00000C84 |
||||
#define UMC_DFITURNOFF 0x00000C88 |
||||
|
||||
/* UM registers */ |
||||
#define UMC_MBUS0 0x00080004 |
||||
#define UMC_MBUS1 0x00081004 |
||||
#define UMC_MBUS2 0x00082004 |
||||
#define UMC_MBUS3 0x00000C78 |
||||
#define UMC_MBUS4 0x00000CF8 |
||||
#define UMC_MBUS5 0x00000E78 |
||||
#define UMC_MBUS6 0x00000EF8 |
||||
#define UMC_MBUS7 0x00001278 |
||||
#define UMC_MBUS8 0x000012F8 |
||||
#define UMC_MBUS9 0x00002478 |
||||
#define UMC_MBUS10 0x000024F8 |
||||
|
||||
/* UMC1 register */ |
||||
#define UMC_SIORST 0x00000728 |
||||
#define UMC_VO0RST 0x0000073c |
||||
#define UMC_VPERST 0x00000744 |
||||
#define UMC_RGLRST 0x00000750 |
||||
#define UMC_A2DRST 0x00000764 |
||||
#define UMC_DMDRST 0x00000770 |
||||
|
||||
#endif /* UMC_LD20_REGS_H */ |
||||
@ -1,41 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_UNIPHIER=y |
||||
CONFIG_SYS_TEXT_BASE=0x84000000 |
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000 |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_ARCH_UNIPHIER_LD11_SINGLE=y |
||||
CONFIG_MICRO_SUPPORT_CARD=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld11-ref" |
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_NOR_SUPPORT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_CONFIG=y |
||||
# CONFIG_CMD_XIMG is not set |
||||
# CONFIG_CMD_ENV_EXISTS is not set |
||||
CONFIG_CMD_GPT=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_USB=y |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_TFTPPUT=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_TIME=y |
||||
# CONFIG_CMD_MISC is not set |
||||
CONFIG_CMD_FAT=y |
||||
# CONFIG_SPL_DOS_PARTITION is not set |
||||
# CONFIG_SPL_EFI_PARTITION is not set |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_SPL_OF_TRANSLATE=y |
||||
CONFIG_GPIO_UNIPHIER=y |
||||
CONFIG_MISC=y |
||||
CONFIG_I2C_EEPROM=y |
||||
CONFIG_MMC_SDHCI=y |
||||
CONFIG_MMC_SDHCI_SDMA=y |
||||
CONFIG_MMC_SDHCI_CADENCE=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_EHCI_HCD=y |
||||
CONFIG_USB_EHCI_GENERIC=y |
||||
CONFIG_USB_STORAGE=y |
||||
@ -1,40 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_UNIPHIER=y |
||||
CONFIG_SYS_TEXT_BASE=0x84000000 |
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000 |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_ARCH_UNIPHIER_LD20_SINGLE=y |
||||
CONFIG_MICRO_SUPPORT_CARD=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref" |
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_NOR_SUPPORT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_CONFIG=y |
||||
# CONFIG_CMD_XIMG is not set |
||||
# CONFIG_CMD_ENV_EXISTS is not set |
||||
CONFIG_CMD_GPT=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_USB=y |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_TFTPPUT=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_TIME=y |
||||
# CONFIG_CMD_MISC is not set |
||||
CONFIG_CMD_FAT=y |
||||
# CONFIG_SPL_DOS_PARTITION is not set |
||||
# CONFIG_SPL_EFI_PARTITION is not set |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_SPL_OF_TRANSLATE=y |
||||
CONFIG_GPIO_UNIPHIER=y |
||||
CONFIG_MISC=y |
||||
CONFIG_I2C_EEPROM=y |
||||
CONFIG_MMC_UNIPHIER=y |
||||
CONFIG_MMC_SDHCI=y |
||||
CONFIG_MMC_SDHCI_CADENCE=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_XHCI_HCD=y |
||||
CONFIG_USB_STORAGE=y |
||||
Loading…
Reference in new issue