zipitz2 was dropped in 49d8899ba9
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
master
parent
9caeb26c54
commit
f19eb15426
@ -0,0 +1,9 @@ |
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if TARGET_ZIPITZ2 |
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config SYS_BOARD |
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default "zipitz2" |
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config SYS_CONFIG_NAME |
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default "zipitz2" |
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endif |
@ -0,0 +1,6 @@ |
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ZIPITZ2 BOARD |
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M: Vasily Khoruzhick <anarsoul@gmail.com> |
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S: Maintained |
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F: board/zipitz2/ |
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F: include/configs/zipitz2.h |
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F: configs/zipitz2_defconfig |
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#
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# Copyright (C) 2009
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# Marek Vasut <marek.vasut@gmail.com>
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#
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# Heavily based on pxa255_idp platform
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := zipitz2.o
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/*
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* Copyright (C) 2009 |
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* Marek Vasut <marek.vasut@gmail.com> |
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* |
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* Heavily based on pxa255_idp platform |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <serial.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/pxa.h> |
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#include <asm/arch/regs-mmc.h> |
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#include <spi.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#ifdef CONFIG_CMD_SPI |
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void lcd_start(void); |
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#else |
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inline void lcd_start(void) {}; |
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#endif |
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/*
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* Miscelaneous platform dependent initialisations |
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*/ |
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int board_init(void) |
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{ |
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/* We have RAM, disable cache */ |
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dcache_disable(); |
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icache_disable(); |
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/* arch number of Z2 */ |
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gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = 0xa0000100; |
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/* Enable LCD */ |
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lcd_start(); |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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pxa2xx_dram_init(); |
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gd->ram_size = PHYS_SDRAM_1_SIZE; |
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return 0; |
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} |
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void dram_init_banksize(void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
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} |
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#ifdef CONFIG_CMD_MMC |
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int board_mmc_init(bd_t *bis) |
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{ |
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pxa_mmc_register(0); |
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return 0; |
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} |
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#endif |
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#ifdef CONFIG_CMD_SPI |
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struct { |
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unsigned char reg; |
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unsigned short data; |
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unsigned char mdelay; |
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} lcd_data[] = { |
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{ 0x07, 0x0000, 0 }, |
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{ 0x13, 0x0000, 10 }, |
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{ 0x11, 0x3004, 0 }, |
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{ 0x14, 0x200F, 0 }, |
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{ 0x10, 0x1a20, 0 }, |
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{ 0x13, 0x0040, 50 }, |
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{ 0x13, 0x0060, 0 }, |
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{ 0x13, 0x0070, 200 }, |
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{ 0x01, 0x0127, 0 }, |
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{ 0x02, 0x0700, 0 }, |
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{ 0x03, 0x1030, 0 }, |
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{ 0x08, 0x0208, 0 }, |
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{ 0x0B, 0x0620, 0 }, |
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{ 0x0C, 0x0110, 0 }, |
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{ 0x30, 0x0120, 0 }, |
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{ 0x31, 0x0127, 0 }, |
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{ 0x32, 0x0000, 0 }, |
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{ 0x33, 0x0503, 0 }, |
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{ 0x34, 0x0727, 0 }, |
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{ 0x35, 0x0124, 0 }, |
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{ 0x36, 0x0706, 0 }, |
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{ 0x37, 0x0701, 0 }, |
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{ 0x38, 0x0F00, 0 }, |
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{ 0x39, 0x0F00, 0 }, |
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{ 0x40, 0x0000, 0 }, |
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{ 0x41, 0x0000, 0 }, |
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{ 0x42, 0x013f, 0 }, |
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{ 0x43, 0x0000, 0 }, |
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{ 0x44, 0x013f, 0 }, |
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{ 0x45, 0x0000, 0 }, |
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{ 0x46, 0xef00, 0 }, |
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{ 0x47, 0x013f, 0 }, |
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{ 0x48, 0x0000, 0 }, |
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{ 0x07, 0x0015, 30 }, |
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{ 0x07, 0x0017, 0 }, |
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{ 0x20, 0x0000, 0 }, |
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{ 0x21, 0x0000, 0 }, |
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{ 0x22, 0x0000, 0 }, |
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}; |
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void zipitz2_spi_sda(int set) |
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{ |
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/* GPIO 13 */ |
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if (set) |
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writel((1 << 13), GPSR0); |
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else |
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writel((1 << 13), GPCR0); |
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} |
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void zipitz2_spi_scl(int set) |
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{ |
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/* GPIO 22 */ |
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if (set) |
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writel((1 << 22), GPCR0); |
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else |
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writel((1 << 22), GPSR0); |
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} |
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unsigned char zipitz2_spi_read(void) |
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{ |
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/* GPIO 40 */ |
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return !!(readl(GPLR1) & (1 << 8)); |
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} |
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int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
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{ |
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/* Always valid */ |
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return 1; |
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} |
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void spi_cs_activate(struct spi_slave *slave) |
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{ |
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/* GPIO 88 low */ |
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writel((1 << 24), GPCR2); |
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} |
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void spi_cs_deactivate(struct spi_slave *slave) |
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{ |
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/* GPIO 88 high */ |
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writel((1 << 24), GPSR2); |
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} |
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void lcd_start(void) |
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{ |
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int i; |
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unsigned char reg[3] = { 0x74, 0x00, 0 }; |
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unsigned char data[3] = { 0x76, 0, 0 }; |
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unsigned char dummy[3] = { 0, 0, 0 }; |
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/* PWM2 AF */ |
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writel(readl(GAFR0_L) | 0x00800000, GAFR0_L); |
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/* Enable clock to all PWM */ |
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writel(readl(CKEN) | 0x3, CKEN); |
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/* Configure PWM2 */ |
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writel(0x4f, PWM_CTRL2); |
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writel(0x2ff, PWM_PWDUTY2); |
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writel(792, PWM_PERVAL2); |
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/* Toggle the reset pin to reset the LCD */ |
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writel((1 << 19), GPSR0); |
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udelay(100000); |
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writel((1 << 19), GPCR0); |
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udelay(20000); |
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writel((1 << 19), GPSR0); |
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udelay(20000); |
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/* Program the LCD init sequence */ |
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for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) { |
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reg[0] = 0x74; |
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reg[1] = 0x0; |
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reg[2] = lcd_data[i].reg; |
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spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END); |
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data[0] = 0x76; |
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data[1] = lcd_data[i].data >> 8; |
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data[2] = lcd_data[i].data & 0xff; |
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spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END); |
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if (lcd_data[i].mdelay) |
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udelay(lcd_data[i].mdelay * 1000); |
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} |
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writel((1 << 11), GPSR0); |
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} |
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#endif |
@ -0,0 +1,7 @@ |
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CONFIG_ARM=y |
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CONFIG_TARGET_ZIPITZ2=y |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_SETEXPR is not set |
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# CONFIG_CMD_NET is not set |
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# CONFIG_CMD_NFS is not set |
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CONFIG_SYS_PROMPT="$ " |
@ -0,0 +1,224 @@ |
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/*
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* Aeronix Zipit Z2 configuration file |
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* |
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* Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Board Configuration Options |
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*/ |
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#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ |
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#define CONFIG_SYS_TEXT_BASE 0x0 |
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#undef CONFIG_BOARD_LATE_INIT |
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#undef CONFIG_SKIP_LOWLEVEL_INIT |
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#define CONFIG_PREBOOT |
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/*
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* Environment settings |
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*/ |
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#define CONFIG_ENV_OVERWRITE |
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#define CONFIG_ENV_IS_IN_FLASH 1 |
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#define CONFIG_ENV_ADDR 0x40000 |
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#define CONFIG_ENV_SIZE 0x10000 |
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#define CONFIG_SYS_DCACHE_OFF |
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#define CONFIG_SYS_MALLOC_LEN (128*1024) |
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#define CONFIG_ARCH_CPU_INIT |
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#define CONFIG_BOOTCOMMAND \ |
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"if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
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"then " \
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"source 0xa0000000; " \
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"else " \
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"bootm 0x50000; " \
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"fi; " |
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#define CONFIG_BOOTARGS \ |
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"console=tty0 console=ttyS2,115200 fbcon=rotate:3" |
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#define CONFIG_TIMESTAMP |
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#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ |
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#define CONFIG_CMDLINE_TAG |
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#define CONFIG_SETUP_MEMORY_TAGS |
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#define CONFIG_SYS_TEXT_BASE 0x0 |
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#define CONFIG_LZMA /* LZMA compression support */ |
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/*
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* Serial Console Configuration |
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* STUART - the lower serial port on Colibri board |
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*/ |
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#define CONFIG_PXA_SERIAL |
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#define CONFIG_STUART 1 |
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#define CONFIG_CONS_INDEX 2 |
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#define CONFIG_BAUDRATE 115200 |
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/*
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* Bootloader Components Configuration |
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*/ |
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#define CONFIG_CMD_ENV |
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#define CONFIG_CMD_MMC |
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#define CONFIG_CMD_SPI |
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/*
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* MMC Card Configuration |
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*/ |
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#ifdef CONFIG_CMD_MMC |
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#define CONFIG_MMC |
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#define CONFIG_GENERIC_MMC |
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#define CONFIG_PXA_MMC_GENERIC |
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#define CONFIG_SYS_MMC_BASE 0xF0000000 |
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#define CONFIG_CMD_FAT |
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#define CONFIG_CMD_EXT2 |
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#define CONFIG_DOS_PARTITION |
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#endif |
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/*
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* SPI and LCD |
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*/ |
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#ifdef CONFIG_CMD_SPI |
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#define CONFIG_SOFT_SPI |
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#define CONFIG_LCD |
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#define CONFIG_PXA_LCD |
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#define CONFIG_LMS283GF05 |
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#define SPI_DELAY udelay(10) |
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#define SPI_SDA(val) zipitz2_spi_sda(val) |
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#define SPI_SCL(val) zipitz2_spi_scl(val) |
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#define SPI_READ zipitz2_spi_read() |
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#ifndef __ASSEMBLY__ |
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void zipitz2_spi_sda(int); |
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void zipitz2_spi_scl(int); |
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unsigned char zipitz2_spi_read(void); |
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#endif |
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#endif |
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/*
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* HUSH Shell Configuration |
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*/ |
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#define CONFIG_SYS_HUSH_PARSER 1 |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_DEVICE_NULLDEV 1 |
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/*
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* Clock Configuration |
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*/ |
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#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ |
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/*
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* SRAM Map |
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*/ |
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#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ |
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#define PHYS_SRAM_SIZE 0x00040000 /* 256k */ |
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/*
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* DRAM Map |
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*/ |
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#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ |
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
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#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
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#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ |
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#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ |
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#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
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#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ |
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE |
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
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#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) |
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/*
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* NOR FLASH |
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*/ |
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
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#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ |
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#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ |
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
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#define CONFIG_SYS_FLASH_CFI |
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#define CONFIG_FLASH_CFI_DRIVER 1 |
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
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#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
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#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
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#define CONFIG_SYS_MAX_FLASH_SECT 256 |
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
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#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 |
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#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 |
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#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 |
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 |
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#define CONFIG_SYS_FLASH_PROTECTION |
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/*
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* GPIO settings |
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*/ |
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#define CONFIG_SYS_GAFR0_L_VAL 0x02000140 |
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#define CONFIG_SYS_GAFR0_U_VAL 0x59188000 |
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#define CONFIG_SYS_GAFR1_L_VAL 0x63900002 |
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#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 |
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#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa |
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#define CONFIG_SYS_GAFR2_U_VAL 0x29000308 |
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#define CONFIG_SYS_GAFR3_L_VAL 0x54000000 |
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#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 |
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#define CONFIG_SYS_GPCR0_VAL 0x00000000 |
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#define CONFIG_SYS_GPCR1_VAL 0x00000020 |
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#define CONFIG_SYS_GPCR2_VAL 0x00000000 |
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#define CONFIG_SYS_GPCR3_VAL 0x00000000 |
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#define CONFIG_SYS_GPDR0_VAL 0xdafcee00 |
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#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab |
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#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff |
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#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a |
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#define CONFIG_SYS_GPSR0_VAL 0x06080400 |
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#define CONFIG_SYS_GPSR1_VAL 0x007f0000 |
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#define CONFIG_SYS_GPSR2_VAL 0x032a0000 |
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#define CONFIG_SYS_GPSR3_VAL 0x00000180 |
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#define CONFIG_SYS_PSSR_VAL 0x30 |
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/*
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* Clock settings |
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*/ |
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#define CONFIG_SYS_CKEN 0x00511220 |
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#define CONFIG_SYS_CCCR 0x00000190 |
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/*
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* Memory settings |
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*/ |
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#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 |
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#define CONFIG_SYS_MSC1_VAL 0x0000ccd1 |
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#define CONFIG_SYS_MSC2_VAL 0x0000b884 |
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#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 |
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#define CONFIG_SYS_MDREFR_VAL 0x2011a01e |
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#define CONFIG_SYS_MDMRS_VAL 0x00000000 |
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#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 |
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#define CONFIG_SYS_SXCNFG_VAL 0x40044004 |
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/*
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* PCMCIA and CF Interfaces |
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*/ |
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#define CONFIG_SYS_MECR_VAL 0x00000001 |
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#define CONFIG_SYS_MCMEM0_VAL 0x00014307 |
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#define CONFIG_SYS_MCMEM1_VAL 0x00014307 |
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#define CONFIG_SYS_MCATT0_VAL 0x0001c787 |
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#define CONFIG_SYS_MCATT1_VAL 0x0001c787 |
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#define CONFIG_SYS_MCIO0_VAL 0x0001430f |
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#define CONFIG_SYS_MCIO1_VAL 0x0001430f |
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#include "pxa-common.h" |
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#endif /* __CONFIG_H */ |
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