@ -145,18 +145,18 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
. sdram_tim1 = 0xCCCF36B3 ,
. sdram_tim2 = 0x308F7FDA ,
. sdram_tim3 = 0x027F88A8 ,
. read_idle_ctrl = 0x00050000 ,
. read_idle_ctrl = 0x00050001 ,
. zq_config = 0x0007190B ,
. temp_alert_config = 0x00000000 ,
. emif_ddr_phy_ctlr_1_init = 0x00 24400A ,
. emif_ddr_phy_ctlr_1 = 0x00 24400A ,
. emif_ddr_phy_ctlr_1_init = 0x0E 24400A ,
. emif_ddr_phy_ctlr_1 = 0x0E 24400A ,
. emif_ddr_ext_phy_ctrl_1 = 0x10040100 ,
. emif_ddr_ext_phy_ctrl_2 = 0x00B000B0 ,
. emif_ddr_ext_phy_ctrl_3 = 0x00B000B0 ,
. emif_ddr_ext_phy_ctrl_4 = 0x00B000B0 ,
. emif_ddr_ext_phy_ctrl_5 = 0x00B000B0 ,
. emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB ,
. emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB ,
. emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB ,
. emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB ,
. emif_rd_wr_lvl_rmp_win = 0x00000000 ,
. emif_rd_wr_lvl_rmp_ctl = 0x8 0000000 ,
. emif_rd_wr_lvl_rmp_ctl = 0x0 0000000 ,
. emif_rd_wr_lvl_ctl = 0x00000000 ,
. emif_rd_wr_exec_thresh = 0x00000305
} ;
@ -169,18 +169,18 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
. sdram_tim1 = 0xCCCF36B3 ,
. sdram_tim2 = 0x308F7FDA ,
. sdram_tim3 = 0x027F88A8 ,
. read_idle_ctrl = 0x00050000 ,
. read_idle_ctrl = 0x00050001 ,
. zq_config = 0x0007190B ,
. temp_alert_config = 0x00000000 ,
. emif_ddr_phy_ctlr_1_init = 0x00 24400A ,
. emif_ddr_phy_ctlr_1 = 0x00 24400A ,
. emif_ddr_phy_ctlr_1_init = 0x0E 24400A ,
. emif_ddr_phy_ctlr_1 = 0x0E 24400A ,
. emif_ddr_ext_phy_ctrl_1 = 0x10040100 ,
. emif_ddr_ext_phy_ctrl_2 = 0x00B000B0 ,
. emif_ddr_ext_phy_ctrl_3 = 0x00B000B0 ,
. emif_ddr_ext_phy_ctrl_4 = 0x00B000B0 ,
. emif_ddr_ext_phy_ctrl_5 = 0x00B000B0 ,
. emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB ,
. emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB ,
. emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB ,
. emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB ,
. emif_rd_wr_lvl_rmp_win = 0x00000000 ,
. emif_rd_wr_lvl_rmp_ctl = 0x8 0000000 ,
. emif_rd_wr_lvl_rmp_ctl = 0x0 0000000 ,
. emif_rd_wr_lvl_ctl = 0x00000000 ,
. emif_rd_wr_exec_thresh = 0x00000305
} ;
@ -394,24 +394,24 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1 [ ] = {
0x00B000B0 ,
0x00400040 ,
0x00400040 ,
0x00400040 ,
0x00400040 ,
0x00400040 ,
0x00800080 ,
0x00800080 ,
0x00800080 ,
0x00800080 ,
0x00800080 ,
0x00BB00BB ,
0x00440044 ,
0x00440044 ,
0x00440044 ,
0x00440044 ,
0x00440044 ,
0x007F007F ,
0x007F007F ,
0x007F007F ,
0x007F007F ,
0x007F007F ,
0x00600060 ,
0x00600060 ,
0x00600060 ,
0x00600060 ,
0x00600060 ,
0x0080008 0 ,
0x0080008 0 ,
0x0000000 0 ,
0x0060002 0 ,
0x40010080 ,
0x08102040 ,
0x0 ,
@ -439,7 +439,7 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
0x00600060 ,
0x00600060 ,
0x00600060 ,
0x0 ,
0x00000000 ,
0x00600020 ,
0x40010080 ,
0x08102040 ,