The Memory Protection Unit(MPU) allows to partition memory into regions and set individual protection attributes for each region. In absence of MPU a default map[1] will take effect. Add support for configuring MPU on Cortex-R, by reusing the existing support for Cortex-M processor. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I1002400.html Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>lime2-spi
Lokesh Vutla
6 years ago
committed by
Tom Rini
parent
4bbd6b1d94
commit
f2ef204312
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Cortex-R Memory Protection Unit specific code |
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* |
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com> |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <asm/armv7.h> |
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#include <asm/system.h> |
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#include <asm/barriers.h> |
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#include <linux/compiler.h> |
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#include <asm/armv7_mpu.h> |
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/* MPU Type register definitions */ |
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#define MPUIR_S_SHIFT 0 |
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#define MPUIR_S_MASK BIT(MPUIR_S_SHIFT) |
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#define MPUIR_DREGION_SHIFT 8 |
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#define MPUIR_DREGION_MASK (0xff << 8) |
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/**
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* Note: |
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* The Memory Protection Unit(MPU) allows to partition memory into regions |
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* and set individual protection attributes for each region. In absence |
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* of MPU a default map[1] will take effect. make sure to run this code |
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* from a region which has execution permissions by default. |
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* [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I1002400.html
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*/ |
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void disable_mpu(void) |
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{ |
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u32 reg; |
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reg = get_cr(); |
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reg &= ~CR_M; |
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dsb(); |
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set_cr(reg); |
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isb(); |
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} |
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void enable_mpu(void) |
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{ |
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u32 reg; |
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reg = get_cr(); |
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reg |= CR_M; |
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dsb(); |
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set_cr(reg); |
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isb(); |
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} |
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int mpu_enabled(void) |
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{ |
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return get_cr() & CR_M; |
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} |
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void mpu_config(struct mpu_region_config *rgn) |
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{ |
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u32 attr, val; |
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attr = get_attr_encoding(rgn->mr_attr); |
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/* MPU Region Number Register */ |
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asm volatile ("mcr p15, 0, %0, c6, c2, 0" : : "r" (rgn->region_no)); |
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/* MPU Region Base Address Register */ |
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asm volatile ("mcr p15, 0, %0, c6, c1, 0" : : "r" (rgn->start_addr)); |
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/* MPU Region Size and Enable Register */ |
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if (rgn->reg_size) |
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val = (rgn->reg_size << REGION_SIZE_SHIFT) | ENABLE_REGION; |
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else |
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val = DISABLE_REGION; |
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asm volatile ("mcr p15, 0, %0, c6, c1, 2" : : "r" (val)); |
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/* MPU Region Access Control Register */ |
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val = rgn->xn << XN_SHIFT | rgn->ap << AP_SHIFT | attr; |
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asm volatile ("mcr p15, 0, %0, c6, c1, 4" : : "r" (val)); |
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} |
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void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns) |
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{ |
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u32 num, i; |
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asm volatile ("mrc p15, 0, %0, c0, c0, 4" : "=r" (num)); |
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num = (num & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT; |
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/* Regions to be configured cannot be greater than available regions */ |
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if (num < num_rgns) |
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num_rgns = num; |
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/**
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* Assuming dcache might not be enabled at this point, disabling |
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* and invalidating only icache. |
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*/ |
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icache_disable(); |
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invalidate_icache_all(); |
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disable_mpu(); |
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for (i = 0; i < num_rgns; i++) |
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mpu_config(&rgns[i]); |
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enable_mpu(); |
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icache_enable(); |
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} |
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@ -0,0 +1,130 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. |
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*/ |
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#ifndef _ASM_ARMV7_MPU_H |
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#define _ASM_ARMV7_MPU_H |
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#ifdef CONFIG_CPU_V7M |
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#define AP_SHIFT 24 |
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#define XN_SHIFT 28 |
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#define TEX_SHIFT 19 |
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#define S_SHIFT 18 |
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#define C_SHIFT 17 |
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#define B_SHIFT 16 |
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#else /* CONFIG_CPU_V7R */ |
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#define XN_SHIFT 12 |
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#define AP_SHIFT 8 |
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#define TEX_SHIFT 3 |
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#define S_SHIFT 2 |
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#define C_SHIFT 1 |
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#define B_SHIFT 0 |
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#endif /* CONFIG_CPU_V7R */ |
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#define CACHEABLE BIT(C_SHIFT) |
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#define BUFFERABLE BIT(B_SHIFT) |
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#define SHAREABLE BIT(S_SHIFT) |
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#define REGION_SIZE_SHIFT 1 |
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#define ENABLE_REGION BIT(0) |
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#define DISABLE_REGION 0 |
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enum region_number { |
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REGION_0 = 0, |
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REGION_1, |
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REGION_2, |
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REGION_3, |
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REGION_4, |
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REGION_5, |
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REGION_6, |
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REGION_7, |
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}; |
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enum ap { |
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NO_ACCESS = 0, |
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PRIV_RW_USR_NO, |
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PRIV_RW_USR_RO, |
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PRIV_RW_USR_RW, |
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UNPREDICTABLE, |
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PRIV_RO_USR_NO, |
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PRIV_RO_USR_RO, |
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}; |
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enum mr_attr { |
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STRONG_ORDER = 0, |
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SHARED_WRITE_BUFFERED, |
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O_I_WT_NO_WR_ALLOC, |
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O_I_WB_NO_WR_ALLOC, |
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O_I_NON_CACHEABLE, |
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O_I_WB_RD_WR_ALLOC, |
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DEVICE_NON_SHARED, |
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}; |
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enum size { |
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REGION_8MB = 22, |
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REGION_16MB, |
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REGION_32MB, |
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REGION_64MB, |
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REGION_128MB, |
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REGION_256MB, |
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REGION_512MB, |
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REGION_1GB, |
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REGION_2GB, |
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REGION_4GB, |
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}; |
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enum xn { |
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XN_DIS = 0, |
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XN_EN, |
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}; |
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struct mpu_region_config { |
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uint32_t start_addr; |
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enum region_number region_no; |
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enum xn xn; |
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enum ap ap; |
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enum mr_attr mr_attr; |
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enum size reg_size; |
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}; |
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void disable_mpu(void); |
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void enable_mpu(void); |
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int mpu_enabled(void); |
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void mpu_config(struct mpu_region_config *reg_config); |
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void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns); |
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static inline u32 get_attr_encoding(u32 mr_attr) |
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{ |
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u32 attr; |
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switch (mr_attr) { |
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case STRONG_ORDER: |
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attr = SHAREABLE; |
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break; |
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case SHARED_WRITE_BUFFERED: |
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attr = BUFFERABLE; |
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break; |
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case O_I_WT_NO_WR_ALLOC: |
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attr = CACHEABLE; |
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break; |
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case O_I_WB_NO_WR_ALLOC: |
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attr = CACHEABLE | BUFFERABLE; |
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break; |
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case O_I_NON_CACHEABLE: |
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attr = 1 << TEX_SHIFT; |
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break; |
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case O_I_WB_RD_WR_ALLOC: |
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attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE; |
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break; |
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case DEVICE_NON_SHARED: |
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attr = (2 << TEX_SHIFT) | BUFFERABLE; |
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break; |
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default: |
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attr = 0; /* strongly ordered */ |
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break; |
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}; |
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return attr; |
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} |
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#endif /* _ASM_ARMV7_MPU_H */ |
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@ -1,66 +0,0 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. |
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*/ |
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enum region_number { |
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REGION_0 = 0, |
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REGION_1, |
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REGION_2, |
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REGION_3, |
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REGION_4, |
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REGION_5, |
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REGION_6, |
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REGION_7, |
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}; |
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enum ap { |
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NO_ACCESS = 0, |
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PRIV_RW_USR_NO, |
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PRIV_RW_USR_RO, |
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PRIV_RW_USR_RW, |
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UNPREDICTABLE, |
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PRIV_RO_USR_NO, |
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PRIV_RO_USR_RO, |
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}; |
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enum mr_attr { |
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STRONG_ORDER = 0, |
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SHARED_WRITE_BUFFERED, |
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O_I_WT_NO_WR_ALLOC, |
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O_I_WB_NO_WR_ALLOC, |
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O_I_NON_CACHEABLE, |
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O_I_WB_RD_WR_ALLOC, |
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DEVICE_NON_SHARED, |
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}; |
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enum size { |
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REGION_8MB = 22, |
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REGION_16MB, |
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REGION_32MB, |
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REGION_64MB, |
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REGION_128MB, |
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REGION_256MB, |
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REGION_512MB, |
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REGION_1GB, |
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REGION_2GB, |
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REGION_4GB, |
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}; |
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enum xn { |
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XN_DIS = 0, |
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XN_EN, |
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}; |
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struct mpu_region_config { |
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uint32_t start_addr; |
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enum region_number region_no; |
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enum xn xn; |
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enum ap ap; |
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enum mr_attr mr_attr; |
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enum size reg_size; |
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}; |
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void disable_mpu(void); |
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void enable_mpu(void); |
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void mpu_config(struct mpu_region_config *reg_config); |
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